Simple CPU Instruction Set Design.pptx

Simple CPU Instruction Set Design.pptx

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  Simple CPU Instruction SetDesign
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  • It actuallytakes very little hardware to implement a simple CPU. • An instruction fetch unit, which grabs the next instruction. The bits of the instruction are what activate different parts of the CPU circuit to make things happen. • A register file, from which operands are read, and results are written. • An arithmetic unit, which performs operations on the operands.
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  • There area few key tricks used throughout these designs: • In a circuit, feeding the output of the circuit back around to its own input, recycling the same values over and over. • Most CPUs operate on values of more than one bit. Using a single bus to represent multiple bits with a single line dramatically simplifies the circuit schematic compared to the physically more realistic approach of drawing separate wires for each bit. Logisim calls this "Data Bits"; most other tools call it a "bus".
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  • A multiplexorselects one input line from a set of inputs, based on "select line". For example, an 8-in mux has a 3 bit select input, which is a binary code indicating which of the 8 inputs to select as the output. Multiplexors are used: • In the register file, to select which register should provide input data for arithmetic. The register select lines are controlled by the input register portion of the instruction being executed. • In the arithmetic unit, to pick the output of one arithmetic circuit from those listed. The arithmetic select lines are controlled by the opcode portion of the instruction.
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  11-bit instruction set CPU
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  Pipelining in ComputerArchitecture Introduction- •A program consists of several number of instructions. •These instructions may be executed in the following two ways- 1.Non-Pipelined Execution 2.Pipelined Execution
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  Pipelining in ComputerArchitecture • 1. Non-Pipelined Execution • In non-pipelined architecture, • All the instructions of a program are executed sequentially one after the other. • A new instruction executes only after the previous instruction has executed completely. • This style of executing the instructions is highly inefficient.
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  Pipelining in ComputerArchitecture Example- • Consider a program consisting of three instructions. • In a non-pipelined architecture, these instructions execute one after the other as- • If time taken for executing one instruction = t, then- • Time taken for executing ‘n’ instructions = n x t
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  Pipelining in ComputerArchitecture 2. Pipelined Execution- • Multiple instructions are executed parallelly. • This style of executing the instructions is highly efficient. • Instruction Pipelining- • Instruction pipelining is a technique that implements a form of parallelism called as instruction level parallelism within a single processor. • A pipelined processor does not wait until the previous instruction has executed completely. • Rather, it fetches the next instruction and begins its execution.
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  Pipelining in ComputerArchitecture Pipelined Architecture • The hardware of the CPU is split up into several functional units. • Each functional unit performs a dedicated task. • The number of functional units may vary from processor to processor. • These functional units are called as stages of the pipeline. • Control unit manages all the stages using control signals. • There is a register associated with each stage that holds the data. • There is a global clock that synchronizes the working of all the stages. • At the beginning of each clock cycle, each stage takes the input from its register. • Each stage then processes the data and feed its output to the register of the next stage.
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  Pipelining in ComputerArchitecture • Four-Stage Pipeline 1.Instruction fetch (IF) 2.Instruction decode (ID) 3.Instruction Execute (IE) 4.Write back (WB) • To implement four stage pipeline, • The hardware of the CPU is divided into four functional units. • Each functional unit performs a dedicated task.
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  Pipelining in ComputerArchitecture • Stage-01: • First functional unit performs instruction fetch. • It fetches the instruction to be executed. • Stage-02: • Second functional unit performs instruction decode. • It decodes the instruction to be executed. • Stage-03: • Third functional unit performs instruction execution. • It executes the instruction. • Stage-04: • Fourth functional unit performs write back. • It writes back the result so obtained after executing the instruction.
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  Pipelining in ComputerArchitecture • Execution • Instructions of the program execute parallelly. • When one instruction goes from nth stage to (n+1)th stage, another instruction goes from (n-1)th stage to nth stage. • Phase-Time Diagram- • Phase-time diagram shows the execution of instructions in the pipelined architecture. • The following diagram shows the execution of three instructions in four stage pipeline architecture.
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  Pipelining in ComputerArchitecture • Time taken to execute three instructions in four stage pipelined architecture = 6 clock cycles. In non-pipelined architecture, Time taken to execute three instructions would b = 3 x Time taken to execute one instruction = 3 x 4 clock cycles = 12 clock cycles
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  Pipelining in ComputerArchitecture Performance of Pipelined Execution • The following parameters serve as criterion to estimate the performance of pipelined execution- • Speed Up • Efficiency • Throughput