Embedded Systems Design
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June 2014.
Wilmshurst T., Fast and Effective Embedded System Design applying the
ARM mbed, Elsevier, 2017.
Jonathan W.V., Embedded systems: Introduction to Arm(r) Cortex-M
Microcontrollers(5e), Createspace Independent publishing platform,
June 2017.
UM10360, LPC 176x/5x User Manual, NXP Semiconductors, Rev. 3.1,
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Joseph V., A definitive Guide to ARM Cortex-M3 and Cortex-M4
processors (3e), Elsevier, 2014.
Classification of the controllers
• The architectural design of the CPU for execution of instructions
• Architecture of a micro computer or a micro controller refers to the
arrangement of the CPU with respect of the RAM and ROM.
The architectural design of the CPU for execution of
instructions
• What is RISC?
• A reduced instruction set computer is a computer that only uses simple
commands that can be divided into several instructions that achieve low-
level operation within a single CLK cycle, as its name proposes “Reduced
Instruction Set”.
• What is CISC?
• A complex instruction set computer is a computer where single
instructions can perform numerous low-level operations like a load from
memory, an arithmetic operation, and a memory store or are
accomplished by multi-step processes or addressing modes in single
instructions, as its name proposes “Complex Instruction Set ”.
RISC CISC
1. RISC stands for Reduced Instruction Set Computer. 1. CISC stands for Complex Instruction Set Computer.
2. CSIC processor has complex instructions that take up multiple clocks for execution. take 2-
2. RISC processors have simple instructions taking about takes few cycles 10 cycles.
3. It has no memory unit and uses separate hardware to implement instructions.. 3. It has a memory unit to implement complex instructions.
4. It has a hard-wired unit of programming. 4. It has a microprogramming unit.
5. The instruction set is reduced i.e. it has only a few instructions in the instruction set. 5. The instruction set has a variety of different instructions that can be used for complex
Many of these instructions are very primitive. operations.
6. CISC has many different addressing modes and can thus be used to represent higher-level
6 Supports few addressing modes. programming language statements more efficiently.
7. Complex addressing modes are synthesized using the software. 7. CISC already supports complex addressing modes
8. Multiple register sets are present 8. Only has a single register set
9. RISC processors are highly pipelined 9. They are normally not pipelined or less pipelined
10. The complexity of RISC lies with the compiler that executes the program 10. The complexity lies in the microprogram
11. Execution time is very less 11. Execution time is very high
12. The decoding of instructions is simple. 12. Decoding of instructions is complex
13. It does not require external memory for calculations 13. It requires external memory for calculations
14. The most common RISC microprocessors are Alpha, ARC, ARM, AVR, MIPS, PA- 14. Examples of CISC processors are the System/360, VAX, PDP-11, Motorola 68000 family,
RISC, PIC, Power Architecture, and SPARC. AMD, and Intel x86 CPUs.
15 RISC architecture is used in high-end applications such as video processing, 15. CISC architecture is used in low-end applications such as security systems, home
telecommunications, and image processing. automation, etc.
• As a CPU needs to communicate with the various memory and input-output
devices (I/O) as we know data between the processor and these devices flow
with the help of the system bus.
• Memory BUS: Is for Information transfer between memory and the CPU
• IO BUS: Between CPU and IO devices through IO interface.
• Many computers uses common single bus for both
a. Separate control lines for each function
b. Common address and data lines for both functions.
• Some computer uses two separate buses
• one to communicate with memory and the other one with IO interface
• Memory Mapped I/O –
• In this case every bus in common due to which the same set of
instructions work for memory and I/O.
• Isolated I/O –IO mapped IO
• In which we Have common bus(data and address) for I/O and memory
but separate read and write control lines for I/O.
ISOLATED I/O MEMORY MAPPED I/O
Memory and I/O have separate address space Both have same address space
Due to addition of I/O addressable memory become less for
All address can be used by the memory
memory
Separate instruction control read and write operation in I/O and
Same instructions can control both I/O and Memory
Memory
In this I/O address are called ports. Normal memory address are for both
More efficient due to separate buses Lesser efficient
Larger in size due to more buses Smaller in size
It is complex due to separate separate logic is used to control both. Simpler logic is used as I/O is also treated as memory only.
Architecture of a micro computer or a micro controller refers to
the arrangement of the CPU with respect of the RAM and ROM.
• Von-Neuman and Harvard architecture are the two ways through which the micro controller can
have its arrangement of the CPU with RAM and ROM.
Point of Comparison Harvard Architecture Von Neumann Architecture
In Von-Neumann architecture,
In Harvard architecture, the CPU
there is no separate data and
is connected with both the data
Arrangement program memory. Instead, a
memory (RAM) and program
single memory connection is
memory (ROM), separately.
given to the CPU.
In contrast to the Harvard
It requires more hardware since it
architecture, this requires less
Hardware requirements will be requiring separate data and
hardware since only a common
address bus for each memory.
memory needs to be reached.
Von-Neumann Architecture
Space requirements This requires more space.
requires less space.
Speed of execution is faster Speed of execution is slower since
Speed of execution because the processor fetches data it cannot fetch the data and
and instructions simultaneously . instructions at the same time.
It results in wastage of space since
Space is not wasted because the
if the space is left in the data
space of the data memory can be
Space usage memory then the instructions
utilized by the instructions memory
memory cannot use the space of
and vice-versa.
the data memory and vice-versa.
Controlling becomes complex since Controlling becomes simpler since
Controlling data and instructions are to be either data or instructions are to be
fetched simultaneously. fetched at a time.
• The following two factors can be important in choosing a
microcontroller:
• · Chip characteristics: Some of the factors in choosing a
microcontroller chip are
• clock speed, power consumption, price, and on-chip memories and
peripherals.
• · Available resources: Other factors in choosing a microcontroller
include the IDE
• compiler, legacy software, and multiple sources of production.
ARM architecture
• Why do we need to study the Architeture?
• To program in Assembly language, we must understand the registers
and architecture of a given CPU and the role they play in processing
data.
• we look at the general purpose registers (GPRs) of the ARM, CPSR and
other registers
• simple instructions used for transfering the data between the
registers and the memory
ARM registers
• Registers are used for arithmetic and for logical operations.
• In the CPU, registers are used to store information temporarily
• That information could be a byte of data to be processed, or an
address pointing to the data to be fetched.
• All of ARM registers are 32-bit wide.
• These range from the MSB (most-significant bit) D31 to the LSB (least-
significant bit) D0.
• The 32-bit data size of the ARM is often referred as word.
• The general purpose registers in ARM used to store the data during
the operation
• The general purpose registers in ARM are the same as the
accumulator in other microprocessors
Special function registers in ARM
• In ARM the R13, R14, R15, and CPSR (current program status register)
registers are called SFRs (special function registers)
• R13-> Stack pointer
• R14-> Link register
• R15-> Program counter
• CPSR-> stores the status of the program after execution of a given
instruction.
• Since each one is dedicated to a specific function.
Program Counter in the ARM
• One of the most important register in the ARM microcontroller is the PC
(program counter) .
• the R15 is the program counter
• The program counter is used by the CPU to point to the address of the next
instruction to be executed
• As the CPU fetches the opcode from the program memory, the program
counter is incremented automatically to point to the next instruction
• The wider the program counter, the more memory locations a CPU can access
• a 32-bit program counter can access a maximum of 4G (2^32 = 4G) bytes of
program memory locations
Memory space allocation in the
ARM
• The ARM has 4G bytes of directly accessible memory space. This
memory space has addresses 0 to 0xFFFFFFFF.
• The 4G bytes of memory space can be divided into five sections.
• On-chip peripheral and I/O registers:
• On-chip data SRAM:
• On-chip EEPROM
• On-chip Flash ROM
• Off-chip DRAM space
Memory address calculation
• Starting address is calculated by writing all zero
• Ending address by writing all 1s
• Finally represent it in Hexadecimal
example
On-chip peripheral and I/O
registers
• This area is dedicated to general purpose I/O (GPIO) and special
function registers (SFRs) of peripherals
• such as timers serial communication, ADC, and so on.
• In other words, ARM uses memory-mapped I/O.
• The function and address location of each SFR is fixed by the chip
vendor at the time of design because it is used for port registers of
peripherals
On-chip data SRAM
• A RAM space ranging from a few kilobytes to several hundred kilobytes is set
aside mainly for data storage
• Even within the same family, the size of the data SRAM space varies from chip
to chip.
• The data RAM space is used for data variables and stack and is accessed by
the microcontroller instructions.
• one can also buy or design an ARM-based system in which the RAM space is
used for both data and program codes. Example: x86 PCs
• Microsoft Windows 8 uses such a system for ARM-based Tablet computers.
• The data RAM space is read/write memory used by the CPU for storage of
data variables, and stack
On-chip EEPROM
• A block of memory from 1K bytes to several thousand bytes is set
aside for EEPROM memory
• EEPROM used most often for saving critical data.
On-chip Flash ROM
• A block of memory from a few kilobytes to several hundred kilobytes
is set aside for program space
• The program space is used for the program code.
• The Flash memory of code ROM is under the control of the PC
(program counter)
• A given ARM chip has the following address assignments. Calculate
the space and the amount of memory given to each section.
• (a) Address range of 0x00100000 – 0x00100FFF for EEPROM
• (b) Address range of 0x40000000 – 0x40007FFF for SRAM
• (c) Address range of 0x00000000 – 0x0007FFFF for Flash
• (d) Address range of 0xFFFC0000 – 0xFFFFFFFF for peripherals
ARM's method to move any (large) integer value into a register
One ARM instruction does not have enough space left to encode integer values that
are large
•Because the ARM instructions is fixed length (every ARM instruction is 4 bytes):
•In order to move a large binary number (that requires more bits to encode),
• we break the binary number into 2 (equal) halves:
• Consider the following example:
• ldr r1, =0xffffffff
• ldr r2, =0x00000001
• adds r0, r1, r2
• The result of the operation would be 0x100000000, but the top bit is
lost because it does not fit into the 32-bit destination register and so
the real result is 0x00000000. In this case, the flags will be set as
follows:
Flag Explanation
The result is 0, which is considered positive, and so the N (negative) bit
N=0
is set to 0.
Z=1 The result is 0, so the Z (zero) bit is set to 1.
We lost some data because the result did not fit into 32 bits, so the
C=1
processor indicates this by setting C (carry) to 1.
From a two's complement signed-arithmetic viewpoint, 0xffffffff really
V=0 means -1, so the operation we did was really (-1) + 1 = 0. That
operation clearly does not overflow, so V (overflow) is set to 0.
Flags: N (negative): 0
Z (zero) : 1
C (carry) : 1
V (overflow): 0
Condition Codes:
EQ: 1
NE: 0
CS: 1
CC: 0
MI: 0
PL: 1
VS: 0
VC: 1
HI: 0
LS: 1
GE: 1
LT: 0
GT: 0
LE: 1
• Bubble Sort is the simplest sorting algorithm that works by repeatedly
swapping the adjacent elements if they are in wrong order.
• Example:
First Pass:
( 5 1 4 2 8 ) –> ( 1 5 4 2 8 ), Here, algorithm compares the first two
elements, and swaps since 5 > 1.
( 1 5 4 2 8 ) –> ( 1 4 5 2 8 ), Swap since 5 > 4
( 1 4 5 2 8 ) –> ( 1 4 2 5 8 ), Swap since 5 > 2
( 1 4 2 5 8 ) –> ( 1 4 2 5 8 ), Now, since these elements are already in
order (8 > 5), algorithm does not swap them.
• Second Pass:
( 1 4 2 5 8 ) –> ( 1 4 2 5 8 )
( 1 4 2 5 8 ) –> ( 1 2 4 5 8 ), Swap since 4 > 2
( 1 2 4 5 8 ) –> ( 1 2 4 5 8 )
( 1 2 4 5 8 ) –> ( 1 2 4 5 8 )
• ldr r0, =result
• mov r3, #10
• sub r3, r3, #1
• mov r9, r3 ; R9 contain no of passes
• mov r5, r0
• mov r4, r3 ; R4 contains no of compare in a pass
• inner_loop
• ldr r6, [r5], #4
• ldr r7, [r5]
• cmp r7, r6 ; swap without swp instruction
• strls r6, [r5]
• strls r7, [r5, #-4]
•
• subs r4, r4, #1
• bne inner_loop
• sub r3, #1
• subs r9, r9, #1
• bne outer_loop
• A recursive procedure is one that calls itself. There are two kind of
recursion: direct and indirect. In direct recursion, the procedure calls
itself and in indirect recursion, the first procedure calls a second
procedure, which in turn calls the first procedure.
• Recursion could be observed in numerous mathematical algorithms.
For example, consider the case of calculating the factorial of a
number. Factorial of a number is given by the equation −
Fact (n) = n * fact (n-1) for n > 0
• For example: factorial of 5 is 1 x 2 x 3 x 4 x 5 = 5 x factorial of 4 and
this can be a good example of showing a recursive procedure. Every
recursive algorithm must have an ending condition, i.e., the recursive
calling of the program should be stopped when a condition is fulfilled.
In the case of factorial algorithm, the end condition is reached when n
is 0.
• ldr r0,=05
• bl factorial
• stop b stop
•
• factorial
• push {r4,lr} ;//push r4 and lr onto the top of the stack
• mov r4,r0;//make a copy of r0
• cmp r0,#0 ;//compare r0 with 0
• bne not_zero ;//branch to not_zero if not equal
• mov r0,#1 ;//r0=1
• b last
• not_zero
• sub r0,r0,#1 ;//r0=r0-1
• bl factorial ;//call recursively factorial
• mov r1,r4
• mul r0,r0,r1 ;//r0=r0*r1
• last
• pop {r4,lr} ;//pop <=> ldmia sp! {r4,lr}
• bxlr