Module 3:

Fabrication and
Layout
CMOS Fabrication
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or
etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

2
Inverter Cross-section
• Typically use p-type substrate for nMOS transistors
• Requires n-well for body of pMOS transistors VDD

A Y

A
GND VDD SiO2
GND
Y
n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

This picture is not complete without the p-substrate tap and n-well tap 
 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD (WHY ??)
• Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode
• Use heavily doped well and substrate contacts / taps

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor n diffusion

5
Inverter Top View

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

6
The entire design of a chip is defined by
masks: a mask set

7
Detailed Mask Views

• Six masks n well

• n-well
• Polysilicon Polysilicon

• n+ diffusion
• p+ diffusion n+ Diffusion

• Contact p+ Diffusion

• Metal Contact

Metal
To understand what a mask is, we must describe the fabrication steps
Fabrication
• Chips are built in huge factories called fabs
• Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
• Cover wafer with protective layer of SiO2 (oxide)
• Remove layer where n-well should be built
• Implant or diffuse n dopants into exposed wafer
• Strip off SiO2

p substrate
Oxidation
• Grow SiO2 on top of Si wafer
• 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate
Photoresist
• Spin on photoresist
• Photoresist is a light-sensitive organic polymer
• Softens where exposed to light

Photoresist
SiO2

p substrate
 First Mask !! (N-Well)
Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist
Top View of Mask

Cross-section view of substrate

Photoresist
SiO2

p substrate
Etch
• Etch oxide with hydrofluoric acid (HF)
• Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate
Strip Photoresist
• Strip off remaining photoresist
• Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate
n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
• Place wafer in furnace with arsenic gas
• Heat until As atoms diffuse into exposed Si
• Ion Implanatation
• Blast wafer with beam of As ions
• Ions blocked by SiO2, only enter exposed Si

SiO2

n well
Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate
Polysilicon : Gate Regions

• Deposit very thin layer of gate oxide

• < 20 Å (6-7 atomic layers). 1 Å = 10-10 m (angstrom)
• Chemical Vapor Deposition (CVD) of silicon layer
• Place wafer in furnace with Silane gas (SiH4)
• Forms many small crystals called polysilicon
• Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
Polysilicon : Gate Regions

Photoresist

n well
p substrate
Polysilicon : Gate Regions

Polysilicon
mask

Photoresist

n well
p substrate
Polysilicon : Gate Regions

Polysilicon
mask

n well
p substrate
Polysilicon : Gate Regions

Polysilicon
Thin gate oxide

n well
p substrate
n+ Diffusion Regions

• Grow oxide to be used as mask

n well
p substrate
Self-Aligned Process
• Use oxide and masking to expose where n+ dopants
should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate
n+ Diffusion Regions

• Apply photoresist- remove oxide where we want n+ diffusion

• N-diffusion forms nMOS source, drain, and n-well contact

n+ Diffusion

Photoresist

n well
p substrate
n+ Diffusion Regions

 Historically, dopants were diffused

 Today: ion implantation
 But regions are still called diffusion
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
Source and Drain are automatically
aligned (self-aligned)

n+ n+ n+

n well
p substrate
N-diffusion cont.
• Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate
P-Diffusion
• Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate
Note: you could do the p+ diffusion before the n+ diffusion.
These are the only steps that you can interchange their order.
Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate
 Meta
l
• Coat entire surface with metal (aluminum)
• Apply photo resist as before
• Use the last mask to pattern the metal connections
throughout the integrated circuit
 Metal

Metal
Mask

Aluminum
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
 Metal

Metal
Mask

Aluminum
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
 Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
gate gate
 (i)
cross-sections while
manufacturing gate and n+
diffusion regions
(j)

(k)

(L)

(m)

(n)
(o)

(p)

(q)
 Top view to side view

GND Vcc

Substrate

Can you do the rest?

 VDD

Y
A

B
n+ n+ n+ p+ p+

n well

p- substrate

3: Fabrication & Layout 41

 Stick Diagrams
Easy way to draw a layout and estimate its dimensions (size)

• help plan layout quickly

• need not be to scale
• Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3
 No need to draw the n-well (or p-well).
Assume they are there.

n-well
NAND
This stick diagram
is a 2 input NAND

Not exactly the same.

Where’s the difference?

B A B A

vdd Label the sources and drains?

x x x
x Remember from Module 2:
out
NMOS: the source is lower
x x
voltage than the drain.
B A PMOS: the source is higher
gnd x
voltage than the drain
 2 input NOR gate

vdd x
x x
A
B
Y
x x x

gnd x x

Label sources and drains?

 2 input NOR gate

vdd

x x
A
B
Y
x x x

gnd
x
Try: )
 )

x
vdd
x x x x x

x x x
gnd
x
A B C D
 )
C and D are
now here

vdd
x
x x x x x

Y
x x x
gnd
x
A B C D
 )

vdd
x
x x x x x

Y
x x x
gnd
x
A B C D
 )

vdd

a nd d?
e
“C” itch
f
a t i sw
h e
W ” ar
“D

gnd

x
 )

How to easily determine order of

polysilicon gates A,B,C,D ?
 )

Find a continuous path that connects all transistor paths

(sources-drains) on the NMOS side. Then see if this same
path can be implemented on the PMOS side.

Can this be
Yes. Therefore A,C,D,B is
done for the
one solution
PMOS ?

What about the order: A, B, C ,D ?

This order cannot be done on the NMOS side
(or the PMOS side) so it is not a solution.

Let’s try A, C, D, B …..

 )

vdd

gnd

x
 )

vdd

a n d “d” in the
Writ e “ s ”
r a s t h e lo op that gnd
same orde t h e schemat
ic
o s e f o r
you ch

x
 )

Label “s” and “d” for PMOS:

Make connections
vdd
x x x x x

x x x x

gnd
 )

Another solution, probably easier. Start from “B”

Order: B, A, C, D
Does this work with the B, A, C, D is a solution
PMOS ?
Order (PMOS): B, A, C, D
 )

Try B, A, C, D
vdd

gnd
Try:𝑦 =( 𝐴 + 𝐵 + 𝐶 ) ∙ 𝐷
Try:𝑦 =( 𝐴 + 𝐵 + 𝐶 ) ∙ 𝐷

Path: A, B, C, D

Path A,B,C,D is possible for

both nMOS and pMOS
networks, therefore this is
one possible solution

Path: A,B,C,D

Example: Path A, D, C, B is
possible for pMOS network,
but not for nMOS.
Try it !!
𝑦 =( 𝐴 + 𝐵 + 𝐶 ) ∙ 𝐷

Try path A, D, C, B
vdd

PMOS is ok !
NMOS is not ok!

gnd
Look at “D”. Both sides here are sharing a
diffusion with another nMOS. But this is not
the same as the schematic. It can’t be done!
Try:𝑦 =( 𝐴 + 𝐵 + 𝐶 ) ∙ 𝐷
Try path A, B, C, D

Notice the order of sources and

drains- same as the path

This works!
What is this? Y = ?
What is this? Y = ?
What is this? Y = ?
What is this? Y = ?
What is this? Y = ?
What is this? Y = ?
Another Example: 𝑌 = 𝐴 ∙ ( 𝐵+ 𝐶 ) + 𝐷 ∙ 𝐸

Choose a path that can work for both nMOS and pMOS

C, B, A, E, D works for both

NMOS network
3: Fabrication & Layout 69
Another Example: 𝑌 = 𝐴 ∙ ( 𝐵+ 𝐶 ) + 𝐷 ∙ 𝐸

C, B, A, E, D

Done !

3: Fabrication & Layout 70

Design rules for layout
• The major determination of cost in the fabrication process is
the minimum feature size- which is the distance between the
source and the drain.
• This is the minimum width of the polysilicon gate.
• The “process” cannot make this width any smaller.
• We often name the process by this minimum polysilicon
width (i.e., a “one-micron process”)
• We make design rules in terms of ½ of this width and call it
lamda (l) ; l = 0.3 mm in 0.6 mm process
• If we describe our design in terms of l, then if using a
different process, the same design can be used even if the
value of l is different. This is called “scalable CMOS”.

3: Fabrication & Layout 71

 Simplified Design
Rules
• Conservative rules to get you started; your design will be ok if within
these guidelines. These are all minimum.
• The Metal tracks take up the most space- one track is 8λ
Don’t let metal tracks get closer than
Minimum metal width is 4λ
4λ
.. And so on…

3: Fabrication & Layout 72

Gate Layout
• Layout can be very time consuming
• Design gates to fit together nicely
• Build a library of standard cells
• Standard cell design methodology
• VDD and GND should abut (standard height)
• Adjacent gates should satisfy design rules
• nMOS at bottom and pMOS at top
• All gates include well and substrate contacts

3: Fabrication & Layout 73

Example: Inverter

note: missing
contact(s) for
the input A.

3: Fabrication & Layout 74

Wiring Tracks
• A wiring track is the space required for a wire
• 4 l width, 4 l spacing from neighbor = 8 l pitch
• Transistors also consume one wiring track

3: Fabrication & Layout 75

Well spacing
• Wells must surround transistors by 6 l
• Implies 12 l between opposite transistor types
• Leaves room for one wire track

3: Fabrication & Layout 76

Example: Area Estimation for 3 input NAND (NAND3)

Width: 3 complete metal tracks, then

add 1 to take it to the outside edges.
𝟖𝝀
The width is approximately

note: missing 𝟖 𝝀
contact(s) for the
inputs A,B,C. Y
𝟖𝝀
Height: 4 complete metal tracks, then 𝟑𝟔 𝝀
add 1 to take it to the outside edges.
𝟖𝝀
The height is approximately

Area ≈ 32 l by 40 l

3: Fabrication & Layout 77

• Sketch a stick diagram for the following and estimate area
•
𝑌 = ( 𝐴+𝐵+𝐶 ) ∙ 𝐷
VDD
A B C D

6 tracks =
48 
Y

GND
5 tracks =
40 

CMOS VLSI Design 4th Ed.

3: Fabrication & Layout 78
• Sketch a stick diagram for the following and estimate area
•
𝑌 = ( 𝐴+𝐵+𝐶 ) ∙ 𝐷 𝐻𝑒𝑖𝑔h𝑡 : ( 5+1 ) × 8 𝜆=48 𝜆
VDD 𝑊𝑖𝑑𝑡h : ( 4+1 ) × 8 𝜆=40 𝜆
A B C D
1
Area =
2
3 Y
1 4
2 3 4

5
GND

CMOS VLSI Design 4th Ed.

3: Fabrication & Layout 79
 From before:

1
2

5
1 2 3 4 5

6
7

Therefore: Height =
Therefore: Width =

Area =
3: Fabrication & Layout 80