Decoder
• A decoder is a combinational circuit that converts binary
information from n input lines to a maximum of 2n unique output
lines.
• If the n -bit coded information has unused combinations, the
decoder may have fewer than 2n outputs.
• The name decoder is also used in conjunction with other code
converters, such as a BCD-to-seven-segment decoder.
• As an example, consider the three-to-eight-line decoder circuit of
Fig. 1 . The three inputs are decoded into eight outputs, each
representing one of the minterms of the three input variables.
• The three inverters provide the complement of the inputs, and each
one of the eight AND gates generates one of the minterms.
• . A particular application of this decoder is binary-to-octal
conversion.
• For each possible input combination, there are seven outputs
that are equal to 0 and only one that is equal to 1. The output
whose value is equal to 1 represents the minterm equivalent
of the binary number currently available in the input lines.
• n. A two-to-four-line decoder with an enable input
constructed with NAND gates is shown in Fig. 4.2.
• The circuit operates with complemented outputs and a
complement enable input. The decoder is enabled when
E is equal to 0 (i.e., active-low enable).
• As indicated by the truth table, only one output can be equal to 0
at any given time; all other outputs are equal to 1.
• The output whose value is equal to 0 represents the minterm
selected by inputs A and B .
• Decoders with enable inputs can be connected together to form a
larger decoder circuit.
• Figure 4.20 shows two 3-to-8-line decoders with enable inputs
connected to form a 4-to-16-line decoder.
• When w 0, the top decoder is enabled and the other is disabled.
• The bottom decoder outputs are all 0’s, and the top eight outputs
generate minterms 0000 to 0111.
• When w 1, the enable conditions are reversed: The bottom
decoder outputs generate minterms 1000 to 1111, while the
outputs of the top decoder are all 0’s.
4 * 16decoder constructed with two 3 * 8decoders
Combinational Logic Implementation
• A decoder provides the 2n minterms of n input variables.
• The procedure for implementing a combinational circuit by
means of a decoder and OR gates requires that the Boolean
function for the circuit be expressed as a sum of minterms.
• s. A decoder is then chosen that generates all the minterms of
the input variables. The inputs to each OR gate are selected
from the decoder outputs according to the list of minterms of
each function. This procedure will be illustrated by an
example that implements a full-adder circuit.
• From the truth table of the full adder.
• we obtain the functions for the combinational circuit in sum-of-
minterms form: S(x, y, z) = (1, 2, 4, 7) C(x, y, z) = (3, 5, 6, 7).
•
Encoders
• An encoder is a digital circuit that performs the inverse
operation of a decoder. An encoder has 2n (or fewer) input
lines and n output lines.
• . The output lines, as an aggregate, generate the binary
code corresponding to the input value.
• An example of an encoder is the octal-to-binary encoder
whose truth table is given in Table. It has eight inputs (one
for each of the octal digits) and three outputs that
generate the corresponding binary number.
• . It is assumed that only one input has a value of 1 at any
given time
• The encoder can be implemented with OR gates whose inputs are determined directly
from the truth table. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7.
Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. These
conditions can be expressed by the following Boolean output functions:
• z = D1 + D3 + D5 + D7
• y = D2 + D3 + D6 + D7
• x = D4 + D5 + D6 + D7
• The encoder
• can be implemented with three OR gates.
• Priority Encoder :
• A priority encoder is an encoder circuit that includes the priority
function.
• The operation of the priority encoder is such that if two or more
inputs are equal to 1 at the same time, the input having the
highest priority will take precedence.
• The truth table of a four-input priority encoder is given in Table
4.8 .
• . In addition to the two outputs x and y , the circuit has a third
output designated by V ; this is a valid bit indicator that is set to
1 when one or more inputs are equal to 1. If all inputs are 0,
there is no valid input and V is equal to 0. The other two
outputs are not inspected when V equals 0 and are specified as
don’t-care conditions.
• According to Table 4.8 , the higher the subscript number, the
higher the priority of the input.
• . Input D3 has the highest priority, so, regardless of the values
of the other inputs, when this input is 1, the output for xy is 11
(binary 3).
• D2 has the next priority level.
• The output is 10 if D2 = 1, provided that D3 = 0, regardless of
the values of the other two lower priority inputs. The output for
D1 is generated only if higher priority inputs are 0, and so on
down the priority levels.