3.

BASIC INPUT/OUTPUT
3.1 Accessing I/O devices
Processor Memory

Bus

I/O device 1 I/O device n

•Multiple I/O devices may be connected to the processor and the

memory via a interconnection network. That interconnection
network is called BUS.
•Bus consists of three sets of lines to carry address, data and
control signals.
•Each I/O device is assigned an unique address.
•To access an I/O device, the processor places the address on the
address lines.
•The device recognizes the address, and responds to the control
 Accessing I/O devices (contd..)
I/O devices and the memory may share the same
address space is called Memory-mapped I/O.
Any machine instruction that can access memory
can be used to transfer data to or from an I/O
device.
I/O devices and the memory may have different
address spaces is called Isolated I/O.
Special instructions used to transfer data to and from I/O
devices.
In fact, address lines may be shared between I/O devices and
memory, with a control signal to indicate whether it is a
memory address 3 or an I/O address.
Memory-Mapped I/o
• With memory-mapped I/O, any machine instruction
that can access memory can be used to transfer data
to or from an I/O device.
• For example, if DATAIN is the address of a register in
an input device, the instruction
• Load R2, DATAIN
• reads the data from the DATAIN register and loads
them into processor register R2.
• Similarly, the instruction
• Store R2, DATAOUT
• sends the contents of register R2 to location
DATAOUT, which is a register in an output device.
I/O device Interface (contd..)

Computer System includes special hardware components

between the CPU and I/O to supervise and synchronize all
I/O transfer. These components are called Interface.
I/O device Interface (contd..)
• I/O interface is a H/W device it provides a means of data
transfer between CPU , memory and I/O devices. Each device
has its own interface.
•I/O device is connected to the bus using an I/O interface circuit
which has:
- Address decoder, control register, and data and
status registers.
•Address decoder decodes the address placed on the address
lines thus enabling the device to recognize its address.
•Data register may server as buffer for data transfer. It holds
the data being transferred to or from the processor.
•Status register : provides status information to the CPU about
the I/O device.
•Control Register: is used by the CPU to control and configure
the device.

I/O registers are accessed by program instructions as if they are memory locations
Program-Controlled I/O
• I/O devices transfer data at a slower rate than the processor
speed.
• This creates a need to synchronize data transfer between
processor and I/O devices
• Two mechanisms used to synchronize data transfer between
processor and I/O devices:
(i) Program-controlled I/O, (ii) Interrupts
Program-Controlled I/O
Program-controlled I/O: In this method, the I/O device does not
have direct access to memory.
To transfer from I/O device to memory requires the execution of
several instructions by the CPU.
• Processor repeatedly monitors a status flag to check if the I/O
device is ready or not. This is called Signaling protocol.
• For example, a processor sending data to a display needs to
check whether the display is ready to receive the next character.
• Ex2: An input character is obtained from the keyboard in a
similar way. i.e. the CPU waits for a signal that indicates a key has
been pressed and that is available in an interface data register.
Then CPU proceeds to read the code.
• This is also called “polling” the I/O device
Keyboard Interface
Display interface
Data transfer from I/O to CPU
• Figure shows an example of data transfer from an I/O device through its interface into
memory via the CPU.
• The device places a byte of data, when available, in the I/O bus and enables its data valid line.
• The interface accepts the byte into its data register and enables its data accepted line.
• A flag bit is then set in its status register by the interface.
• The device now disables the data valid line, and it will not transfer another byte until the data
accepted line is disabled and flag bit is reset by the interface.
• An I/O Program check the flag bit in the status register to determine if a byte is placed in the
data register by the I/O device.
• By reading the status register into a CPU register and checking the value of the flag bit, this
can be done.
• When the flag bit is set to 1, the CPU reads the data from data register and transfers to the
memory by executing STORE instruction.
• The flag bit is then set to 0 by interface.
• When the flag bit is 0, the interface disables the data accepted line and the device can then
transfer the next byte.
• Thus the following 4 steps are executed by the CPU to transfer each byte:
1. Read the status register of interface unit.
2. Check the flag bit of the status register and go to step 3 if it is set to 1; otherwise loop back to
step1.
3. Read the data register of interface for data.
4. Send the data to the memory by executing store instruction.
 Keyboard Interface
• The keyboard includes a circuit that responds to a key being pressed
by producing the code for the corresponding character that can be
used by the computer.
• We will assume that ASCII code is used, in which each character
code occupies one byte.
• Let KBD_DATA be the address label of an 8-bit register that holds
the generated character.
• Also, let a signal indicating that a key has been pressed be provided
by setting to 1 a flip-flop called KIN, which is a part of an eight-bit
status register, KBD_STATUS.
• The processor can read the status flag KIN to determine when a
character code has been placed in KBD_DATA.
• When the processor reads the status flag to determine its state, we
say that the processor polls the I/O device
 Display Interface
• The display includes an 8-bit register, which we
will call DISP_DATA, used to receive characters
from the processor.
• It also must be able to indicate that it is ready to
receive the next character; this can be done by
using a status flag called DOUT, which is one bit
in a status register, DISP_STATUS.
 Example
• Let us consider the details of the input process.
• When a key is pressed, the keyboard circuit places the ASCII-
encoded character into the KBD_DATA register.
• At the same time, the circuit sets the KIN flag to 1. Meanwhile,
the processor is executing the I/O program which continuously
checks the state of the KIN flag.
• When it detects that KIN is set to 1, it transfers the contents of
KBD_DATA into a processor register.
• Once the contents of KBD_DATA are read, KIN must be cleared to
0, which is usually done automatically by
the interface circuit.
• If a second character is entered at the keyboard, KIN is again set
to 1 and the process repeats.
 READWAIT: Read the KIN flag
Branch to READWAIT if KIN = 0
Transfer data from KBD_DATA to R5
• which reads the character into processor register R5.

• Note: We assume that the initial state of KIN is 0 and the initial state of DOUT is 1. This initialization is
normally performed by the device control circuits when power is turned on.
• In computers that use memory-mapped I/O, data can be transferred between
these registers and the processor using instructions such as Load, Store, and
Move.
• For example, the contents of the keyboard character buffer KBD_DATA can be
transferred to register R5 in the processor by the instruction
• LoadByte R5, KBD_DATA
• Similarly, the contents of register R5 can be transferred to DISP_DATA by the
instruction
– StoreByte R5, DISP_DATA

• The LoadByte and StoreByte operation codes signify that the operand size is a
byte, to distinguish them from the Load and Store operation codes that we have
used for word operands.
 Display
• when characters are transferred from the processor to the
display. When DOUT is equal to 1, the display is ready to receive
a character.
• Under program control, the processor monitors DOUT, and
when DOUT is equal to 1, the processor transfers an ASCII-
encoded character to DISP_DATA.
• The transfer of a character to DISP_DATA clears DOUT to 0.
When the display device is ready to receive a second character,
DOUT is again set to 1.
• This can be achieved by performing the operations:
WRITEWAIT : Read the DOUT flag
Branch to WRITEWAIT if DOUT = 0
Transfer data from R5 to DISP_DATA
Interrupts
Interrupts
What is an Interrupt ?
Disturbing the CPU what it is presently doing and transfer the control some where
else.
• i.e. When an interrupt can occurs, the control transfers from currently running
program to another service routine.
• Again the control returns to the original program after the service program is
executed.
What happens when interrupt occurs?
• It is same way as subroutine call.
• Whenever interrupt occurs, the CPU completes the execution of the current
instruction and, save Program Counter (PC) value and present Status of CPU (PS
Register) is stored in memory, and then starts the execution of interrupt service
Routine(ISR).
• ISR tells the processor, what to do when an interrupt occurs.
• For every interrupt, there must be an ISR available in main memory.
• All ISR starting addresses are going to be placed in one table is called IVT.
(Interrupt Vector Table)
Sequence of Steps as follows when an interrupt occurs:
1. Execute the current instruction, and saves the PC in stack.
2. It saves the current status of PS register.
3. It jumps to the memory location of the IVT, identify ISR entry.
4. The CPU gets the address of the ISR from IVT and jumps to it.
5. And starts the execution of ISR; when reach Return instruction CPU returns to
the location where it was interrupted.
 Interrupt initiated I/O
• In program-controlled I/O, the processor continuously monitors the status of
the device, whether it is ready for data transfer. it does not perform any useful
tasks.
• It keeps the CPU busy needlessly.
• It can be avoided by making the interface continuously monitor the device
status and raise an interrupt to the CPU as soon as the device is ready for data
transfer.
• Upon detecting external interrupt signal, processor stops what is presently
doing and branches to an interrupt service routine (ISR) to initiate I/O
transfer, and data transfer is over, return to the task it was originally doing.
• In interrupt- initiated I/O, CPU performs data transfer but it not involving in
checking whether the device is ready for data transfer or not.
 Interrupts (contd..)
Program 1 Interrupt Service routine

1
2

Interrupt
occurs i
here
i+1

Processor is executing the instruction located at address i when an interrupt occurs.

Routine executed in response to an interrupt request is called the interrupt-service routin
When an interrupt occurs, control must be transferred to the interrupt service routine.
But before transferring control, the current contents of the PC (i+1), must be saved in a k
ocation.
This will enable the return-from-interrupt instruction to resume execution at i+1.
Return address, or the contents of the PC are usually stored on the processor stack.
 Interrupts (contd..)
Treatment of an interrupt-service routine is very similar to that of a
subroutine. However there are significant differences:
Interrupts are initiated by signals rather than from the execution of
instruction.
The address of ISR is determined by the H/W rather than from the
address field of an instruction.
 Before starting the execution of the ISR, PC and status information of processor must
be saved.
 This saved information must be restored in-order to resume the execution of the
interrupted program.
 In this way , the original program can continue execution without being affected in
any way by the interruption.
 Interrupts (contd..)
Saving and restoring information can be done automatically by
the processor or explicitly by program instructions.
Saving and restoring registers involves memory transfers:
Increases the total execution time.
Increases the delay between the time an interrupt request is
received, and the start of execution of the interrupt-service
routine. This delay is called interrupt latency.
In order to reduce the interrupt latency, most processors save only the
minimal amount of information:
 This minimal amount of information includes Program Counter and processor
status registers.
Another approach is to provide duplicate set of processor registers. In this
case, a different set of registers can be used by the ISR , thus eliminating the
need to save and restore registers. Duplicate registers are called shadow
registers.
 Enabling and Disabling Interrupts
 Interrupts can arrive at any time, they can alter the sequence of events.
 The arrival of an interrupt request from an external device causes the
processor to suspend the execution of one program and starts the execution
of another program.
 Hence, we need a mechanism to enable and disable such interruptions as
desired.
 It is able to enable & disable interrupts at both CPU and I/O device ends.
 The CPU can either accept or ignore interrupt request.
 An I/O device can be allowed to raise interrupt request or prevented from
doing so.
 A commonly used mechanism to achieve this is to use some control bits in
registers.
 The CPU has a Status register (PS) , which contains information about its
current status of operation.
 Let one bit “ IE (Interrupt Enable) “ of this register be assigned for enabling/
disabling interrupts.
 Contd..

 When IE  1 the CPU responds to the interrupt request from I/O device
 When IE  0, the CPU ignores the interrupt request from I/O device.

• The Programmer can set or reset the IE bit by using EI (Enabling Interrupt) and
DI (Disable Interrupt) instructions.
• The CPU sets the IE flag to 1 , when executing EI instruction.
• The CPU reset IE to 0 , when executing DI instruction.
• There is one special situation , where CPU resets IE flag on its own: processor
automatically disable interrupts before starting the execution of the interrupt-
service routine and after saves the contents of the program counter and the
processor status register.
• 2. The interface of an I/O device includes a control register. One bit in that
register may be dedicated to interrupt control.
• The I/O device is allowed to raise interrupt request only when this bit is set to
1 (KIE).
Sequence of Events involved in handling an Interrupt request from a Single
Device
• let us summarize the sequence of events involved in handling an interrupt
request from a single device.
• Assuming that interrupts are enabled in both the processor and the device,
the following is a typical scenario:
1. The device raises an interrupt request.
2. The processor interrupts the program currently being executed and saves the
contents of the PC and PS registers.
3. Interrupts are disabled by clearing the IE bit in the PS to 0.
4. The action requested by the interrupt is performed by the interrupt-service
routine, during which time the device is informed that its request has been
recognized, and in response, it deactivates the interrupt-request signal.
5. Upon completion of the interrupt-service routine, the saved contents of the
PC and PS registers are restored (enabling interrupts by setting the IE bit to
1), and execution of the interrupted program is resumed.
 Handling Multiple Devices
 Multiple I/O devices may be connected to the processor and the memory via a
bus. Some or all of these devices may be capable of generating interrupt
requests.
 When more than one device raises an interrupt request signal, the additional
information is needed to decide which device to be considered first.
 How does the processor know which device has generated an interrupt?
 How does the processor know which interrupt service routine needs to be
executed?
 Should a device is allowed to interrupt the processor, while another interrupt
is being serviced?
 If two interrupt-requests are received simultaneously, then how to break the
tie?
 The following methods are used to decide which device to select. 1) Polling
Polling: Interrupt identification by polling.
When device request an interrupt, to determine which device
request an interrupt, The information is available in the status
register of the device requesting an interrupt:
 The status register of each device has an IRQ bit which it sets to 1 when it requests
an interrupt.
 When ever interrupt occurs, to determine which device raise it, there is a special ISR,
that poll all I/O devices in the system.
 The first device encountered with its IRQ bit set to 1 is the device that should be
serviced.
 The polling scheme is easy to implement.
 Disadvantages: a lot of time is wasted by interrogating the IRQ bit of all the devices.
• Vectored Interrupts:
• In vectored interrupts, a device requesting an interrupt identifies itself directly by
sending a special code to the processor over the interconnection network.
• This allows the processor to identify the device that generated the interrupt.
• Then processor identifies the address of the ISR by using Interrupt Vector Table. (IVT)
 Interrupt Nesting: During the execution of one ISR, if it allows another
interrupt, then this is known as interrupt nesting.
 Ex: The CPU initially executing a program A when the first interrupt occurs.
Then the CPU stores return address of A and starts executing ISR1.
 Now in the mean time, second interrupt occurs. The CPU again after storing
return address of ISR1, start the execution of ISR2.
 After completing ISR2, the CPU resumes the execution of ISR1, similarly after
ISR1 completion, resumes execution of A.

 I/O devices should be organized in a priority structure.

 An interrupt request from high priority device should be accepted while the
processor is servicing a request from a lower priority device.
 Here assign the priority level to the devices.
 Simultaneous Requests:
There is also possibility that several devices may request interrupt services
simultaneously.
In this case , the CPU must decide which to service first . i.e. when 2 devices
interrupt the CPU at the same time, the CPU services the device, with the higher
priority first.
 Controlling I/O Device Behaviour
• To ensure that interrupt requests are
generated only by those I/O devices that the
processor is currently willing to recognize.
• Hence, we need a mechanism in the interface
circuits of individual devices to control whether
a device is allowed to interrupt the processor.
• The control needed is usually provided in the
form of an interrupt-enable bit in the device’s
interface circuit.
• The keyboard status register includes bits KIN and
KIRQ. We have already discussed the use of the KIN
bit.
• The KIRQ bit is set to 1 if an interrupt request has
been raised, but not yet serviced.
• The keyboard may raise interrupt requests only when
the interrupt-enable bit, KIE, in its control register is
set to 1.
• Thus, when both KIE and KIN bits are equal to 1, an
interrupt request is raised and the KIRQ bit is set to 1.
• (similarly DIRQ) in status register of display interface
indicates whether an interrupt request has been
raised or not. DIE in control register is used to enable
interrupts . (Dout  1 and DIE 1 then DIRQ1
 Processor Control Registers
• To deal with interrupts it is useful to have some
other control registers.
• where there are four processor control
registers.
• The status register, PS, includes the interrupt-
enable bit, IE, in addition to other status
information.
• Recall that the processor will accept interrupts
only when this bit is set to 1.
Contd..
 Contd..
• The IPS register is used to automatically save the
contents of PS when an interrupt request is
received and accepted.
• At the end of the interrupt-service routine, the
previous state of the processor is automatically
restored by transferring the contents of IPS into PS.
• Since there is only one register available for storing
the previous status information, it becomes
necessary to save the contents of IPS on the stack if
nested interrupts are allowed.
 Contd..
• The IENABLE register allows the processor to
selectively respond to individual I/O devices.
• When a bit is set to 1, the processor will accept
interrupt requests from the corresponding device.
• The IPENDING register indicates the active
interrupt requests. This is convenient when
multiple devices may raise requests at the same
time. Then, a program can decide which interrupt
should be serviced first.
 DMA (Direct Memory Transfer)
• Blocks of data are often transfer between the main memory and the I/O
devices.
• To transfer the data from an I/O device to the memory:
i. first, reading them from I/O device using instruction Load R2, DataIn
ii. Which loads data into a processor register. Then, the data read are stored
into a memory location.
• The reverse process takes place for transferring data from memory to an I/O
device.
• Data transfer instruction is executed only after the CPU determines that the
I/O device is ready, either by Polling its status register or by waiting for an
interrupt request.
• In either case, several instructions must be executed for data transfer.
• In both cases, CPU is involved for data transfer between memory and I/O
devices.
• An alternative approach is used to transfer blocks of data directly between
the main memory and I/O devices such as Disk.
 DMA (Direct Memory Transfer)
• DMA :- Transfer the data between Memory and Disk without CPU
intervention. This approach is called DMA.
• A special control unit is provided to manage the transfer ,
without Cpu involvement . This unit is called DMA Controller. i.e.
the Unit that controls the data transfer.
• The DMA controller performs the functions that would be carried
out by CPU when accessing main memory.
• To initiate data transfer, the CPU sends
i. the starting address to DMA controller,
ii. also sends [Link] words in the block,
iii. and the direction of the transfer.
• The DMA controller then proceeds to perform the requested operation.
• When entire block has been transferred, it informs the CPU by raising
an interrupt.
 DMA (Direct Memory Transfer)
• DMA Controller Registers: 2 registers are used for storing the starting address and the
word count. The third register contains status and control flags. The R/W specifies the
direction of transfer. When it is 1 read 0 write. When controller transfers data then it
sets Done bit to 1
DMA (Direct Memory Transfer)
 DMA (Direct Memory Transfer)
• The Figure shows how DMA controllers may be used in a computer system.
• One DMS controller connects a high speed ethernet to the computers I/O bus.
• The Disk Controller, which controls two disks, also has DMA capability and provides 2
DMA channels.
• It can perform 2 independent DMA operations, as if each disk had its own DMA
controller.
• To start a DMA transfer of a Block of data from the main memory to one of the disk, an
operating System routine writes the address and word count information into the
registers of the DMA controller.
• The DMA controller proceeds, to implement the specified operation when the transfer
is completed, this fact is recorded in the status and control register of DMA channel by
setting the DONE bit.
• At the same time , if the IE bit is set, the controller sends an interrupt request to the
CPU and sets the IRQ bit.