TOPIC -1

• Brief review of
Number System
Number
systems s
• Digital Logic and
and electrical
Gates its
Logic characteristics
Families • Review of RTL, DTL,
TTL, ECL, CMOS
families.

BECE102L – DIGITAL SYSTEM DESIGN 2

BECE102L – DIGITAL SYSTEM DESIGN 3
INTRODUCTION TO DIGITAL
SYSTEMS
ANALOG vs DIGITAL
SYSTEMS

BECE102L – DIGITAL SYSTEM DESIGN

 INTRODUCTION TO DIGITAL
SYSTEMS INTRODUCTION
 In electronics is important when dealing
with various quantities that we be able
to represent their values efficiently and
accurately.

 Electronic circuits can be divided into two

broad categories, digital and analog.

 The major difference between analog and

digital quantities, then, can be stated
simply as follows:
 Analog = continuous
 BECE102L – DIGITAL SYSTEM DESIGN
 INTRODUCTION TO DIGITAL
SYSTEMS ANALOG SYSTEMS
 Systems which are capable of
processing a continuous range of values
varying with respect to time are called
analog systems.

 Most things that can be measured

quantitatively occur in nature in analog
form.

 Analog quantities have an important

characteristic: they can vary over a
continuous range of values.
BECE102L – DIGITAL SYSTEM DESIGN
INTRODUCTION TO DIGITAL
SYSTEMS ANALOG
SYSTEMS

BECE102L – DIGITAL SYSTEM DESIGN

INTRODUCTION TO DIGITAL
SYSTEMS ANALOG
CIRCUITS

BECE102L – DIGITAL SYSTEM DESIGN

 INTRODUCTION TO DIGITAL
SYSTEMS DIGITAL SYSTEMS
 A digital quantity is one having a discrete
set of values. Systems which process
discrete values are called digital systems.
 In digital representation the quantities
are represented not by proportional
quantities but by symbols called digits.
 For many years, applications of digital
electronics were confined to computer
systems. Today, digital technology is applied
in a wide range of areas in addition to
computers. BECE102L – DIGITAL SYSTEM DESIGN
INTRODUCTION TO DIGITAL
SYSTEMS DIGITAL
SYSTEMS

BECE102L – DIGITAL SYSTEM DESIGN

INTRODUCTION TO DIGITAL
SYSTEMS DIGITAL
CIRCUITS

BECE102L – DIGITAL SYSTEM DESIGN

INTRODUCTION TO DIGITAL
SYSTEMS ANALOG vs DIGITAL
SIGNALS

Analog waves
are smooth and
continuous,
digital waves
are stepping,
square, and
discrete

BECE102L – DIGITAL SYSTEM DESIGN

 INTRODUCTION TO DIGITAL
SYSTEMS ANALOG vs DIGITAL SIGNALS
For example, the air temperature changes over a
continuous range of values. During a given day, the
temperature does not go from, say, 70 to 71
instantaneously; it takes on all the infinite values in
between.

BECE102L – DIGITAL SYSTEM DESIGN

 INTRODUCTION TO DIGITAL
SYSTEMS ANALOG vs DIGITAL SIGNALS
Rather than graphing the temperature on a
continuous basis, suppose you just take a
temperature reading every hour. Now you have
sampled values representing the temperature at
discrete points in time (every hour) over a 24-hour
period.

BECE102L – DIGITAL SYSTEM DESIGN

 INTRODUCTION TO DIGITAL
SYSTEMS
DIGITAL SYSTEMS ADVANTAGES
 Easier to design.
 Information storage is easy.
 Digital circuits are less affected by noise.
 Exact valuesare not important,only the
range (HIGH or LOW) in which they fall.
 More digital circuitry can be fabricated on IC
chips.
 Applications: communications rada
systems, navigation, r,
military
instrumentation, systems,
industrial process medic
control. al
BECE102L – DIGITAL SYSTEM DESIGN
BECE102L – DIGITAL SYSTEM DESIGN
NUMBER BASE
CONVERSIONS
NUMBER
SYSTEMS

BECE102L – DIGITAL SYSTEM DESIGN

NUMBER BASE
CONVERSIONS
NUMBER
SYSTEMS

BECE102L – DIGITAL SYSTEM DESIGN

BECE102L – DIGITAL SYSTEM DESIGN
 BINARY NUMBERS
BINARY NUMBER SYSTEMS
 The binary number system has two digits (bits
0 &1)

 The binary number system has a base of 2

 The position of a 1 or 0 in a binary number

indicates its weight. or value within the
number

 The weights in a binary number are based on

powers of 2

 In general, with n bits you can count up to a

BECE102L – DIGITAL SYSTEM DESIGN
 BINARY NUMBERS
BINARY NUMBER SYSTEMS
 The weight or value of a bit increases from
right to left in a binary number.

 A binary number is a weighted number

 The right-most bit is the LSB (least

significant bit) and left-most bit is the MSB
(most significant bit)

 Fractional numbers can also be

represented in binary by placing bits to
the right of the binary point
BECE102L – DIGITAL SYSTEM DESIGN
 BINARY NUMBERS
BINARY NUMBER SYSTEMS
 All the bits to the left of the binary point
have weights that are positive powers of
two
 All bits to the right of the binary point
have weights that are negative powers of
two
 The weight doubles for each positive
power of two and that the weight is
halved for each negative power of two

BECE102L – DIGITAL SYSTEM DESIGN

BECE102L – DIGITAL SYSTEM DESIGN
 NUMBER BASE
CONVERSIONS
DECIMAL NUMBER SYSTEMS
 Decimal number system has ten digits
(0 to 9)

 The decimal number system has the base of

10
 The value of the digit is determined
by the position of the number

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
DECIMAL NUMBER SYSTEMS

Express the decimal number 568.23 as a sum

of the values of each digit.

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
DECIMAL to BINARY CONVERSION
(Repeated division by 2 method)
 To get the binary number for a given decimal
number, divide the decimal number by 2 until
the quotient is 0. Remainders form the binary
number.

BECE102L – DIGITAL SYSTEM DESIGN

NUMBER BASE
CONVERSIONS
DECIMAL TO BINARY
CONVERSION

(156)10 = (10011100)2
BECE102L – DIGITAL SYSTEM DESIGN
NUMBER BASE
CONVERSIONS
DECIMAL to BINARY
CONVERSION
(Repeated division by 2
method)

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
DECIMAL TO BINARY CONVERSION
(Fractional)

Convert (0.188)10 to binary form

BECE102L – DIGITAL SYSTEM DESIGN

NUMBER BASE
CONVERSIONS
BINARY to DECIMAL
CONVERSION

BECE102L – DIGITAL SYSTEM DESIGN

NUMBER BASE
CONVERSIONS
BINARY to DECIMAL
CONVERSION

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
HEXADECIMAL NUMBERS
 The hexadecimal number
system has a base of sixteen;
it consists of digits 0-9 and letters A-F.

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
BINARY to HEXADECIMAL CONVERSION
 Simply break the binary number into 4-bit groups,
starting at the right-most bit and replace each 4-bit
group with the equivalent hexadecimal symbol.

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
HEXADECIMAL to BINARY CONVERSION
 To convert from a hexadecimal number to a
binary number, reverse the process and replace
each hexadecimal symbol with the appropriate
four bits.

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
OCTAL NUMBER SYSTEMS

 The octal number system has a base of 8

 The octal numbersystem is

composed of eight digits, which are
0, 1, 2, 3, 4, 5, 6, 7

 To count above 7, begin another column

and start over: 10, 11, 12. 13, 14, 15, 16, 17,
20, 21,...

 Counting in octal is similar to counting in

decimal, except that the digits 8 and 9 are
BECE102L – DIGITAL SYSTEM DESIGN
 NUMBER BASE
CONVERSIONS
OCTAL to BINARY CONVERSION

 To convert an octal number to a

binary number, simply
replace each octal digit with the appropriate three
bits.

BECE102L – DIGITAL SYSTEM DESIGN

 NUMBER BASE
CONVERSIONS
BINARY to OCTAL CONVERSION
 Conversion of a binary number to an octal
number is the reverse of the octal-to-binary
conversion.

BECE102L – DIGITAL SYSTEM DESIGN

NUMBER BASE
CONVERSIONS
Exercise
problems

BECE102L – DIGITAL SYSTEM DESIGN

BECE102L – DIGITAL SYSTEM DESIGN
BINARY ARITHMETIC

BECE102L – DIGITAL SYSTEM DESIGN

BINARY ARITHMETIC

BECE102L – DIGITAL SYSTEM DESIGN

BINARY ARITHMETIC

BECE102L – DIGITAL SYSTEM DESIGN

BINARY ARITHMETIC
BINARY
ARITHMETIC

BECE102L – DIGITAL SYSTEM DESIGN

BECE102L – DIGITAL SYSTEM DESIGN
 COMPLEMENTS
1’s COMPLEMENT OF BINARY
NUMBER

BECE102L – DIGITAL SYSTEM DESIGN

 COMPLEMENTS
2’s COMPLEMENT OF BINARY
NUMBER

BECE102L – DIGITAL SYSTEM DESIGN

 COMPLEMENTS
2’s COMPLEMENT OF BINARY
NUMBER

BECE102L – DIGITAL SYSTEM DESIGN

BECE102L – DIGITAL SYSTEM DESIGN
 REPRESENTATION OF NEGATIVE
NUMBERS
SIGNED MAGNITUDE NUMBERS
 In decimal system, generally a plus (+) sign
denotes a positive number whereas a minus
(–) sign denotes a negative number. This
type of representation of numbers is known
as signed numbers.

 But in digital circuits, there is no provision to

put a plus or minus sign, normally an
additional bit is used as the sign bit. This sign
bit is usually placed as the MSB.

 Generally a 0 is reserved for a positive number

and a 1 is reserved for a negative number.
BECE102L – DIGITAL SYSTEM DESIGN
 REPRESENTATION OF NEGATIVE
NUMBERS
SIGNED MAGNITUDE NUMBERS
 For example, an 8-bit signed binary number
01101001 represents a positive number
whose magnitude is (1101001)2= (105)10 the
MSB is 0, which indicates that the number is
positive.

 On the other hand, in the signed binary

form, 11101001 represents a negative
number whose magnitude is (11101001)2= (-
105)10 . The 1 in the MSB position indicates
that the number is negative and the other
seven bits give its magnitude.
BECE102L – DIGITAL SYSTEM DESIGN
REPRESENTATION OF NEGATIVE
NUMBERS
SIGNED MAGNITUDE
NUMBERS

BECE102L – DIGITAL SYSTEM DESIGN

BECE102L – DIGITAL SYSTEM DESIGN
DIGITAL LOGIC GATES
NOT - LOGIC
GATES

BECE102L – DIGITAL SYSTEM DESIGN

DIGITAL LOGIC GATES
AND - LOGIC
GATES

BECE102L – DIGITAL SYSTEM DESIGN

DIGITAL LOGIC GATES
OR - LOGIC
GATES

BECE102L – DIGITAL SYSTEM DESIGN

DIGITAL LOGIC GATES
NAND - LOGIC
GATES

BECE102L – DIGITAL SYSTEM DESIGN

DIGITAL LOGIC GATES
NOR - LOGIC
GATES

BECE102L – DIGITAL SYSTEM DESIGN

DIGITAL LOGIC GATES
XOR-LOGIC
GATES

BECE102L – DIGITAL SYSTEM DESIGN

 TOPIC -2

• Basic Definitions,
Axiomatic Definition
Boolean Algebra,
of
Boolea Theorems Basic
and Properties
of Boolean Algebra,
n Boolean Functions,
algebr Canonical and Standard
Forms
a
BECE102L – DIGITAL SYSTEM DESIGN 2
BECE102L – DIGITAL SYSTEM DESIGN 3
 BOOLEAN ALGEBRA
BOOLEAN ALGEBRA INTRODUCTION

 Boolean Algebra is the mathematics we

use to analyze digital gates and circuits.

 We can use these “Laws of Boolean” to

both reduce and simplify a complex
Boolean expression to reduce the number
of logic gates required.

 Boolean Algebra is therefore a

system of mathematics based on logic
that has its own set of rules or laws which
are used to define and reduce Boolean
BECE102L – DIGITAL SYSTEM DESIGN 4
 BOOLEAN
ALGEBRA
LAWS OF BOOLEAN ALGEBRA
 Commutative Laws: The commutative
law of addition for two
variables is written as:A+B=B+A

 The commutative law of

multiplication for two variables is, AB
= BA

BECE102L – DIGITAL SYSTEM DESIGN 5

 BOOLEAN
ALGEBRA
LAWS OF BOOLEAN ALGEBRA
 Associative Laws: The associative law of
addition is written as follows for three
variables:
A + (B + C) = (A + B) + C

 The associative law of multiplication is

written as follows for three variables:A(BC)
= (AB)C

BECE102L – DIGITAL SYSTEM DESIGN 6

 BOOLEAN
ALGEBRA
LAWS OF BOOLEAN ALGEBRA

 Distributive Law: The distributive law

is written for three variables as
follows:

A(B + C) = AB + AC

BECE102L – DIGITAL SYSTEM DESIGN 7

 BOOLEAN
ALGEBRA
RULES OF BOOLEAN ALGEBRA

 Basic rules that are useful in manipulating

and simplifying Boolean expressions.

BECE102L – DIGITAL SYSTEM DESIGN 8

 BOOLEAN
ALGEBRA
RULES OF BOOLEAN
ALGEBRA

RULE - 1

RULE -
2

RULE -
6

BECE102L – DIGITAL SYSTEM DESIGN 9

 BOOLEAN
ALGEBRA
RULES OF BOOLEAN
ALGEBRA

RULE - 4

RULE -
5

RULE -
6

BECE102L – DIGITAL SYSTEM DESIGN 10

 BOOLEAN
ALGEBRA
RULES OF BOOLEAN
ALGEBRA

RULE - 7

RULE -
8

RULE -
9

BECE102L – DIGITAL SYSTEM DESIGN 11

BOOLEAN
ALGEBRA
RULES OF BOOLEAN
ALGEBRA

BECE102L – DIGITAL SYSTEM DESIGN 12

BOOLEAN
ALGEBRA
RULES OF BOOLEAN
ALGEBRA

BECE102L – DIGITAL SYSTEM DESIGN 13

BOOLEAN
ALGEBRA
RULES OF BOOLEAN
ALGEBRA

BECE102L – DIGITAL SYSTEM DESIGN 14

 BOOLEAN
ALGEBRA
DEMORGAN’S LAW – FIRST LAW
 The complement of a product of variables is
equal to the sum of the complements of the
variables

 The formula for expressing this theorem

for two variables is

BECE102L – DIGITAL SYSTEM DESIGN 15

 BOOLEAN
ALGEBRA
DEMORGAN’S LAW – SECOND LAW

 The complement of a sum of variables is

equal to the product of the complements of
the variables.

 The formula for expressing this theorem

for two variables is

BECE102L – DIGITAL SYSTEM DESIGN 16

 BOOLEAN
ALGEBRA
DEMORGAN’S LAW –
EXAMPLES

BECE102L – DIGITAL SYSTEM DESIGN 17

 BOOLEAN
ALGEBRA
MINIMIZATION OF BOOLEAN
EXPRESSION

(x’+ y) (x+ y)
= x’.x+ x’y+ yx+
y.y
[ x.x’= 0]; [ y. y=
= 0+ x’y+ xy+ y y]
= y ( x’+ x+ 1)
[ 1+ x =
= y( 1 ) 1]
= y.
BECE102L – DIGITAL SYSTEM DESIGN 18
 BOOLEAN
ALGEBRA
MINIMIZATION OF BOOLEAN
EXPRESSION
xy+ xyz+ xyz’+ x’yz
= xy ( 1+ z+ z’)+
x’yz
[ 1+ x =
= xy ( 1 ) + x’yz 1]
= xy+ x’yz
[ x+ x’y = x+
= y ( x+ x’z ) y]
= y ( x+ z ).

BECE102L – DIGITAL SYSTEM DESIGN 19

 BOOLEAN
ALGEBRA
MINIMIZATION OF BOOLEAN
EXPRESSION
x’yz+ xy’z’+ x’y’z’+ xy’z+ xyz
= yz (x’+x) + xy’z’+ x’y’z’+
= yz (1) + y’z’
xy’z(x+ x’) + [ x+ x’=
xy’z 1]
= yz+ y’z’ (1) + xy’z [ x+ x’=
1]
= yz+ y’z’+ xy’z
= yz+ y’ (z’+ xz)
= yz+ y’ (z’+ x) [ x’+ xy = x’+
y]
= yz+ y’z’+ xy’
BECE102L – DIGITAL SYSTEM DESIGN 20
 BOOLEAN
ALGEBRA
MINIMIZATION OF BOOLEAN
EXPRESSION
xy+ xy’( x’z’)’
= xy+ xy’ (x’’+
z’’) [x’’ =
= xy+ xy’ (x+ z) x]
= xy+ xy’x+ [x. x=
xy’z x]
= xy+ xy’+ xy’z [1+ x =
= xy+ xy’ [1+ z] 1]
= xy+ xy’ [1]
= xy+ xy’ [x+ x’=
= x( y+ y’) 1]
= x [1] BECE102L – DIGITAL SYSTEM DESIGN 21
 BOOLEAN
ALGEBRA
MINIMIZATION OF BOOLEAN
EXPRESSION

[(xy)’+ x’+ xy]’

= [ x’+ y’+ x’+
xy]’
[x+ x= x]
= [ x’+ y’+ xy]’
[ x’+ xy = x’+
= [x’+ y’+ x]’ y]
= [y’+ 1]’ [ x+ x’= 1]
= [ 1 ]’ [ 1+ x = 1 ]
= 0.
BECE102L – DIGITAL SYSTEM DESIGN 22
 BOOLEAN
ALGEBRA
MINIMIZATION OF BOOLEAN EXPRESSION -
EXERCISE

1. xyz+ xy’z+ xyz’ = x(y+ z)

2. w’xyz’+ xyz’+ xy’z’+ xy’z = xz
3. w’xy’z+ w’xyz+ wxz = xz
4. AB + (AC)' + AB’C (AB + C) = 1
5. x’y’z’+ x’y’z+ x’yz’+ x’yz+ xy’z’ =
x’+ y’z’
6. (x+ y) (x’z’+ z) (y’+ xz)’ = x’y
BECE102L – DIGITAL SYSTEM DESIGN 23
BECE102L – DIGITAL SYSTEM DESIGN 24
 CANONICAL AND STANDARD
FORMS
BOOLEAN EXPRESSION FOR A LOGIC CIRCUIT

 To derive the Boolean expression for a given

logic circuit, begin at the left-most inputs
and work toward the final output, writing
the expression for each gate.

BECE102L – DIGITAL SYSTEM DESIGN 25

 CANONICAL AND STANDARD
FORMS
CONSTRUCTING A TRUTH TABLE FOR A LOGIC CIRCUIT
 Truth table shows the output for all possible
values of the input variables can be
developed.
 The procedure requires that you
evaluate the Boolean expression for all
possible combinations of values for the
input variables.
 The first step is to list the sixteen input
variable combinations of 1’s and 0’s in
binary sequence.
 BECE102L – DIGITAL SYSTEM DESIGN 26
 CANONICAL AND STANDARD
FORMS
CONSTRUCTING A TRUTH TABLE FOR A LOGIC
CIRCUIT

BECE102L – DIGITAL SYSTEM DESIGN 27

 CANONICAL AND STANDARD
FORMS
 Standard form: In a standard form we don’t
have to compulsorily write all the literals
in all the terms of an expression.
e.g. f = xyz + y + x

 Canonical form: In a canonical form we

have to compulsorily write all the literals
in all the terms of an expression.
e.g. f = xyz+x’yz’+xy’z’

BECE102L – DIGITAL SYSTEM DESIGN 28

 CANONICAL AND STANDARD
FORMS
 All Boolean expressions, regardless of their
form, can be represented into either of two
forms:
 Sum-of-Products Form (SOP)
 Product-of Sums Form (POS)

 Sum of Products(SOP): The logical sum of

two or more logical product terms is
referred to as a sum of products expression.

 It is basically an OR operation on AND

operated variables. For example,
Y = A + BC + AB’C or Y = AB’C’ + A’BC +
BECE102L – DIGITAL SYSTEM DESIGN 29
 CANONICAL AND STANDARD
FORMS
 Product of Sums(POS): Similarly, the
logical product of two or more logical sum
terms is called a product of sums
expression.

 It
Foris an AND Y=(A)
operation on OR operated
(B+C)
variables.
example, (A+B’+C)
Y= (A+B’+C’)(A′+
or B+C) (A+B’+C)

 Minterm: A binary variable may appear

either in its normal form (x) or in its
complement form (x’).
BECE102L – DIGITAL SYSTEM DESIGN 30
 CANONICAL AND STANDARD
FORMS
 When two binary variables x and y combined
with an AND operation, there are four possible
combinations:

x’y’, x’y, xy’ and xy

Each of these four AND terms is called as

‘minterm’.

 Maxterm: In a similar fashion, when two

binary variables x and y combined with an
OR operation, there are four possible
combinations:
BECE102L – DIGITAL SYSTEM DESIGN 31
CANONICAL AND STANDARD
FORMS

BECE102L – DIGITAL SYSTEM DESIGN 32

CANONICAL AND STANDARD
FORMS
DERIVING SOP AND POS FROM TRUTH
TABLE

BECE102L – DIGITAL SYSTEM DESIGN 33

 CANONICAL AND STANDARD
FORMS
 Canonical Sum of Product Expression: If
each term in SOP form contains all the
literals then the SOP is known as Standard
(or) Canonical SOP form.

 Example:

F (A, B, C) = AB’C+ ABC+ ABC’

 The same can be expressed in a compact

form by listing the corresponding decimal-
equivalent codes of the minterms
containing a function value of 1. 34
BECE102L – DIGITAL SYSTEM DESIGN
 CANONICAL AND STANDARD
FORMS
 For example, if the canonical sum of
product form
of a three-variable logic function
minterms F has and
A′BC, AB′C, the
ABC′,
expressedthis ascan
the sum of thebe
decimalcodes corresponding to
these minterms as below.

F (A,B,C) = Σ (3,5,6)
= m3 + m5 +
m6
= A′BC + AB′C
+ ABC′
where Σ(3,5,6) represents
BECE102L – DIGITAL SYSTEM DESIGN 35
 CANONICAL AND STANDARD
FORMS
 Example-1: .Obtain the canonical sum of
product form of the following function, F
(A, B, C) = A + BC
Solution:
 The function contains three variables
given C. A, B,
 The variables B and C are missing from
the first term of the expression and the
variable A is missing from the second term
of the expression.
 Therefore, first term is to be multiplied by
(B+B′) and (C+C′).The second term is to
be multiplied by (A+A′).
BECE102L – DIGITAL SYSTEM DESIGN 26
 CANONICAL AND STANDARD
FORMS

Example-
2:

BECE102L – DIGITAL SYSTEM DESIGN 37

 CANONICAL AND STANDARD
FORMS
 Canonical Product of Sum Expression:
When a Boolean function is expressed
as the logical product of all the maxterms
from the rows of a truth table, for which
the value of the function is 0, it is
referred to as the canonical product of
sum expression.

 The same can be expressed in a compact

form by listing the corresponding decimal
equivalent codes of the maxterms
containing a function value of 0.
BECE102L – DIGITAL SYSTEM DESIGN 38
 CANONICAL AND STANDARD
FORMS
 For example, if the canonical product of
sums form of a three-variable logic
function F has the maxterms A + B + C, A
+ B′+ C, and A′+ B + C′, this can be
expressed as the product of the decimal
codes corresponding to these maxterms as
below,

Where ∏(0,2,5) represents the

product of maxterms corresponding to
decimal codes 0, 2, and 5.
BECE102L – DIGITAL SYSTEM DESIGN 39
 CANONICAL AND STANDARD
FORMS
 Example-1: Obtain the canonical product
of the sum form of the following
function, F(A,B,C)=(A+B′) (B+C) (A+C′)

Solution:
 In the above three-variable expression, C is
missing from the first term, A is missing
from the second term, and B is missing from
the third term.

 Therefore, CC′ is to be added with first term,

AA′ is to be added with the second, and
BB′ is to be added with the third term.
BECE102L – DIGITAL SYSTEM DESIGN 40
CANONICAL AND STANDARD
FORMS

BECE102L – DIGITAL SYSTEM DESIGN 41

 CANONICAL AND STANDARD
FORMS
Example-
2:

BECE102L – DIGITAL SYSTEM DESIGN 42

 CANONICAL AND STANDARD
FORMS
Exercises
Obtain the canonical Sum of products form
of the following function

(i) Y (A, B, C, D) = AB+ ACD

(ii) Y (A, B, C) = A+ ABC

Obtain the canonical product of

sum form of the following
function

(iii)Y= A. (B+ C+ A)
(iv) Y= (A+B’) (B+C) (A+C’)
BECE102L – DIGITAL SYSTEM DESIGN 43
 CANONICAL AND STANDARD
FORMS
CONVERTING CANONICAL SOP TO CANONICAL POS
 To convert from canonical SOP to canonical
POS, the following steps are taken:
Step 1. Evaluate each product term in
the SOP expression. That is, determine the
binary numbers that represent the product
terms.
Step 2. Determine all of the binary
numbers not included in the evaluation in
Step 1.
Step 3. Write the equivalent sum term for
each binary number from Step 2 and 44
BECE102L – DIGITAL SYSTEM DESIGN
CANONICAL AND STANDARD
FORMS
CONVERTING CANONICAL SOP TO CANONICAL
POS

BECE102L – DIGITAL SYSTEM DESIGN 45

 TOPIC-3

The Map Method - K-map, Product of

Sums and Sum of Products
Simplification, NAND
Implementation
and

NOR
BECE102L – DIGITAL SYSTEM DESIGN 2
BECE102L – DIGITAL SYSTEM DESIGN 3
 SIMPLIFICATION USING BOOLEAN
ALGEBRA

 Many times in the application of Boolean

algebra, you have to reduce a particular
expression to its simplest form or change
its form to a more convenient one to
implement the expression most efficiently.

 This approach uses the basic laws,

rules, and theorems of Boolean algebra to
manipulate and simplify an expression.

BECE102L – DIGITAL SYSTEM DESIGN 4

SIMPLIFICATION USING BOOLEAN
ALGEBRA

BECE102L – DIGITAL SYSTEM DESIGN 5

SIMPLIFICATION USING BOOLEAN
ALGEBRA

BECE102L – DIGITAL SYSTEM DESIGN 6

SIMPLIFICATION USING BOOLEAN
ALGEBRA

BECE102L – DIGITAL SYSTEM DESIGN 7

BECE102L – DIGITAL SYSTEM DESIGN 8
 GATE MINIMIZATION USING
K-MAP
SIMPLIFICATION USING KARNAUGH MAP
 The Karnaugh map technique
provides a systematic method for
simplifying and manipulation of Boolean
expressions

 A Karnaugh map is similar to a truth table

because it presents all of the possible
values of input variables and the resulting
output for each value.

 Karnaugh map is an array of cells in which

each cell represents a binary value of
BECE102L – DIGITAL SYSTEM DESIGN 9
 GATE MINIMIZATION USING
K-MAP
SIMPLIFICATION USING KARNAUGH MAP

 The number of cells in a Karnaugh map is

equal to the total number of possible
input variable combinations.

 For n variables on a Karnaugh map there

are 2n numbers of squares. For three
variables, number of cells is 2 3 = 8. For
four variables, the number of cells is 24 =
16.

 Karnaugh maps can be used for

expressions with two, three, four, and five 10
BECE102L – DIGITAL SYSTEM DESIGN
GATE MINIMIZATION USING
K-MAP
SIMPLIFICATION USING KARNAUGH
MAP

BECE102L – DIGITAL SYSTEM DESIGN 11

 GATE MINIMIZATION USING
K-MAP
3-VARIABLE KARNAUGH MAP
 The 3-variable Karnaugh map is an array of
eight cells.
 In this case, A, B, and C are used for the
variables although other letters could be
used.

 Binary values of A is at the left side

(notice the sequence) and the values of BC
are across the top.

 The value of a given cell is the binary

value of A at the left in the same row 12
BECE102L – DIGITAL SYSTEM DESIGN
 GATE MINIMIZATION USING
K-MAP
3-VARIABLE KARNAUGH MAP
 Figure shows the standard product terms
that are represented by each cell in the
Karnaugh map.

BECE102L – DIGITAL SYSTEM DESIGN 13

 GATE MINIMIZATION USING
K-MAP
4-VARIABLE KARNAUGH MAP
 The 4-variable Karnaugh map is an array of
sixteen cells.

 Binary values of A and B are along the left side

and the values of C and D are across the top.

 The value of a given cell is the binary values of A

and B at the left in the same row combined
with the binary values of C and D at the top in
the same column.

 For example, the cell in the upper right corner

has a binary value of 0010 and the cell in the
BECE102L – DIGITAL SYSTEM DESIGN 14
 GATE MINIMIZATION USING
K-MAP
4-VARIABLE KARNAUGH MAP
 Figure shows the standard product terms
that are represented by each cell in
the 4-variable Karnaugh map.

BECE102L – DIGITAL SYSTEM DESIGN 15

 GATE MINIMIZATION USING
K-MAP
4-VARIABLE KARNAUGH MAP
 Cells that differ by only one variable are
adjacent & Cells with values that differ by
more than one variable are not adjacent.

 In the 3-variable map the 010 cell is adjacent

to the 000,011 and 110 cell. The 010 cell is
not adjacent to the 001, 111, 100, or 101 cell.

 Physically, each cell is adjacent to the cells

that are immediately next to it on any of its
four sides.

 A cell is not adjacent to the cells that

BECE102L – DIGITAL SYSTEM DESIGN 16
 GATE MINIMIZATION USING
K-MAP4-VARIABLE KARNAUGH
MAP

When we have a difference of 1 bit b/w two

adjacent cells we can easily eliminate
Redundant literals from the expression & then
we can minimize our function which is the
aim of K-Map !

 Why k-map follows gray code logic?

In the case of K-Map, we have difference of only 1-bit b/w adjacent cells.
Consider the case of first 2 cells: 00 01. In case(SOP) if we have 1 in both these
cells then it will produce A'B'+A'B. Which will give A‘. Because B+B'=1.
To utilize this concept of B+B'=1 easily we have Gray code in K-Map.
BECE102L – DIGITAL SYSTEM DESIGN 17
 GATE MINIMIZATION USING
K-MAP
GROUPING IN KARNAUGH MAP
 The power of K-maps is in minimizing the terms,
K-maps can be minimized with the help of
grouping the terms to
form single terms.
 When forming groups of squares, observe the
following:
[Link] square containing 1 must be considered at least
once.
[Link] number of 1’s in a group must be equal to 2n ,
i.e. 2,4,8.
3.A group must be as large as possible.
4.A square containing 1 can be included in as many
groups as desired.
[Link] a square containing 1 cannot beplaced
in a group,BECE102L
then – DIGITAL SYSTEM DESIGN 18
 GATE MINIMIZATION USING
K-MAP
TYPES OF GROUPING IN KARNAUGH MAP
 PAIR: Grouping of two 1’s togetherand
it is represented with three variables

BECE102L – DIGITAL SYSTEM DESIGN 19

 GATE MINIMIZATION USING
K-MAP
TYPES OF GROUPING IN KARNAUGH MAP
 QUAD: Grouping of four adjacent 1’s and it
results two variables

BECE102L – DIGITAL SYSTEM DESIGN 20

 GATE MINIMIZATION USING
K-MAP
TYPES OF GROUPING IN KARNAUGH MAP
 OCTET: If eight adjacent 1’s are
combined; and represented with by one
variable.

BECE102L – DIGITAL SYSTEM DESIGN 21

 GATE MINIMIZATION USING
K-MAP
RULES FOR KARNAUGH MAP MINIMIZATION

1. No zeros allowed in grouping.

2. No diagonals grouping.
3. Only power of 2 number of cells in each
group.
4. Groups should be as large as possible.
5. Every 1’s must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.
BECE102L – DIGITAL SYSTEM DESIGN 22
 GATE MINIMIZATION USING
K-MAP
RULES FOR KARNAUGH MAP
MINIMIZATION
1. Groups may not include any cell containing a zero

2. Groups may be horizontal or vertical, but not

diagonal

BECE102L – DIGITAL SYSTEM DESIGN 23

 GATE MINIMIZATION USING
4. EachK-MAP
group should be as large as
possible.

5. Each cell containing a one must be in at least

one group.

BECE102L – DIGITAL SYSTEM DESIGN 24

 GATE MINIMIZATION USING
K-MAP
6. Groups may
overlap.

BECE102L – DIGITAL SYSTEM DESIGN 25

 GATE MINIMIZATION USING
7.
K-MAP
Groups may wrap around the table. The leftmost cell in a
row may be grouped with the rightmost cell and the top
cell in a column may be grouped with the bottom cell.

8. There should be as few groups as possible, as long as this

does not contradict any of the previous rules.

BECE102L – DIGITAL SYSTEM DESIGN 26

 GATE MINIMIZATION USING
K-MAP
PROCEDURE FOR K- MAP SOP MINIMIZATION

The generalized procedure to simplify Boolean

expressions as follows:
1. Plot the K-map and place 1’s in those cells corresponding
to the 1’s
in the sum of product expression. Place 0’s in the other
cells.
2. Check the K-map for adjacent 1’s and encircle those 1’s
which are not adjacent to any other 1’s. These are
called isolated 1’s.
3. Check for those1’swhich are adjacent to only
one other 1 and
encircle such pairs.
4. Check for quads and octets of adjacent 1’s even if it
contains some 1’s that have already been encircled.
While doing this BECE102L
make– DIGITAL
sureSYSTEM
thatDESIGN there are minimum 27
GATE MINIMIZATION USING
K-MAP3-Variable K-Maps
Simplification

BECE102L – DIGITAL SYSTEM DESIGN 28

GATE MINIMIZATION USING
K-MAP3-Variable K-Maps
Simplification

BECE102L – DIGITAL SYSTEM DESIGN 29

 GATE MINIMIZATION USING
K-MAPK- MAP SOP MINIMIZATION

Design an car driver alert system based on

following condition. The buzzer (B=1) will
alert the driver whenever any one of the
following condition is satisfied.

(i). When engine is O N (E=1) and any

one of the door is opened (D=1)
(ii).when fuel level is low (F=1)
(iii). When car exceed speed limit (S=1)

BECE102L – DIGITAL SYSTEM DESIGN 30

GATE MINIMIZATION USING
K-MAP
PROCEDURE FOR K- MAP SOP
MINIMIZATION

Truth table

BECE102L – DIGITAL SYSTEM DESIGN 31

GATE MINIMIZATION USING
K-MAP
PROCEDURE FOR K- MAP SOP
MINIMIZATION

K-MAP

B=F+S+E
D

BECE102L – DIGITAL SYSTEM DESIGN 32

GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF SOP FORMS -
EXAMPLE

BECE102L – DIGITAL SYSTEM DESIGN 33

GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF SOP FORMS -
EXAMPLE

BECE102L – DIGITAL SYSTEM DESIGN 34

GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF SOP FORMS -
EXAMPLE

BECE102L – DIGITAL SYSTEM DESIGN 35

GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF SOP FORMS -
EXAMPLE

BECE102L – DIGITAL SYSTEM DESIGN 36

 GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF SOP FORMS – WITH DON’T
CARES

 A don’t care minterm is a

combination of variables whose logical
value is not specified.

 When choosing adjacent squares to

simplify the function in a map, the don’t
care minterm may be assumed to be either
0 or 1.

 When simplifying the function, we can

choose to include each don’t care minterm
BECE102L – DIGITAL SYSTEM DESIGN 37
 GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF SOP FORMS – WITH DON’T
CARES

BECE102L – DIGITAL SYSTEM DESIGN 38

 GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF SOP FORMS – WITH DON’T
CARES

BECE102L – DIGITAL SYSTEM DESIGN 39

 GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF POS FORMS
 For a POS expression in standard form, a
0 is placed on the Karnaugh map for each
sum term in the expression & the cells that
do not have a 0 are the cells for which the
expression is 1.

 Steps for the POS K-mapping process.

Step 1: Determine the binary value of each sum
term in the standard POS expression. This is the
binary value that makes the term equal to 0.
Step 2: As each sum term is evaluated, place a 0
on the Karnaugh map in the corresponding cell.
Step3: Other procedure are similar to SOP K-map 40
BECE102L – DIGITAL SYSTEM DESIGN
GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF POS FORMS -
EXAMPLE

BECE102L – DIGITAL SYSTEM DESIGN 41

GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF POS FORMS -
EXAMPLE

BECE102L – DIGITAL SYSTEM DESIGN 42

 GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF POS FORMS
 Reduce F(W,X,Y,Z) = ∏(0,1,2,4,5,7,10,15) using
K-map

BECE102L – DIGITAL SYSTEM DESIGN 43

GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF POS
FORMS

F = (W+Y) . (X’+Y’+Z’) . (X+Y’+Z)

BECE102L – DIGITAL SYSTEM DESIGN 44

 GATE MINIMIZATION USING
K-MAP
K-MAP SIMPLIFICATION OF POS FORMS
 Use a Karnaughmap to minimize the following
POS expression:
(B+ C+D)(A+B+C’+D)(A’+B+C+D’)(A+B’+C+D)(A’+B’+
C+D)

The first term must be

expanded into A’ + B + C + D
and A + B + C + D to get a
standard POS expression,
which is then mapped;

BECE102L – DIGITAL SYSTEM DESIGN 45

 GATE MINIMIZATION USING
K-MAP
KARNAUGH MAP MINIMIZATION - EXERCISE
Using a Karnaugh map, simplify the following functions and
implement them with basic gates.
(a)F (A, B, C, D) = Σm (0, 2, 3, 6, 7, 8, 10, 11, 12, 15)
(b) F (A, B, C, D) = Σm (0, 2, 3, 5, 7, 8, 13) + d (1, 6, 12)
(c)F (A, B, C, D) = Σm (1, 7, 9, 10, 12, 13, 14, 15) + d (4, 5, 8)
(d) F (A, B, C, D) = πM (0, 8, 10, 11, 14) + d (6)
(e)F (A, B, C, D) = π M(2, 8, 11, 15) + d (3, 12, 14)
(f) F (W, X, Y, Z) = πM (0, 2, 6, 11, 13, 15) + d (1, 9, 10, 14)
Prepare a Karnaugh map for the following functions.
(g)F = ABC + A'BC + B'C'
(h) F = A + B + C'
(i) Y = AB + B'CD
Using the Karnaugh map method, simplify the following functions,
obtain their sum of the products form, and product of the sums
form. Realize them with basic gates.
(j) F (W, X, Y, Z) = Σ (1, 3, 4, 5, 6, 7, 9, 12, 13)
(k) F (W, X, Y, Z) = Σ (1, 5, 6, 7, 11, 12, 13, 15)

BECE102L – DIGITAL SYSTEM DESIGN 46

BECE102L – DIGITAL SYSTEM DESIGN 47
 NAND & NOR
IMPLEMENTATION
UNIVERSAL LOGIC GATES
 OR, AND and NOT gates are the three basic
logic gates as they together can be used to
construct the logic circuit for any given
Boolean expression.

 The combination of NAND gates or a

combination of NOR gates can be used to
perform functions of any of the basic logic
gates.

 And also, NAND and NOR gates are referred

to as universal gates because each alone can
be combined together with itself to form all 48
BECE102L – DIGITAL SYSTEM DESIGN
 NAND & NOR
IMPLEMENTATION
NAND GATE AS UNIVERSAL LOGIC GATE
 The NAND gate is a universal gate because it can
be used to produce any of the other logic gates
function.

BECE102L – DIGITAL SYSTEM DESIGN 49

NAND & NOR
IMPLEMENTATION
NAND GATE AS UNIVERSAL LOGIC
GATE

BECE102L – DIGITAL SYSTEM DESIGN 50

NAND & NOR
IMPLEMENTATION
NAND GATE AS UNIVERSAL LOGIC
GATE

BECE102L – DIGITAL SYSTEM DESIGN 51

 NAND & NOR
IMPLEMENTATIONLOGIC
NOR GATE AS UNIVERSAL GATE
 Like the NAND gate, the NOR gate can be
used to produce any logic function.

BECE102L – DIGITAL SYSTEM DESIGN 52

NAND & NOR
IMPLEMENTATION
NOR GATE AS UNIVERSAL
LOGIC GATE

BECE102L – DIGITAL SYSTEM DESIGN 53

NAND & NOR
IMPLEMENTATION
NOR GATE AS UNIVERSAL
LOGIC GATE

BECE102L – DIGITAL SYSTEM DESIGN 54

 NAND & NOR
IMPLEMENTATION
NAND & NOR IMPLEMETATION

 Digital circuits are more frequently

constructed using NAND and NOR gates
than with AND and OR gates

 NAND and NOR gates are easier to

fabricated with other electronics
components and these are the basic gates
used in most digital logic IC families

 To ease the conversion of NAND, NOR

logic it is convenient to define other
graphical symbol for these gates 55
BECE102L – DIGITAL SYSTEM DESIGN
NAND & NOR
IMPLEMENTATION
NAND & NOR
IMPLEMETATION

BECE102L – DIGITAL SYSTEM DESIGN 56

 NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION

 Implement the following logical expression

into an equivalent NAND gate based logic
circuit
F= AB + CD + E

BECE102L – DIGITAL SYSTEM DESIGN 57

 NAND & NOR
IMPLEMENTATION
NAND
IMPLEMETATION

AND is gate is replaced by NAND gate and

OR gate is replaced by NAND gate with
inverted OR gate
BECE102L – DIGITAL SYSTEM DESIGN 58
NAND & NOR
IMPLEMENTATION
NAND
IMPLEMETATION

BECE102L – DIGITAL SYSTEM DESIGN 59

NAND & NOR
IMPLEMENTATION
NAND
IMPLEMETATION

BECE102L – DIGITAL SYSTEM DESIGN 60

NAND & NOR
IMPLEMENTATION
NAND
IMPLEMETATION

BECE102L – DIGITAL SYSTEM DESIGN 61

NAND & NOR
IMPLEMENTATION
NAND
IMPLEMETATION

BECE102L – DIGITAL SYSTEM DESIGN 62

NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION -
EXAMPLES

BECE102L – DIGITAL SYSTEM DESIGN 63

NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION -
EXAMPLES

BECE102L – DIGITAL SYSTEM DESIGN 64

NAND & NOR
IMPLEMENTATION
NAND IMPLEMETATION -
EXAMPLES

BECE102L – DIGITAL SYSTEM DESIGN 65

 NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION
 NOR function is a dual of NAND function,
so all procedures and rules followed for NOR
will be dual of NAND logic realization

 Implementation of boolean function with

NOR gates requires that the function to be
simplified in POS forms
 The POS specifies a group of OR gates for
the sum terms, followed by AND gates to
produce the product

 So, it transfers the OR-AND logic circuits

into the NOR-NOR logic circuits.
BECE102L – DIGITAL SYSTEM DESIGN 66
NAND & NOR
IMPLEMENTATION
NOR
IMPLEMETATION

BECE102L – DIGITAL SYSTEM DESIGN 67

NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other
Examples

BECE102L – DIGITAL SYSTEM DESIGN 68

NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other
Examples

BECE102L – DIGITAL SYSTEM DESIGN 69

NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other
Examples

BECE102L – DIGITAL SYSTEM DESIGN 70

NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other
Examples

BECE102L – DIGITAL SYSTEM DESIGN 71

NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other
Examples

BECE102L – DIGITAL SYSTEM DESIGN 72

NAND & NOR
IMPLEMENTATION
NOR IMPLEMETATION – Other
Examples

BECE102L – DIGITAL SYSTEM DESIGN 73

MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 1
 INTRODUCTION TO COMBINATIONAL
LOGIC
 A combinational circuit consists of input
variables, logic gates, and output variables.

 The logic gates accept signals from inputs

and output signals are generated according
to the logic circuits employed in it.

 Binary information from the given data

transforms to desired output data in this
process.

 Both input and output are obviously the

binary signals,
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 6
 INTRODUCTION TO COMBINATIONAL
LOGIC

Block diagram of a combinational logic

circuit

MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 7
 INTRODUCTION TO COMBINATIONAL
LOGIC

 For n number of input variables to a

combinational circuit, 2n possible combinations
of binary input states are possible.

 For each possible combination, there is one and

only one possible output combination.

 A combinational logic circuit can be

described by m Boolean functions and each
output can be expressed in terms of n input
variables.
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 8
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 32
 BINARY
ADDER
HALF ADDER
 A half-adder is a combinational circuit that can
be used
to add two binary bits.

 It has two inputs that represent the two bits to

be added and two outputs, with one
producing the SUM output Inputs and Outputs
the other
producing the CARRY. A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
BLOCK
1 1 1 0
DIAGRAM
MODULE- 3
TRUTH
BECE102L – DIGITAL SYSTEM DESIGN TABLE 33
 BINARY
ADDER
HALF
ADDER

 The Boolean expressions for the SUM and

CARRY outputs are given by the
equations,
Sum, S = A’B+ AB’=
MODULE- 3 AB
BECE102L – DIGITAL SYSTEM DESIGN 34
 BINARY
ADDER
FULL ADDER
 The full adder circuit overcomes
the limitation of the half-adder,
which can be used to add two bits only.

 A full adder is a combinational

circuit that formsthe
arithmetic sum of three input bits.

 It consists of 3 inputs and 2 outputs. Two of

the input variables, represent the significant bits
to be added.
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 36
 BINARY
ADDER
FULL
ADDER

Inputs Outputs
Sum Carry
A B Cin (S) (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
LOGIC
DIAGRAM
TRUTH
MODULE- 3
TABLE
BECE102L – DIGITAL SYSTEM DESIGN 37
 BINARY
ADDER
FULL
K- ADDER
MAP

 The Boolean expressions for the SUM and

CARRY outputs are given by the
equations,
Sum, S= A’B’Cin+ A’BC’in +
AB’C’in + ABCin
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 38
 BINARY
ADDER
FULL ADDER
 The logic diagram for the above functions is
shown as,

Implementation of full-adder in Sum of

MODULE- 3 Products
BECE102L – DIGITAL SYSTEM DESIGN 39
 BINARY
ADDER
FULL ADDER
 The logic diagram of the full adder
can also be implemented with two half-
adders and one OR gate.

 The S output from the second half adder is the

exclusive- OR of Cin and the output of the first
half-adder, giving

Sum = A’BC’in + AB’C’in + ABCin + A’B’Cin .

= C’in (A’B+AB’) + Cin (AB+A’B’)
= C’in (A’B+AB’) + Cin (A’B+AB’)’
MODULE- 3
= Cin  (A’B+AB’)
BECE102L – DIGITAL SYSTEM DESIGN 40
 BINARY
ADDER
FULL
ADDER
Carry, Cout = AB+ ACin+ BCin.
= AB+ ACin+ BCin (A +A’)
= ABCin+ AB+ ACin+
A’BCin [Cin+1=
= AB (Cin+1) + ACin+ 1]
A’BCin
= AB+ ACin+ A’BCin [Cin+1=
= AB+ ACin (B+B’) + 1]
A’BCin
= ABCin+ AB+ A’BCin+
MODULE- 3
AB’C BECE102L – DIGITAL SYSTEM DESIGN 41
 BINARY
ADDER
FULL
ADDER

Implementation of full adder with two half-adders and

an OR gate
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 42
 BINARY SUBTRACTOR
HALF SUBTRACTOR
 A half Subtractor is a combinational circuit
that can be used to subtract one binary
digit from another to produce a DIFFERENCE
output and a BORROW output.

 The BORROW output here specifies whether a

‘1’ has been borrowed to perform the
subtraction.

Block schematic of half

MODULE- 3
Subtractor
BECE102L – DIGITAL SYSTEM DESIGN 44
 BINARY SUBTRACTOR
HALF SUBTRACTOR
 The truth table of half Subtractor, showing all
possible input combinations and the
corresponding outputs are shown below.

Input Output
A B Difference (D) Borrow (Bout)
0 0 0 0

0 1 1 1
1 0 1 0
1 1 0 0

MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 45
 BINARY SUBTRACTOR
HALF SUBTRACTOR
 K-map simplification for half
Subtractor:

 The Boolean expressions

forthe DIFFERENCE and BORROW
outputs are given by the equations,
Difference, D= A’B+ AB’=
MODULE- 3 A  B Borrow, Bout = A’ .
BECE102L – DIGITAL SYSTEM DESIGN 46
 BINARY SUBTRACTOR
HALF
SUBTRACTOR

Logic Implementation of Half-

Subtractor
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 47
 BINARY SUBTRACTOR
HALF SUBTRACTOR
 Comparing a half Subtractor with a half-adder,
we find that the expressions for the SUM
and DIFFERENCE outputs are just the same.

 The expression for BORROW in the case of

the half- Subtractor is also similar to what we
have for CARRY in the case of the half-adder.

 If the input A i.e. the minuend is

complemented, an AND gate can be used to
implement the BORROW output.
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 48
 BINARY SUBTRACTOR
FULL SUBTRACTOR

 A full Subtractor performs subtraction operation

on two bits, a minuend and a subtrahend,
and also takes into consideration whether a
‘1’ has already been borrowed by the previous
adjacent lower minuend bit or not.

 As a result, there are three bits to be

handled at the input of a full Subtractor,
namely the two bits to be subtracted and a
borrow
MODULE- 3 bit designated as Bin.
BECE102L – DIGITAL SYSTEM DESIGN 49
 BINARY SUBTRACTOR
FULL SUBTRACTOR

 There are two outputs, namely the DIFFERENCE

output D and the BORROW output Bo. The
BORROW output bit tells whether the
minuend bit needs to borrow a ‘1’ from the
next possible higher minuend bit.

Block schematic of full

Subtractor
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 50
 BINARY SUBTRACTOR
FULL
SUBTRACTOR
Inputs Outputs

A B Bin
Difference(D) Borrow(Bout)

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Truth
MODULE- 3 Table
BECE102L – DIGITAL SYSTEM DESIGN 51
 BINARY SUBTRACTOR
FULL SUBTRACTOR
 K-map simplification for full
Subtractor:

 The Boolean expressions for the

DIFFERENCE and BORROW outputs are
given by the equations,
Difference, D= A’B’Bin+ A’BB’in + AB’B’in
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 52
 BINARY SUBTRACTOR
FULL
SUBTRACTOR

Implementation of full
MODULE- 3
Subtractor
BECE102L – DIGITAL SYSTEM DESIGN 53
 BINARY SUBTRACTOR
FULL SUBTRACTOR
 The logic diagram of the full Subtractor can
also be implemented with two half Subtractor
and one OR gate.

 The difference, D output from the second half

Subtractor is the exclusive-OR of Bin and the
output of the first half Subtractor, giving
Difference, D = A’BB’in + AB’B’in + ABBin + A’B’Bin .
= B’
= B’in (A’B+AB’)
(A’B+AB’) +
+BBin (AB+A’B’)
[(x’y+xy’)’=
in in
(A’B+AB’)’ (xy+x’y’)]
= Bin  (A’B+AB’) [x  y = x’y+
= Bin  (A  B) xy’]
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 54
 BINARY SUBTRACTOR
FULL SUBTRACTOR

Borrow, = A’B+ BBin+ A’Bin.

Bout = A’B+ BBin+ A’Bin (B
+B’)
= A’BBin+ A’B+ BBin+ [Bin+1=
A’B’Bin 1]
= A’B (Bin+1) + BBin+ [A+A’=
1]
A’B’Bin
[Bin+1=
= A’B+ BBin+ A’B’Bin
1]
= A’B+ BBin (A+A’) +
A’B’B
= A’B+
in Bin (A’B+AB’)’
MODULE- 3 = A’BBin+ A’B+ ABBin+
[(x’y+xy’)’=(xy+x’y’)]
BECE102L – DIGITAL SYSTEM DESIGN 55
 BINARY SUBTRACTOR
FULL SUBTRACTOR
 Therefore, we can implement full Subtractor
using two half Subtractor and OR gate as,

Implementation of full Subtractor with two half Subtractor

and an OR gate
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 56
 BINARY ADDER &
SUBTRACTOR
APPLICATIONS
 Adders & Subtractors are wildly used in in
computer’s ALU (Arithmetic logic unit) to
compute addition as well as CPU (Central
Processing unit) and GPU (Graphics
Processing unit) for graphics applications to
reduce the circuit complexity.

 Adder and subtractor are basically used for

performing arithmetical functions like
addition, subtraction, multiplication and
division in electronic calculators and digital
instruments.
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN56
 BINARY ADDER &
SUBTRACTOR
APPLICATIONS

 Microcontrollers use adders for arithmetic

additions, PC (program counter) and timers.

 It is also used in microprocessors to calculate

address, table indices, increment and
decrement operators and slimier operations

 It is also used in networking and DSP

(Digital signal processor) oriented system

MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 56
 PARALLEL
ADDER
 A single full adder is capable of adding two
one bit numbers and an input carry. In order
to add a binary number with more than one
bit an additional full adders must be
employed.

 The n-bitparallel adder can be

constructed using “n”
number of full adder circuits in parallel.

 The block diagram of n-bit parallel adder using

number of full adder circuits connected in
MODULE- 3
cascade i.e. the carry output of each adder is
BECE102L – DIGITAL SYSTEM DESIGN 58
 PARALLEL
ADDER

n-bit parallel
Adder

MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 59
 PARALLEL
ADDER
 The 4-bit binary adder using full adder circuits
is capable of adding two 4-bit numbers resulting
in a 4-bit sum and a carry output as shown in
figure below.

4-bit binary parallel

Adder
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 60
 PARALLEL
ADDER
 Since all the bits of augend and addend are fed
into the adder circuits simultaneously and the
additions in each position are taking place at
the same time, this circuit is known as parallel
adder.
 Let the 4-bit words to be added be represented
by, A3 A2 A1 A0= 1 1 1 1 and B3 B2 B1 B0= 0 0 1
1.

MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 61
 PARALLEL
ADDER

Logic diagram of 4-bit

MODULE- 3
parallel adder
BECE102L – DIGITAL SYSTEM DESIGN 62
 PARALLEL
ADDER
 The bits are added with full adders, starting
from the least significant position, to form the
sum bit and carry bit.

 The input carry C0 in the least significant

position must be 0. The carry output of the
lower order stage is connected to the carry
input of the next higher order stage.

 Hence this type of adder is called ripple-carry

adder.
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 63
 PARALLEL
ADDER
 In the least significant stage, A0, B0 and C0
(which is 0) are added resulting in sum S0 and
carry C1. This carry C1 becomes the carry input
to the second stage.

 Similarly in the second stage, A1, B1 and C1

are added resulting in sum S1 and carry C2, in
the third stage, A2, B2 and C2 are added
resulting in sum S2 and carry C3, in the third
stage, A3, B3 and C3 are added resulting in sum
S3 and C4, which is the output carry.
MODULE- 3
BECE102L – DIGITAL SYSTEM DESIGN 64
Carry Look Ahead
Adder
• A Carry Look-Ahead Adder is a fast adder that eliminates the ripple delay by computing all carry bits in
parallel using Boolean logic.

• In a Ripple Carry Adder each carry waits for the previous carry.

• CLA predicts carries in advance using logic, not waiting.

• For each bit position i, define:

Generate

Carry is generated regardless of input carry

Propagate

Carry is propagated if it comes in

Advantages
The propagation delay is reduced.
It provides the fastest addition logic.

Disadvantage
The Carry Look-ahead adder circuit gets complicated as the number of variables
increases.
The circuit is costlier as it involves more number of hardware
 DECODE
RS
 A decoder is a combinational circuit that
converts binary information from ‘n’ input
lines to a maximum of ‘2n’ unique output
lines.

 The encoded information is presented as

‘n’ inputs producing ‘2n’ possible outputs. The
2n output values are from 0 through 2n-1.

 A decoder is provided with enable inputs to

activate decoded output based on data inputs.
When any one enable input is unasserted, all
outputs of decoder are disabled.
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN18
 DECODE
RS

Block diagram of
decoders

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
2 : 4 Decoders

 A binary decoder is used when it is necessary

to activate exactly one of 2n outputs based on
an n-bit input value.

 Here the 2 inputs are decoded into 4

outputs, each output representing one of the
minterms of the two input variables.

 As shown in the truth table, if enable input is 1

(EN= 1) only one of the outputs (Y0 – Y3), is
active for a given input.
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
2:4
Decoders

Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Truth
table
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
2:4
Decoders

Logic
MODULE-3
Diagram
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
3 : 8 Decoders
 A 3-to-8 line decoder has three inputs (A, B, C)
and eight outputs (Y0- Y7). Based on the 3
inputs one of the eight outputs is selected.

 This decoder is used for binary-to-octal

conversion. The input variables may represent
a binary number and the outputs will represent
the eight digits in the octal number system.

 The output line whose value is equal to 1

represents the minterm equivalent of the
binary number presently available in the input
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
3:8
Decoders
Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Truth
table
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
3:8
Decoders

Logic
MODULE-3
Diagram
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
Applications
 Instruction decoder is the part of
the CPU
 Memory address decoding

 Decoder outputs can be to drivea 7

used display (TTL segment
74LS47)
 Binary Decoders such as binary or
BCD ,decimal or octal etc and commonly
available decoder IC’s (TTL 74LS138 3-to-8 line
binary decoder or the 74ALS154 4-to-16 line
decoder)
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
Cascading Decoders
 Exampl Design a 4 to 16 line decoders using
e: 2 to 4 line
decode
 To implement 4:16 decoder we need five 2:4 line decoders.
rs
 Decoder-1 is used to enable one of the decoder 2, 3, 4 and
5. Inputs of
the first decoders are A and B i.e. MSB inputs of 4:16
decoders.

 The inputs of decoders are connected together forming C

and D inputs of 4:16 decoders.

 When AB=00 decoder-1 is enabled, for AB=01 decoder-2 is

enabled, for AB=10 decoder-3 is selected, and for AB=11
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
Cascading
Decoders

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 19
 DECODE
RS
Realization of Boolean Expression using
Decoders
 The combination of decoder and external logic
gates can be used to implement single or
multiple output function. The decoder can have
one of the two output states either active or
active high.
 For active high output :
 SOP function implementation
 When the decoder output is active high it generates
minterms for input variables (i.e) it makes the
selected output logic1. In such cases to implement
the sop function we have to take sum of selected
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 20
 DECODE
RS
Realization of Boolean Expression using
Decoders

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 20
 DECODE
RS
Realization of Boolean Expression using
Decoders
 POS function implementation: When the decoder
output is active high POS function in similar manner
as per SOP function except function output is
complemented. This can be achieved by connecting
NOR gates instead of OR gates .

Single output function implementation using

MODULE-3decoder and gate
BECE102L – DIGITAL SYSTEM DESIGN 20
 ENCODERS
 An encoder is a combinational circuit that
converts binary information from 2n input lines
to a maximum of ‘n’ unique output lines.
 An encoder is a digital circuit that performs
the
operation
inverse ofa decoder. the of
Hence, decoding process opposite
the encoding.
structure is called
of encoder The general
circuit is,

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 20
 ENCODERS

 Generally, digital encoders produce outputs of

2-bit, 3-bit or 4-bit codes depending upon the
number of data input lines.

 An "n-bit" binary encoder has 2n input lines

and n-bit output lines with common types that
include 4-to-2, 8-to- 3 and 16-to-4 line
configurations.

 The output lines of a digital encoder generate

the binary equivalent of the input line whose
value is equal to “1”.
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 20
 ENCODERS
4 to 2
Encoder

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 20
 ENCODERS
Priority Encoder

 One of the main disadvantages of standard

digital encoders is that they can generate the
wrong output code when there is more than
one input present at logic level "1".

 For example, if we make inputs D1 and D2 HIGH

at logic "1" both at the same time, the resulting
output is neither at "01" or at "10" but it will
be at "11" which is an output binary number
that is different to the actual input present.
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 20
 ENCODERS
Priority Encoder

 One simple way to overcome this problem

is to "Priorities" the level of each input pin
and if there was more than one input at logic
level "1" the actual output code would only
correspond to the input with the highest
designated priority.

 Then this type of digital encoder is known

commonly as a Priority Encoder or P-encoder
for short.
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 205
 ENCODERS
Priority Encoder
 A priority encoder is an encoder
circuit that includes the
priority function.

 In priority encoder, if two or more inputs are

equal to 1 at the same time, the input having the
highest priority will take precedence. The higher
the subscript number, higher the priority of the
input.

 Input D3, has the highest priority. So, regardless of

the values of the other inputs, when D3 is 1, the
output for xy is 11. D2 has the next priority level.
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 20
 ENCODERS
4 to 2 Priority
Encoder

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
4 to 2 Priority
Encoder

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
4 to 2 Priority
Encoder

4-Input Priority
MODULE-3
Encoder
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
8 to 3 Priority
Encoder

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
Encoder Applications
(i) Keyboard Encoder
 Priority encoders can be used to reduce the
number of wires needed in a particular circuits
or application that have multiple inputs.

 For example, assume that a microcomputer needs

to read the 104 keys of a standard QWERTY
keyboard where only one key would be pressed
either “HIGH” or “LOW” at any one time.

 One way would be to connect all 104 wires

from the individual keys on the keyboard directly
to the computers input but this would be
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
Encoder Applications

 Another alternative and better way would be to

interface the keyboard to the PC using a priority
encoder.

 The 104 individual buttons or keys could be

encoded into a standard ASCII code of only 7-
bits (0 to 127 decimal) to represent each key or
character of the keyboard and then input as a
much smaller 7-bit B.C.D code directly to the
computer.

 Keypad encoders such as the 74C923 20-key

MODULE-3
encoder are available to do just that. 21
BECE102L – DIGITAL SYSTEM DESIGN
 ENCODERS
Encoder Applications
(ii) Positional Encoders
 Another more common application is in
magnetic
control positional
as used on ships
navigationetc. or for robotic arm
positioning
 Here for example, the angular or rotary position of
a compass is converted into a digital code
priority
by encoder
a 74LS148
and input
8-to-3 toline
the systems
computer to provide navigational data and an
example of a simple 8 position to 3-bit output
compass encoder is shown below.

 Magnets and reed switches could be used at each

compass point to indicate the needles angular
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
Encoder
Applications

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
Encoder
Applications

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
Encoder
Applications
(iii). Interrupt Requests
 Priority Encoders for detecting
used microprocessor interrupts in
applications.
 Here the microprocessor uses interrupts to allow
peripheral devices such as the disk drive, scanner,
mouse, or printer etc, to communicate with it.

 But the microprocessor can only “talk” to one

peripheral device at a time so needs some way
of knowing when a particular peripheral device
wants to communicate with it.
MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 21
 ENCODERS
Encoder Applications
 The processor does this by using “Interrupt
Requests” or
“IRQ” signals to assign priority to all the
peripheral devices to ensure that the most
important peripheral device is serviced first.

 The order of importance of the devices will

depend upon their connection to the priority
encoder.

 Because implementing such a system using

priority encoders such as the standard 74LS148
priority encoder IC involves additional logic
MODULE-3
circuits, purpose built integrated circuits such as 22
BECE102L – DIGITAL SYSTEM DESIGN
 ENCODERS
Encoder
Applications

MODULE-3
BECE102L – DIGITAL SYSTEM DESIGN 22
BECE102L – DIGITAL SYSTEM DESIGN
 ELECTRICAL
CHARACTERISTICS
 Important electrical
characteristics of digital
logic gate IC families:
 DC Voltage Supply
 Logic Levels
 Noise Margin
 Power Dissipation
 Propagation Delay
 Fan-out
BECE102L – DIGITAL SYSTEM DESIGN
 ELECTRICAL
CHARACTERISTICS
DC POWER SUPPLY

 Digital logic chips have a power pin(s)

and a ground pin(s).

 These supply voltages have names

which are based on the type of
transistors used in the construction of
that particular logic family.

 TTL gates are made with bipolar transistors,

which have a collector and an emitter; so
the supply voltages are shown as VCC
(power) and Ground (occasionally shown as
BECE102L – DIGITAL SYSTEM DESIGN
 ELECTRICAL
CHARACTERISTICS
DC POWER SUPPLY

 The nominal value of the dc supply

voltage for TTL(transistor-transistor logic)
devices is +5 V.

 CMOS gates are built with field-effect

transistors, which have a drain and a
source; so the supply voltages are shown
as VDD (power) and VSS (ground) on
most data sheets.

 CMOS (complementary metal-

oxide semiconductor) devices are available
BECE102L – DIGITAL SYSTEM DESIGN
 ELECTRICAL
CHARACTERISTICS
LOGIC LEVELS

 There are four different logic-level

specifications:
1. VIHmin -- the minimum input voltage which
will be accepted as a logic 1 state.
2. VILmax -- the maximum input voltage which
will be accepted as a logic 0 state.
-- the minimum output
3.
representing
voltage
a logic 1
state.
V OHmin
-- the maximum output
4.
voltage
representing a logic 0
V state. BECE102L – DIGITAL SYSTEM DESIGN
ELECTRICAL
CHARACTERISTICS
LOGIC
LEVELS

BECE102L – DIGITAL SYSTEM DESIGN

ELECTRICAL
CHARACTERISTICS
LOGIC
LEVELS

BECE102L – DIGITAL SYSTEM DESIGN

ELECTRICAL
CHARACTERISTICS
LOGIC
LEVELS

BECE102L – DIGITAL SYSTEM DESIGN

 ELECTRICAL
CHARACTERISTICS
NOISE MARGIN

 Noise immunity is the ability to tolerate a

certain amount of unwanted voltage
fluctuation on its inputs without changing
its output state.

 A measure of a circuit’s noise immunity is

called the noise margin, which is expressed
in volts.

 There are two values of noise margin

specified for a given logic circuit: the HIGH-
level noise margin (V N H ) and the LOW-level
BECE102L – DIGITAL SYSTEM DESIGN
 ELECTRICAL
CHARACTERISTICS
NOISE MARGIN

 V N H is the difference between the lowest

possible HIGH output from a driving gate
(VOH(min)) and the lowest possible HIGH input
that the load gate can tolerate (VIH(min)).

 VNL is the betwee the

n a
difference possible that maximum
can
LOW input gate
maximum possible
tolerate
output of the drivingLOW
(VIL(max))and gate
(VOL(max)).
the
BECE102L – DIGITAL SYSTEM DESIGN
ELECTRICAL
CHARACTERISTICS
NOISE
MARGIN

BECE102L – DIGITAL SYSTEM DESIGN

 ELECTRICAL
CHARACTERISTICS
POWER DISSIPATION

 A logic gate draws current from the dc

supply voltage source, When the gate is
in the HIGH output state, current ICCH is
drawn; and in the LOW output state, a
current, ICCL, is drawn.

 As is example,
an 5 V and if
if Ithe gate
is is in aasstatic
specified 1.5 mA
V CC CCH
(non HIGH output state, the
changing)
when
power dissipation(PD) of the gate is

BECE102L – DIGITAL SYSTEM DESIGN

 ELECTRICAL
CHARACTERISTICS
PROPAGATION DELAY

 When a signal passes (propagates) through

a logic circuit, it always experiences a time,
this is delay is called the propagation delay
time.
 There
for logic are two propagation
gates delay
& tPLH.
times
tPHL specified
 tPHL: The time betweeninput pulse and
output pulse when the output is changing
HIGH to LOW.
 tPLH:The time between input pulse and
output pulse when the output is changing
BECE102L – DIGITAL SYSTEM DESIGN
ELECTRICAL
CHARACTERISTICS
PROPAGATION
DELAY

Propagation delay times

BECE102L – DIGITAL SYSTEM DESIGN
 ELECTRICAL
CHARACTERISTICS
FAN-OUT

 When the output of a logic gate is

connected to one or more inputs of other
gates, a load on the driving gate is created

 There is a limit to the number of load gate

inputs that a given gate can drive. This limit
is called the fan-out of the gate.

BECE102L – DIGITAL SYSTEM DESIGN

BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
INTRODUCTION

 In Digital Electronics, a logic family refers to

digital integrated circuit devices which
are constructed with a combination of
electronic gates.

 There are different families of logic gates.

Each family has its own characteristics,
limitations and advantages.

 Some families also have common

characteristics. Also within each family,
there is a range of voltages which may
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
INTRODUCTION
 These families are listed below:
 Diode Logic (DL)
 Resistor-Transistor Logic
(RTL)
 Diode-Transistor Logic
(DTL)
 Emitter Coupled Logic
(ECL)
 Transistor-Transistor Logic
(TTL) BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
DIODE LOGIC (DL)

 In Diode logic, all the logic is

implemented with the use of resistors and
diodes.
 In diode logic, the purpose of the diodes
is to perform OR and AND operations. It
is essential that the diode is forward
biased so that it can conduct.
 Disadvantage:
 they tend to degrade the signals quickly.
 cannot work for multiple stages
 cannot perform the NOT operation
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
RESISTOR-TRANSISTOR LOGIC (RTL)
 In RTL, all the logic is implemented with the
use of transistors and resistors.

A B T1 T2 Q
L L OFF OFF H
L H OFF ON H
H L ON OFF H
H H ON ON L

BECE102L – DIGITAL SYSTEM DESIGN

 REVIEW OF LOGIC GATE
FAMILIES
RESISTOR-TRANSISTOR LOGIC (RTL)
 Advantages:
 can be used as amplifiers
 can also be used as an betwee
interface digital and linear n
 circuits
not very expensive andare
very simple to construct
 Disadvantages:
 extratransistor is needed to
re-amplify the signal
 they draw a great amount of current
 they cannot switch at high speeds
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
DIODE-TRANSISTOR LOGIC (DTL)
 In Diode-transistor logic, all logic
the implemented with diodes and is
transistors.
 DTL has some advantages over DL and RTL.
As the diodes can perform AND and OR
operations but along with a transistor the
output signal can be amplified.

 In DTL, the signal can be restored to full

logic levels if we add a transistor at the
output of the logic gates. This results in
logic inversion.
UNIT-II : LECTURE-11 BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
DIODE-TRANSISTOR LOGIC (DTL)

 Another advantage of DTL is that the

OR operation can be performed by the
diodes instead of resistors. But the
switching speed of the transistor is
limited.
A B DA DB TR1 Q
L L FB FB OFF H
L H FB RB OFF H
H L RB FB OFF H
H H RB RB ON L

BECE102L – DIGITAL SYSTEM DESIGN

 REVIEW OF LOGIC GATE
FAMILIES
EMITTER-COUPLED LOGIC (ECL)

 In Emitter coupled logic, the

transistors are prevented from going into
deep saturation so that there are no storage
delays.

 This logic is used in applications with high

speed environment.

 In fact, it is the fastest bi-polar circuit

available today. This logic family bypasses
TTL in terms of speed.
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
EMITTER-COUPLED LOGIC (ECL)
 The logic levelsfor ECL are normally -0.9V
for high logic and -1.6 for low logic.

ECL NOT
GATE
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
TRANSISTOR-TRANSISTOR LOGIC (TTL)
 TTL has become the standard logic circuit in
many application for a number of years.
 TTL greatly decreases the manufacturing
costs because multiple emitters can be
added in the input so no extra space is
needed and a multiple input gate can be
constructed easily.
 A commercial IC package of TTL includes
three three-input gates, four two-input
gates, or two four-input gates. The
structure of the IC always remains the
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
TRANSISTOR-TRANSISTOR LOGIC (TTL)

 In transistor-transistor logic, the logic gates

are constructed around the transistors.
 TTL uses bipolar transistors to
construct its integrated circuits.
 There have been different versions of TTL:
 Standard TTL.
 High speed TTL.
 Low power TTL.
 Schcottky TTL.

BECE102L – DIGITAL SYSTEM DESIGN

REVIEW OF LOGIC GATE
FAMILIES
TRANSISTOR-TRANSISTOR LOGIC
(TTL)

BECE102L – DIGITAL SYSTEM DESIGN

 REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC
 CMOS is known for its low power
consumption and high fan-out. It is also
considered to be one of the most reliable
logic family today.

 The transistors inside the CMOS are made

from an NMOS transistor and PMOS
transistor.

 To realize the logical functions, both P-type

and N- type transistors are used. It is
currently being used in microprocessor
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC
 The gate of a MOS transistor controls the
flow of the current between the drain and
the source

 The MOS transistor can be

viewed as a simple ON/OFF
switch

BECE102L – DIGITAL SYSTEM DESIGN

 REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC - inverter
 CMOS gates are built around
the technology of the basic CMOS
inverter

 Two Transistors are enhancement mode

MOSFETs and Transistors come in
complementary pairs

 N-Channel with its source grounded & P-

Channel with its source connected to +V

 Input: gates connected together & Output:

BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC -
inverter

vdd
in out
p1

in out

in p1 n1 out n1
0 ON OFF 1
vss
1 OFF ON 0

BECE102L – DIGITAL SYSTEM DESIGN

 REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC -
NAND
vdd

a p1 p2 b
a b p1 p2 n1 n2 out
0 0 ON ON OFF OFF 1
out
0 1 ON OFF OFF ON 1
a n1

c 1 0 OFF ON ON OFF 1

b n2 1 1 OFF OFF ON ON 0

vss

BECE102L – DIGITAL SYSTEM DESIGN

 REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC -
NOR vdd

a p1
a b p1 p2 n1 n2 out
0 0 ON ON OFF OFF 1
b p2
0 1 ON OFF OFF ON 0
out
1 0 OFF ON ON OFF 0
a n1 n2 b
1 1 OFF OFF ON ON 0

vss

BECE102L – DIGITAL SYSTEM DESIGN

REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC -
EXAMPLES

C
4 INPUT
CMOS NOR GATE
D
BECE102L – DIGITAL SYSTEM DESIGN
 REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC -
AND CMOS LOGIC -
OR

BECE102L – DIGITAL SYSTEM DESIGN

REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC -
EXAMPLES

BECE102L – DIGITAL SYSTEM DESIGN

REVIEW OF LOGIC GATE
FAMILIES
CMOS LOGIC -
EXAMPLES

BECE102L – DIGITAL SYSTEM DESIGN

 REVIEW OF LOGIC GATE
FAMILIES
EXERCISE PROBLEMS
Realize following logical expressions using
CMOS logic:
1. Y = (AB+C)’
2. Y = AB’+A’B
3. Y = B’C+ ABC’
4. Y = (A(BC+D))’
5. Y = (AB+A(C+D))’
6. Y = (ABC+DE+F)
BECE102L – DIGITAL SYSTEM DESIGN
REVIEW OF LOGIC GATE
FAMILIES SUMMAR
Y

BECE102L – DIGITAL SYSTEM DESIGN