DIGITAL VLSI

DESIGN
PROGRAM ELECTIVE-1
Course Code: R5EL3101T
MODULE 3: HDL
 Digital IC Design Tools: Software Used
VLSI Design Type Description Software Used

RTL Simulation & Test correctness of HDL ModelSim, VCS

Functional Verification code (Synopsys), NC-Sim
(Cadence), VIVADO, (by
XILINX)
Synthesis RTL → Gate-level netlist Design Compiler
(Synopsys), Genus
(Cadence)

Logic Optimization Area, timing, power Design Compiler, Genus

optimization
Physical Design Layout creation following Virtuoso, Tanner EDA,
LVS (Layout Versus Microwind
Schematic) and DRC
 Importance of HDLs (Hardware Description
Language)
 Designers can write their RTL description without choosing a specific fabrication technology.

 Logic synthesis tools can automatically convert the design to any fabrication technology.

 If a new technology emerges, designers do not need to redesign their circuit.

 They simply input the RTL description to the logic synthesis tool and create a new gate-level netlist, using the
new fabrication technology.

By describing designs in HDLs, functional verification of the design can be done early in the design cycle.

 Since designers work at the RTL level, they can optimize and modify the RTL description until it meets the
desired functionality.
 Popularity of Verilog HDL
 Verilog HDL is a general-purpose hardware description language that is easy to learn and easy to use. It is similar
in syntax to the C programming language.

 Verilog HDL allows different levels of abstraction to be mixed in the same model. Thus, a designer can define a
hardware model in terms of switches, gates, RTL, or behavioral code.
 Basic Concepts
 Module: Verilog provides the concept of a module.

 A module is the basic building block in Verilog. A

module can be an element or a collection of lower-level
design blocks.

 In Verilog, a module is declared by the keyword

module.

 A corresponding keyword endmodule must appear at

the end of the module definition.

 Each module must have a module-name, which is the

identifier for the module, and a module-terminal-list,
which describes the input and output terminals of the
module.

PC:Verilog HDL: A Guide to Digital Design and Synthesis, 2nd Edition by Samir Palnitkar
 Verilog is both a behavioral and a structural language.

Internals of each module can be defined at four levels of abstraction, depending on the needs of the design.

Behavioral or algorithmic level :This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the hardware implementation details. Designing at
this level is very similar to C programming.

Dataflow level : At this level the module is designed by specifying the data flow. The designer is aware of how data flows
between hardware registers and how the data is processed in the design.

Gate level : The module is implemented in terms of logic gates and interconnections between these gates. Design at this
level is similar to describing a design in terms of a gate-level logic diagram.
Instances module ripple_adder (X, Y, S, Co);
input [3:0] X, Y;// Two 4-bit inputs
 Instantiation allows the creation of hierarchy in Verilog description output [3:0] S;
output Co;
wire w1, w2, w3;
// instantiating 4 1-bit full adders in Verilog
fulladder u1(X[0], Y[0], 1'b0, S[0], w1);
fulladder u2(X[1], Y[1], w1, S[1], w2);
fulladder u3(X[2], Y[2], w2, S[2], w3);
fulladder u4(X[3], Y[3], w3, S[3], Co);
endmodule
4-bit Ripple Carry Adder module full_adder (a,b,cin,sum,carry);
input a, b, cin;
output sum, carry;
wire c,c1,s;

half_adder ha0 (a, b, s, c);

half_adder ha1(cin, s, sum, c1);
assign carry = c | c1 ;
endmodule
module half_adder (a,b,sum,carry);
input a, b,];
output sum, carry;
Full Adder using Half adder xor x1(sum, a, b);
And A1(carry, a, b);
endmodule
[Link]
 Data Types: Verilog Basics
 Net :The size of a net is explicitly specified in a net declaration. Nets have values continuously driven on them by the outputs
of devices that they are connected to. Nets are one-bit values by default unless they are declared explicitly as vectors.
 The default value of a net is z
wire [4:0] D; // A 5-bit wire net
wor A; // 1-bit wor net
When no size is explicitly specified in a net declaration, the default size is one bit.
Here are the different kinds of net data types that are supported for synthesis are:
wire wor wand tri supply0 supply1

module WireExample (BpW, Error, Wait, Valid,

Clear);
input Error, Wait, Valid, Clear;
output BpW;
wire BpW;
assign BpW = Error & Wait;
assign BpW = Valid| Clear;
endmodule
PC: "Verilog® HDL Synthesis: A Practical Primer" by J. Bhasker Synthesized Netlist of WireExample
module UsesGates (BpW, BpR, Error, Wait, Clear);
input Error, Wait, Clear;
output BpW, BpR;
wor BpW;
wand BpR;
assign BpW = Error & Wait;
assign BpW = Valid| Clear;
assign BpR = Error^ Valid;
assign BpR = ! Clear;
endmodule

A Verilog wand (wired-AND) net type means that if multiple

drivers are connected to a wand net, the resulting value of
the net is the bit-wise AND of all the driving values.

Synthesized Netlist of UsesGates

 Register (reg): The different kinds of register types that are supported for synthesis are:
reg integer
A reg declaration explicitly specifies the size, that is, the corresponding number of bits of the variable in hardware.
Registers represent data storage elements.
Registers retain value until another value is placed onto them.
In Verilog, the term register merely means a variable that can hold a value.
Unlike a net, a register does not need a driver.
Register data types are commonly declared by the keyword reg. The default value for a reg data type is X.
For example,
reg [1:25] Cpt; // 25-bit variable
reg Bxr; // 1-bit variable When no size is explicitly specified in a reg declaration, the default is one bit.
. reg reset; // declare a variable reset that can hold its value
initial
begin
reset = 1’b1; //initialize reset to 1 to reset the digital circuit
#100 reset = l1’b0; // after 100 time units reset is deasserted
end
 Integer, and real data types are supported in Verilog.
 Integer: An integer is a general-purpose register data type used for manipulating quantities.
 Integers are declared by the keyword integer.
 Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for
purposes such as counting.
 The default width for an integer is 32 bits.
 Registers declared as data type reg store values as unsigned quantities, whereas integers store values as signed quantities.

In Verilog, numbers are unsigned by default, but you can declare

them as signed so that arithmetic is handled using two’s complement
representation.

reg signed [7:0] a = -5;

reg signed [7:0] b = 3;
reg signed [7:0] result;

initial begin
result = a + b; // result = -2
end
 Real: Real number constants and real register data types are declared with the keyword real.
 They can be specified in decimal notation (e.g., 3.14) or in scientific notation (e.g., 3e6, which is 3 X ).
 Real numbers cannot have a range declaration, and their default value is 0.
 When a real value is assigned to an integer, the real number is rounded off to the nearest integer.

real delta; // Define a real variable called delta

initial
begin
delta = 4e10; // delta is assigned in scientific notation
delta = 2.13; // delta is assigned a value 2.13
end
Few more important concepts:
 Vectors: Nets or reg data types can be declared as vectors (multiple bit widths). If bit width is not specified, the default
is scalar (1-bit)
The left number in the squared brackets is always the MSB of the vector.
In the example shown, bit 0 is the most significant bit of vector virtual-addr.
For the vector declarations shown above, it is possible to address bits or parts of vectors.

EXAMPLE 1:
wire a; // scalar net variable, default
wire [7:0] bus; // 8-bit bus
wire [31:01 busA, busB, busC; // 3 buses of 32-bit width.
reg clock; // scalar register,
reg [0 : 40] virtual-addr; // vector register, virtual address 41 bits width

EXAMPLE 2:
busA[7] // bit # 7 of vector busA
bus[2:0] // Three least significant bits of vector bus, // using virtual-
addr[0:l] //TWO most significant bits of vector virtual-addr
 Arrays: Arrays are allowed in Verilog for reg, integer, and vector register data types. Arrays are not allowed for
real variables.
integer count[0:7]; / / array of 8 count variables module rom_example
(input clk);
reg B[31:0]; //Array of 32 one-bit Boolean register variables reg [4:0] rom [7:0];
reg [4:0] port [0:7] ; //Array of 8port-ids; each port-id is 5 bits
wide initial begin
rom[0] = 5'b00000;
rom[1] = 5'b10110;
Count [5]; // 5th element of array of count variables end
port_id[3]=port_id[2] | port_id[1] always@(clk)
rom[0][1] = rom[1][2];
// The bit 1 of the first word (rom[0]) is
assigned the value of bit 2 of the second
word (rom[1]).
endmodule

 Memories: One often needs to model register files, RAMs, and ROMs.
Memories are modeled in Verilog simply as an array of registers.
Each element of the array is known as a word. Each word can be one or more bits.

reg [7 : 0] membyte [0 : 1023]; // memory membyte with 1K 8-bit words (1 byte)

 Verilog Operators
 Logical Operators : Used mainly as condition in if-else statements.
 They return either 0 (FALSE) or 1 (TRUE)

Symbol Operation
&& Logical AND
! Logical NOT
|| Logical OR

 Symbol Operation
Bitwise Operators: Operands operates on Bits
& AND
~ NOT
| OR
^ XOR
~^ XNOR
~& NAND
module logical_example; module logical_ifelse;
reg a, b; reg a, b, c;
reg [3:0] x, y; initial begin
reg result1, result2, result3, result4; a = 1; b = 0; c = 1;
if (a && c)
initial begin $display("Condition (a && c) is TRUE");
a = 1'b0; else
b = 1'b1; $display("Condition (a && c) is FALSE");
result1 = !a; // logical NOT: !0 = 1 if (a || b)
result2 = a && b; // logical AND: 0 && 1 = $display("Condition (a || b) is TRUE");
0 else
result3 = a || b; // logical OR : 0 || 1 = 1 $display("Condition (a || b) is FALSE");
x = 4'b0000; // treated as FALSE if (!b)
y = 4'b1010; // treated as TRUE (non-zero) $display("Condition (!b) is TRUE");
result4 = (x || y); // since x=0, y≠0 => TRUE else
end $display("Condition (!b) is FALSE");
endmodule end
endmodule
module bitwise_example (a,b, and_result, or_result, xor_result,
xnor_result, not_result);
input [3:0] a, b;
output [3:0] and_result, or_result, xor_result, xnor_result,
not_result;

initial begin
a = 4'b1100; // 12 in decimal
b = 4'b1010; // 10 in decimal
end
assign and_result = a & b; // bitwise AND
assign or_result = a | b; // bitwise OR
assign xor_result = a ^ b; // bitwise XOR
assign xnor_result = a ~^ b; // bitwise XNOR Synthesized Hardware for a_vec & b_vec ;
assign not_result = ~a; // bitwise NOT Each a_vec and b_vec are 3 bits each
end
endmodule
 Arithmetic Operators: + (add) , - (subtractor) , * (multiply), / (division), % (modulus)

module adder(A,B,Y);
input [2:0] A, B;
output [2:0] Y;
assign Y=A+B;
endmodule

Synthesized Netlist of adder

module arithmetic_example (a,b,sum,diff,mod,prod,quotient;
input [4:0] a, b; // 4-bit inputs
output [5:0] sum, diff;
output [4:0] mod;
output [7:0] prod; // product can be larger than 8 bits

assign sum = a + b; // Addition

assign diff = a - b; // Subtraction
assign prod = a * b; // Multiplication
assign mod = a % b; // Modulus

end
endmodule
 Relational Operators: The relational operators // unsigned relational ops
assign a_lt_b = (a < b);
supported for synthesis are: >, <, <=, >=
assign a_gt_b = (a > b);
 assign a_le_b = (a <= b);
If variables of a reg type or a net type are compared,
assign a_ge_b = (a >= b);
an unsigned relational operator is synthesized. (==, !=) — treats x/z as unknown (can propagate X)

 If integer variables are compared, then a signed assign a_eq_b = (a = = b);

relational operator is synthesized. assign a_ne_b = (a != b);
// case equality (= = =, != =) compares bit-for-bit
 Output type : The result is 1-bit value:1 (true)0 including X/Z

(false)Even though you may assign it to a multi-bit assign a_case_eq_b = (a = = = b);

wire/reg, only 1 or 0 is produced. assign a_case_ne_b = (a != = b);
 Equality operators: = =, ! =, ! = =, = = =

 The operators === (case equality) and !== (case inequality) are not supported for synthesis.

 Equality operators are modeled similar to arithmetic operators in terms of whether signed or unsigned comparison is to be
made.

 = = = and ! = = are case equality / inequality they compare bit patterns including x and z.

 Use these when you need to distinguish x/z from 0/1.

 In synthesis, = = =/! = = are not synthesizable to simple hardware in the same way; they are mainly for testbenches and
simulation checks.

 Here is an example that uses signed numbers. Note that in this case, the operands of the equality operator are of integer type
because values of this type represent signed numbers.
 module shift_operator (a, b, result);
 Shift operators: Left shift << and Right shift >> input [7:0] a;
and Arithmetic left shift <<< and Arithmetic input signed [7:0] b;
output reg [7:0] result;
right shift >>> initial begin
a = 8'b00110110; // 54 in decimal
 The vacated bits are filled with 0. << and <<< b = -8'd6; // signed -6 in decimal (11111010 in 2's complement)

behave the same (just shift left and pad with 0). // Logical left shift (adds zeros on the right)
result = a << 2; // 00110110 << 2 = 11011000 (216=54*)
 >> pads with 0s (logical shift). >>> pads with sign
// Logical right shift (adds zeros on the left)
bit (arithmetic shift, keeps the sign of signed result = a >> 2; // 00110110 >> 2 = 00001101 (13=54/ )
numbers).
// Arithmetic left shift (same as logical left shift)
 Left shift also means multiplication with ; n being result = b <<< 2; // -6 (11111010) <<< 2 = 11101000
the number of shifts
// Arithmetic right shift (fills with sign bit instead of 0)
result = b >>> 2; // -6 (11111010) >>> 2 = 11111110 (-2)
 Right shift also means division with ; n being the end
number of shifts endmodule
 Reduction operator: Reduction operators are and (&), nand (~&a), or ( | ), nor (~| ), xor (^), and
xnor (-^).
 Reduction operators take only one operand.
 Reduction operators perform a bitwise operation on a single vector operand and yield a l-bit result.
 Reduction operators work bit by bit from right to left.
 Reduction nand, reduction nor, and reduction xnor are computed by inverting the result of the reduction and, reduction or, and
reduction xor, respectively.

X=4’b1010

&X; // Equivalent to 1 & 0 & 1 & 0. Results in 1’b0

|X; // Equivalent to 1 I 0 I 1 I 0. Results in 1’b1
^X; // Equivalent to 1 ^ 0 ^ 1 ^ 0. Results in 1’b0 Reduction and operation

/A reduction xor or xnor can be used for even or odd parity //generation of a vector.

~X will do bitwise NOT of the bits and the output is not 1 bit: X=4’b1010;
~X=4’b0101
This is because NOT gate is not multi-input bit gate unlike AND, NOR, NAND,
Part Select: In Verilog, part-select is used to pick a subset of bits from a vector Bit select:
module part_select_example (b0, b1, n0, n1, data);
output [15:0] data;
output [7:0] b0, b1; module bit_select_example (data, bit3, bit7);
input [3:0] n0, n1,n2; input [7:0] data;
output bit3, bit7;
initial begin
data = 16'b1101_1010_0110_1111; initial begin
data = 8'b10110110;
// Fixed part-select
b0 = data[7:0]; // lower 8 bits
b1 = data[15:8]; // upper 8 bits
bit3 = data[3];
n0 = data[3:0]; // lowest 4 bits bit7 = data[7];
n1 = data[11:8]; // bits [11:8] end
n2= {data[15], data [2:0]}; endmodule
end
endmodule

Output:
data = 1101101001101111
b0 = 01101111 (lower byte)
b1 = 11011010 (upper byte)
n0 = 1111 (lowest 4 bits)
n1 = 0110 (bits [11:8])
N2=1111
Conditional Expression: <condition>: <expression1>: <expression2>

If the condition is true then expression 1 is select otherwise expression 2

module conditional_example (a,b,max);

input [3:0] a, b;
output [3:0] max;

initial begin
a = 4'd7;
b = 4'd9;

// Conditional expression: if a > b then max = a else max = b

max = (a > b) ? a : b;
end
endmodule
 Operator Preferences: If no parentheses are used to separate parts of expressions, Verilog enforces the
following precedence.
 It is recommended that parentheses be used to separate expressions except in case of unary operators or
when there is no ambiguity.
module precedence_wrong(
input [3:0] a, b, c;
output [4:0] result);

initial begin
a = 4'd5; // 0101
b = 4'd3; // 0011
c = 4'd2; // 0010
end
assign result = a + b & c;
end
endmodule

“&” has a higher preference than “+”

So, result = a + (b & c); and output= 0101+( 0011 & 0010)=0101+0010=0111
However, if assign = (a+b) & c; output = (0101+0011) & 0010=1000&0010 = 0000
 Structural/ Gate Modelling
 Gate level primitives can be instantiated in a model using gate instantiation. The following gate level primitives
are supported for synthesis.
and, nand, or, not, nor, xor, xnor, buf, bufif0, bufif1, notif0, notif1
 buf – Buffer
 bufif0 – Tri-state buffer, enabled when control = 0
 bufif1 – Tri-state buffer, enabled when control = 1
 notif0 – Tri-state inverter, enabled when control = 0
 notif1 – Tri-state inverter, enabled when control = 1
Truth Table for the GATE primitives
module buf_example (a,y); module bufif0_example(a, ctrl, y); module notif0_example;

input a; input a, ctrl; reg a, ctrl;

output y; wire y;
output y;

// bufif0 (output, input, control) // notif0 (output, input, control)

// buf (output, input)
bufif0 b1 (y, a, ctrl); notif0 n1 (y, a, ctrl);
buf b1 (y, a);

initial begin initial begin

initial begin a = 1; ctrl = 0; #10; a = 1; ctrl = 0;
a = 0; #10; // y = a (since ctrl = 0) #10;
a = 1; #10; ctrl = 1; #10; // y = ~a (since ctrl = 0)

end // y = high impedance (z) ctrl = 1;

end #10;
endmodule

endmodule // y = z (disabled)
y=a with a delay
end
endmodule
 Example: Gate Level Multiplexer

module mux4to1_gate (
input i0, i1, i2, i3, // Data inputs
input s0, s1, // Select lines
output out); // Output
wire s0n, s1n, y0, y1, y2, y3;
not (s0n, s0);
not (s1n, s1);
and (y0, i0, s0n, s1n);
and (y1, i1, s0, s1n);
and (y2, i2, s0n, s1);
and (y3, i3, s0, s1);
or (out, y0, y1, y2, y3);
endmodule

Fig. Gate Level 4×1 Multiplexer

Fig. 4×1 Multiplexer

 Gate Delays:
 Rise delay The rise delay is associated with a gate output transition to a 1 from another value.

 Fall Delay: The fall delay is associated with a gate output transition to a o from another value
 Boolean expression: out=(a.b)+c module testbench ();
reg a, b, c;
module D (out, a, b, c);
wire out;
output out; D d1(out, a, b, c);
input a,b,c; initial
begin
wire e; a= 1’b0;
and # (5) a1 (e, a, b) ; //Delay of 5 on b= 1’b0;
gate a1 C= 1’b0;
#10 a= 1’b1; b= 1’b1; c= 1’b1;
or #(4) o1(out, e, c); //Delay of 4 on gate #l0 B= l’b1; C= 1’b0; #20
01 end
endmodule endmodule
 Dataflow Modelling
 For small circuits, the gate-level modeling approach works very well because the number of gates is limited and
the designer can instantiate and connect every gate individually.

 However, in complex designs the number of gates is very large.

 Thus, designers can design more effectively if they concentrate on implementing the function at a level of
abstraction higher than gate level.

 Dataflow modeling provides a powerful way to implement a design.

 Verilog allows a circuit to be designed in terms of the data flow between registers and how a design processes
data rather than instantiation of individual gates.
 Continuous Assignment:
 A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net.
 A continuous assignment replaces gates in the description of the circuit and describes the circuit at a higher level of
abstraction.
 A continuous assignment statement starts with the keyword assign
 Continuous assignments have the following characteristics:

1. The LHS of an assignment must always be a scalar or vector net or a concatenation of scalar and vector nets. It cannot
be a scalar or vector register.

2. Continuous assignments are always active. The assignment expression is evaluated as soon as one of the RHS operands
changes and the value is assigned to the LHS net.

3. The operands on the RHS can be registers or nets or function calls.

Registers or nets can be scalars or vectors.

4. Delay values can be specified for assignments in terms of time units.

// Continuous assignment
out is a net. il and i2 are nets assign
out = il & i2;
// addr is a 16-bit vector net
// addrl and addr2 are 16-bit vector registers
assign addr[15:0] = addr_1[15:0] + addr2[15:0];
// Concatenation
assign {c-out, sum[3:0]) = a[3:0] + b[3:01 + c-in;
 Delays

assign #10 out = in1 & in2; // Delay in a continuous assign

 Examples:  Examples:
module mux4-to-l (out, iO, il, i2, i3, sl, SO); // port / Define a 4-bit full adder by using dataflow
declarations from the 1/0 diagram statements
output out;
module fulladd4 (sum, c-out, a, b, c-in) ;
input iO, il, i2, i3;
output [3:0] sum;
input s1, ;
output c_out;
//Logic equation for out
input [3: 0] a, b;
assign out = (~s1) & (~s0) & i0) |
input c_in;
(~s1) & s0 & i1) I
assign {c_out, sum) = a + b + c_in;
(s1 & ~s0 & i2) I
endmodule
(s1 & s0 & i3) ;
//assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;
endmodule
 Behavioural Modelling
 With the increasing complexity of digital design, it has become vitally important to make wise design decisions
early in a project.

 Architectural evaluation takes place at an algorithmic level where the designers do not necessarily think in terms
of logic gates or data flow but in terms of the algorithm they wish to implement in hardware.

 Designer describes the behavior of the circuit.

 Behavioral modeling represents the circuit at a very high level of abstraction

Structured Procedures :
 There are two structured procedure statements in Verilog: always and initial
 All other behavioral statements can appear only inside these structured procedure statements.
 Verilog is a concurrent programming language.
 Activity flows in Verilog run in parallel rather than in sequence.
 Each always and initial statement starts at simulation time 0.
 Each block executes independently and cannot be nested inside another always or initial.
 Initial Statements module stimulus;
 An initial block starts at time 0, executes reg x,y, a,b, m;
exactly once during a simulation, and then does Initial
not execute again. m = 1’b0;
initial
 If there are multiple initial blocks, each block begin
starts to execute concurrently at time 0. #5 a = 1’b1;
time statement executed
 Each block finishes execution independently of #25 b = 1’b0;
0 m = 1’b0;
other blocks. end
5 a = 1’b1;

initial
Multiple behavioral statements must be 10 X = 1’b0;
begin
grouped, typically using the keywords begin 30 b = 1’b0;
#l0 x = 1’b0;
and end. 35 y = 1’b1;
#25 y = 1’b1;
 50 $finish;
If there is only one behavioral statement, end
grouping is not necessary. initial #50
$finish;
endmodule

In the above example, the three initial statements start to execute

in parallel at time 0. If a delay #<delay> is seen before a
statement, the statement is executed <delay> time units after the
current simulation time.
 In Simulation
initial is allowed.
It runs once at time 0 and is often used to:
Set starting values,
Apply stimulus in testbenches,
Run a block of code just once.
 ASIC synthesis:
initial blocks are NOT synthesizable.
Because real hardware doesn’t have the concept of "time 0 initialization“
 In FPGA synthesis:
Many FPGA tools do allow some forms of initial for register/ROM initialization.
Example (synthesizable on FPGAs like Xilinx/Intel):
reg [7:0] counter = 8'd0; // initialized using initial semantics

But still, complex initial blocks with loops/delays are not synthesizable.
 always statement:
 The always statement starts at time 0 and executes the statements in the always block continuously in a looping fashion.
 This statement is used to model a block of activity that is repeated continuously in a digital circuit.
 An example is a clock generator module that toggles the clock signal every half cycle.
 In real circuits, the clock generator is active from time 0 to as long as the circuit is powered on.

module clock-gen;
reg clock;
initial clock = l1’b0;
always #10 clock = ~clock;
initial #l000 $finish;
endmodule

always statement starts at time 0 and executes the statement clock = -clock every 10 time units.
Notice that the initialization of clock has to be done inside a separate initial statement.
If we put the initialization of clock inside the always block, clock will be initialized every time the always is entered.
Also, the simulation must be halted inside an initial statement. If there is no $stop or $finish statement to halt the simulation,
the clock generator will run forever.
 Procedural Assignments:
 Procedural assignments update values of reg, integer, or real variables.
The value placed on a variable will remain unchanged until another procedural assignment updates the variable with
a different value.
The left-hand side of a procedural assignment can be one of the following:
A reg, integer, or real register variable or a memory element
A bit select of these variables (e.g., addr[10])
A part select of these variables (e.g., addr[31:16])
A concatenation of any of the above
 There are two types of procedural assignment statements: blocking and nonblocking:
1. Blocking
2. Non-blocking
Blocking Procedural Statements:
 Blocking assignment statements are executed in the order they are specified in a sequential block.
 A blocking assignment will not block execution of statements that follow in a parallel block.
reg x, y, z;
• Statement y = 1 is executed only after x = 0 is executed.
reg r15: 01 reg_a, reg_b;
integer count; • The behavior in a particular block is sequential in a begin-end block if
initial
begin blocking statements are used, because the statements can execute only
x=0; y=1; z = 1; in sequence.
count = 0;
• All statements x = 0 through reg_b = reg_a are executed at time 0.
reg_a = 16’b0;
reg_b = reg_a; • Statement reg_a[2] = 0 at time = 15
#15 reg_a[2] = 1’b1;
• Statement reg_bl15:13] = {x, y, z} at time = 25
#10 reg_b[15:13] = {x, y, z}
count = count + 1; • Statement count = count + 1 at time = 25
end
• Since there is a delay of 15 and 10 in the preceding statements,
count = count + 1 will be executed at time = 25 units
 Nonblocking Assignments:
 Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a
sequential block.
 A <= operator is used to specify nonblocking assignments.
 Note that this operator has the same as a relational operator, less-than-equal-to.
 The operator <= is interpreted as a relational operator in an expression and as an assignment operator in the context of a
nonblocking assignment.