Computer Organization

Topics covered:
Memory subsystem
 Memory hierarchy

 A big challenge in the design of a computer system is to

provide a sufficiently large memory, with a reasonable
speed at an affordable cost.
 Static RAM:
 Very fast, but expensive, because a basic SRAM cell has a
complex circuit making it impossible to pack a large
number of cells onto a single chip.
 Dynamic RAM:
 Simpler basic cell circuit, hence are much less expensive,
but significantly slower than SRAMs.
 Magnetic disks:
 Storage provided by DRAMs is higher than SRAMs, but is
still less than what is necessary.
 Secondary storage such as magnetic disks provide a large
amount of storage, but is much slower than DRAMs.

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 Memory hierarchy (contd..)

 All these types of memory units are employed

effectively in a computer.
 SRAM -- Smaller units where speed is critical, namely,
cache memories.
 DRAM -- Large, yet affordable memory, namely, main
memory.
 Magnetic disks -- Huge amount of cost-effective storage.
 Computer memory can be viewed as a hierarchy.

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 Memory hierarchy (contd..)

Processor •Fastest access is to the data held in

processor registers. Registers are at
Registers the top of the memory hierarchy.
Increasing •
Increasing Increasing Relatively small amount of memory that
size speed cost per bit can be implemented on the processor
Primary L1
cache chip. This is processor cache.
•Two levels of cache:
Level 1 (L1) cache is on the processor chip.
Level 2 (L2) cache is in between main memory
Secondary L2 and processor.
cache
•Next level is main memory, implemented
as SIMMs. Much larger, but much slower
than cache memory.
Main •Next level is magnetic disks. Huge amount
memory of inexpensive storage.
•Speed of memory access is critical, the
idea is to bring instructions and data
Magnetic disk
that will be used in the near future as
secondary close to the processor as possible.
memory

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 Cache memories

 Processor is much faster than the main memory.

 As a result, the processor has to spend much of its time
waiting while instructions and data are being fetched from
the main memory.
 Major obstacle towards achieving good performance.
 Speed of the main memory cannot be increased beyond
a certain point.
 Cache memory is an architectural arrangement which
makes the main memory appear faster to the processor
than it really is.
 Cache memory is based on the property of computer
programs known as “locality of reference”.

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 Locality of reference

 Analysis of programs indicates that many instructions in

localized areas of a program are executed repeatedly
during some period of time, while the others are
accessed relatively less frequently.
 These instructions may be the ones in a loop, nested loop
or few procedures calling each other repeatedly.
 This is called “locality of reference”.

 Temporal locality of reference:

 Recently executed instruction is likely to be executed
again very soon.
 Spatial locality of reference:
 Instructions with addresses close to a recently instruction
are likely to be executed soon.

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 Locality of reference (contd..)

 Cache memory is based on the concept of locality of

reference.
 If active segments of a program are placed in a fast cache
memory, then the execution time can be reduced.
 Temporal locality of reference:
 Whenever an instruction or data is needed for the first
time, it should be brought into a cache. It will hopefully be
used again repeatedly.
 Spatial locality of reference:
 Instead of fetching just one item from the main memory to
the cache at a time, several items that have addresses
adjacent to the item being fetched may be useful.
 The term “block” refers to a set of contiguous addresses
locations of some size.

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 Cache memories

Main
Processor Cache
memory

•Processor issues a Read request, a block of words is transferred from the main memory
to the cache, one word at a time.
•Subsequent references to the data in this block of words are found in the cache.
•At any given time, only some blocks in the main memory are held in the cache.
•Which blocks in the main memory are in the cache is determined by a “mapping function”.
•When the cache is full, and a block of words needs to be transferred from the main
memory, some block of words in the cache must be replaced. This is determined by a
“replacement algorithm”.

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 Cache memories (contd..)

•Existence of a cache is transparent to the processor. The processor issues Read and
Write requests in the same manner.

•If the data is in the cache it is called a Read or Write hit.

•Read hit:
- The data is obtained from the cache.

•Write hit:
- Cache is a replica of the contents of the main memory.
- Contents of the cache and the main memory may be updated simultaneously.
This is the write-through protocol.
- Update the contents of the cache, and mark it as updated by setting a bit known
as the dirty bit or modified bit.
The contents of the main memory are updated when this block is replaced.
This is write-back or copy-back protocol.

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 Cache memories (contd..)
•If the data is not present in the cache, then a Read miss or Write miss occurs.

•Read miss:
- Block of words containing this requested word is transferred from the memory.
- After the block is transferred, the desired word is forwarded to the processor.
- The desired word may also be forwarded to the processor as soon as it is
transferred without waiting for the entire block to be transferred. This is called
load-through or early-restart.

•Write-miss:
- Write-through protocol is used, then the contents of the main memory are
updated directly.
- If write-back protocol is used, the block containing the addressed word is first
brought into the cache. The desired word is overwritten with new information.

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 Mapping functions

 Mapping functions determine how memory blocks are

placed in the cache.
 A simple processor example:
 Cache consisting of 128 blocks of 16 words each.
 Total size of cache is 2048 (2K) words.
 Main memory is addressable by a 16-bit address.
 Main memory has 64K words.
 Main memory has 4K blocks of 16 words each.
 Consecutive addresses refer to consecutive words.
 Three mapping functions:
 Direct mapping
 Associative mapping
 Set-associative mapping.

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 Direct mapping •Block j of the main memory maps to j modulo 128 of
the cache.
Main
memory
Block 0 Memory Blocks 0,128,256, …maps to cache block 0.
Memory Blocks 1, 129, 257, …maps to cache block 1.
Cache Block 1
And so on.
tag
Block 0 •More than one memory block is mapped onto the same
tag
Block 1
position in the cache.
•May lead to contention ‫نزاع‬for cache blocks even if the
Block 127 cache is not full.
Block 128 •Resolve the contention by allowing new block to
tag replace the old block, leading to a trivial replacement
Block 127 Block 129
algorithm.
•Memory address is divided into three fields:
- Low order 4 bits determine one of the 16
words in a block.
Block 255 - When a new block is brought into the cache,
Tag Block Word
Block 256 the next 7 bits determine which cache block this
5 7 4
new block is placed in.
Block 257
Main memory address - High order 5 bits determine which of the possible
32 set of blocks of memory is currently present in the
cache. These are tag bits. = No of Blocks of memory / No
of Blocks of cache = 4096/128 = 32 = 2^5
Block 4095 •Simple to implement but not very flexible.

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 Associative mapping
Main
memory
Block 0 •Main memory block can be placed into any cache
Block 1
position.
Cache
•Memory address is divided into two fields:
tag
Block 0 - Low order 4 bits identify the word within a block.
tag
Block 1 - High order 12 bits or tag bits identify a memory
block when it is resident in the cache.
Block 127
•Flexible, and uses cache space efficiently.
Block 128 •Replacement algorithms can be used to replace an
tag
Block 129
existing block in the cache when the cache is full.
Block 127
•Cost is higher than direct-mapped cache because of
the need to search all 128 patterns to determine
whether a given block is in the cache.
Block 255
Tag Word
Block 256
12 4
Block 257
Main memory address

Block 4095

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 Set-Associative mapping
Main
Cache memory
Block 0 Set-associative mapping combination of direct and
tag Block 1
associative mapping.
Block 0
Set 0
tag
Block 1 Blocks of cache are grouped into sets.
tag Mapping function allows a block of the main
Block 2
Set 1 memory to reside in any block of a specific set.
tag Block 63
Block 3 Divide the cache into 64 sets, with two blocks per set.
Block 64 Memory block 0, 64, 128 etc. map to set 0, and they
Block 65
can occupy either of the two positions.
Memory address is divided into three fields:
tag
Block 126
- Low order 4 bits identify the word within a block.
Set 63 - 6 bit field determines the set number.
tag
Block 127 - High order 6 bit fields are compared to the tag
Block 127
fields of the two blocks in a set.
Block 128 Tag size = No of Blocks of memory / No of sets of
Block 129
cache = 4096/64 = 64= 2^6
Tag Set Word
Number of blocks per set is a design parameter.
6 6 4
- One extreme is to have all the blocks in one set,
Main memory address requiring no set bits (fully associative mapping).
- Other extreme is to have one block per set, is
Block 4095
the same as direct mapping.
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 Cache memories (contd..)
•A bit called as “valid bit” is provided for each block.
•If the block contains valid data, then the bit is set to 1, else it is 0.
•Valid bits are set to 0, when the power is just turned on.
•When a block is loaded into the cache for the first time, the valid bit is set to 1.

•Data transfers between main memory and disk occur directly bypassing the cache.
•When the data on a disk changes, the main memory block is also updated.
•However, if the data is also resident in the cache, then the valid bit is set to 0.

•What happens if the data in the disk and main memory changes and the write-back
protocol is being used?
•In this case, the data in the cache may also have changed and is indicated by the
dirty bit.
•The copies of the data in the cache, and the main memory are different. This is
called the cache coherence problem.
•One option is to force a write-back before the main memory is updated from the disk..

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 Replacement algorithms
• Direct-mapped cache, the position that each memory block occupies in the cache is fixed.
As a result, the replacement strategy is trivial.
• Associative and set-associative mapping provide some flexibility in deciding which memory
block occupies which cache block.
When a new block is to be transferred to the cache, and all the positions it may occupy are full,
which block in the cache should be replaced?

• Locality of reference suggests that it may be okay to replace the block that has gone the longest
time without being referenced.
This block is called Least Recently Used (LRU) block, and the replacement strategy is called
LRU replacement algorithm.
LRU algorithm has been used extensively.
It provides poor performance in some cases.
Performance of the LRU algorithm may be improved by introducing a small amount of
randomness into which block might be replaced.

Other replacement algorithms include removing the “oldest” block. However, they disregard
the locality of reference principle and do not perform as well.

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 Performance considerations

 A key design objective is to achieve the best possible

performance at the lowest possible cost.
 Price/performance ratio is a common measure.
 Performance of a processor depends on:
 How fast machine instructions can be brought into the
processor for execution.
 How fast the instructions can be executed.

 Memory hierarchy described earlier was created to

increase the speed and size of the memory at an
affordable cost.
 Data need to be transferred between various units of
this hierarchy as well.
 Speed and efficiency of data transfer between these
various memory units also impacts the performance.

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 Interleaving

 Main memory of a computer is structured as a collection

of modules.
 Each module has its own address buffer register (ABR) and
data buffer register (DBR).
 Memory access operations can proceed in more than
one module increasing the rate of transfer of words to
and from the main memory.
 How individual addresses are distributed over the
modules is critical in determining how many modules
can be kept busy simultaneously.

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 Interleaving (contd..)
k bits m bits
Module Address in module MM address

ABR DBR ABR DBR ABR DBR

Module Module Module

0 i n- 1

•Consecutive words are placed in a module.

•High-order k bits of a memory address determine the module.
•Low-order m bits of a memory address determine the word within a module.
•When a block of words is transferred from main memory to cache, only one module
is busy at a time.
•Other modules may be involved in data transfers between main memory and disk.

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 Interleaving (contd..)
m bits k bits

Address in module Module MM address

ABR DBR ABR DBR ABR DBR

Module Module Module

k
0 i 2 - 1

Consecutive words are located in consecutive modules.

Low-order k bits select a module.
High-order k bits select a word location within that module.
Consecutive addresses can be located in consecutive modules.
While transferring a block of data, several memory modules can be kept busy at
the same time.
Faster access and high memory utilization.
This is called “Memory interleaving”.
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 Performance enhancements
Write buffer
Write-through:
•Each write operation involves writing to the main memory.
•If the processor has to wait for the write operation to be complete, it slows down the
processor.
•Processor does not depend on the results of the write operation.
•Write buffer can be included for temporary storage of write requests.
•Processor places each write request into the buffer and continues execution.
•If a subsequent Read request references data which is still in the write buffer, then
this data is referenced in the write buffer.

Write-back:
•Block is written back to the main memory when it is replaced.
•If the processor waits for this write to complete, before reading the new block, it is
slowed down.
•Fast write buffer can hold the block to be written, and the new block can be read first.

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 Performance enhancements
Prefetching

•New data are brought into the processor when they are first needed.
•Processor has to wait before the data transfer is complete.
•Prefetch the data into the cache before they are actually needed, or a before a Read
miss occurs.
•Prefetching should occur (hopefully) when the processor is busy executing
instructions that do not result in a read miss.
•Prefetching can be accomplished through software by including a special instruction
in the machine language of the processor.
- Inclusion of prefetch instructions increases the length of the programs.
•Prefetching can also be accomplished using hardware:
- Circuitry that attempts to discover patterns in memory references and then
prefetches according to this pattern.

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 Performance enhancements
Lockup-Free Cache

•Prefetching scheme does not work if it stops other accesses to the cache until the
prefetch is completed.
•A cache of this type is said to be “locked” while it services a miss.
•Cache structure which supports multiple outstanding misses is called a lockup
free cache.
•Since only one miss can be serviced at a time, a lockup free cache must include
circuits that keep track of all the outstanding misses.
•Special registers may hold the necessary information about these misses.

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