Module 5
Basic Processing Unit
In this module you will learn about
✓How a processor executes instructions.
✓The internal functional units of a processor and how they are
interconnected
✓Hardware for generating internal control signals
✓The microprogramming approach
✓Micro program organization
SOME FUNDAMENTAL CONCEPTS
➢ To execute a program, the processor fetches one instruction at a time and
performs the operations specified. Instructions are fetched from successive
memory locations until a branch or a jump instruction is encountered.
➢ The processor keeps track of the address of the memory location
containing the next instruction to be fetched using the program counter, PC.
➢ After fetching an instruction, the contents of the PC are updated to point
to the next instruction in the sequence. A branch instruction may load a different
value into the PC.
➢Another key register in the processor is the instruction register, IR.
•Suppose that each instruction comprises 4 bytes, and that it is stored in one memory
word. To execute an instruction, the processor has to perform the following three steps:
1. Fetch the contents of the memory location pointed to by the PC. The contents of
this location are interpreted as an instruction to be executed. Hence, they are loaded
into the IR. Symbolically, this can be written as
• IR ← [[PC]]
2. Assuming that the memory is byte addressable, increment the contents of the PC by
4, that is,
• PC ← [PC] +4
3. Carry out the actions specified by the instruction in the IR.
➢ In cases where an instruction occupies more than one word, steps 1 and
2 must be repeated as many times as necessary to fetch the complete
instruction. These two steps are usually referred to as the fetch phase; step 3
constitutes the execution phase.
•Bus organization design inside processor
➢ Figure 1.1 shows an organization in which the arithmetic and logic unit
(ALU) and all the registers are interconnected via a single common bus. This
bus is internal to the processor and should not be confused with the external
bus that connects the processor to the memory and I/O devices.
Figure 1.1. Single bus organization of the datapath
inside a processor
• The data and address lines of the external memory bus are shown in Figure 1.1
connected to the internal processor bus via the memory data register, MDR, and the
memory address register, MAR, respectively
➢ Register MDR has two inputs and two outputs. Data may be loaded into MDR either
from the memory bus or from the internal processor bus. The data stored in MDR may
be placed on either bus.
➢ The input of MAR is connected to the internal bus, and its output is connected to
the external bus.
➢ The control lines of the memory bus are connected to the instruction decoder and
control logic block. This unit is responsible for issuing the signals that control the
operation of all the units inside the processor and for interacting with the memory bus.
➢The number and use of the processor registers R0 through R(n - 1) vary considerably from one
processor to another.
➢ Registers may be provided for general-purpose use by the programmer. Some may be dedicated as
special-purpose registers, such as index registers or stack pointers.
➢ Three registers, Y, Z, and TEMP in Figure 1.1, have not been mentioned before. These
registers are transparent to the programmer, that is, the programmer need not be concerned
with them because they are never referenced explicitly by any instruction.
➢ They are used by the processor for temporary storage during execution of some
instructions.
➢ These registers are never used for storing data generated by one instruction for later use by
another instruction.
➢The multiplexer MUX selects either the output of register Y or a constant
value 4 to be provided as input A of the ALU.
➢The constant 4 is used to increment the contents of the program counter.
➢We will refer to the two possible values of the MUX control input Select as
Select4 and
• SelectY for selecting the constant 4 or register Y, respectively.
➢ As instruction execution progresses, data are transferred from one register
to another; often passing through the ALU to perform some arithmetic or
logic operation.
➢The instruction decoder and control logic unit is responsible for
implementing the actions specified by the instruction loaded in the IR
register.
➢ The decoder generates the control signals needed to select the registers
involved and direct the transfer of data.
➢The registers, the ALU, and the interconnecting bus are collectively referred
to as the datapath.
• Instruction Execution
With few exceptions, an instruction can be executed by performing one or more of
the following operations in some specified sequence:
✓Transfer a word of data from one processor register to another or to the ALU.
✓Perform arithmetic or a logic operation and store the result in a processor register.
✓Fetch the contents of a given memory location and load them into a processor
register.
✓Store a word of data from a processor register into a given memory location.
REGISTER TRANSFERS
➢ Instruction execution involves a sequence of steps in which data are transferred from
one register to another.
➢ For each register, two control signals are used to place the contents of that register
on the bus or to load the data on the bus into the register. This is represented
symbolically in Figure 1 .2.
➢ The input and output of register Ri are connected to the bus via switches
controlled by the signals Ri in and Riout, respectively.
➢ When Riin is set to 1, the data on the bus are loaded into Ri.
➢ Similarly, when Ri out , is set 1, the contents of register Ri are placed on the bus.
While Riout, is equal to 0, the bus can be used for transferring data from other
registers.
Suppose that we wish to transfer the contents of register R1 to register R4. This can be accomplished as follows:
1. Enable the output of register R1 by setting R1out, to 1. This places the contents of Rl on the processor bus.
2. Enable the input of register R4 by setting R4in to 1. This loads data from the processor bus into register R4.
Figure 1.2: Input and Output
gating for the registers in
Figure 1.1
➢ All operations and data transfers within the processor take place
within time periods defined by the processor clock. The control
signals that govern a particular transfer are asserted at the start of
the clock cycle.
➢ In our example, R1out and R4in are set to 1. The registers consist
of edge-triggered flip- flops. Hence, at the next active edge of the
clock, the flip-flops that constitute R4 will load the data present at
their inputs. At the same time, the control signals R1out and R4in
will return to 0.
•Implementation for one bit of register Ri
➢An implementation for one bit of register Ri is shown in Figure 1.3
as an example.
➢ A two-input multiplexer is used to select the data applied to the
input of an edge-triggered D flip-flop.
➢ When the control input Riin is equal to 1, the multiplexer selects
the data on the bus. This data will be loaded into the flip-flop at the
rising edge of the clock.
➢When Riin =0, multiplexer feeds back the value currently stored
in the flip-flop.
➢The Q output of the flip-flop is connected to the bus via a tri-state
gate.
➢ When Riout =0, the gate's output is in the high-impedance
(electrically disconnected) state. This corresponds to the open-
circuit state of a switch. When Riout = 1, the gate drives the bus to
0 or 1, depending on the value of Q.
Figure 1.3: Input and Output gating for one registers bit
2. PERFORMING AN ARITHMETIC OR LOGIC OPERATION
The ALU is a combinational circuit that has no internal storage. It
performs arithmetic and logic operations on the two operands applied to its
A and B inputs.
➢ In architecture diagram, one of the output of the multiplexer MUX and
the other operand is obtained directly from the bus.
➢ The result produced by the ALU is stored temporarily in register Z.
Therefore, a sequence of operations to add the contents of register R1 to those of
register R2 and store the result in register R3 is (Add R1,R2, R3)
1.R1out, Yin
2.R2out, Select Y, Add, Zin
[Link], R3in
➢The signals whose names are given in any step are activated for the duration of the
clock cycle corresponding to that step. All other signals are inactive.
➢ Hence, in step 1, the output of register R1 and the input of register Y are enabled,
causing the contents of R1 to be transferred over the bus to Y.
➢In step 2, the multiplexer's Select signal is set to SelectY, causing the multiplexer to
gate the contents of register Y to input A of the ALU. At the same time, the contents of
register R2 are gated onto the bus and, hence, to input B.
➢ The function performed by the ALU depends on the signals applied to its
control lines. In this case, the Add line is set to 1, causing the output of the ALU
to be the sum of the two numbers at inputs A and B.
➢This sum is loaded into register Z because its input control signal is activated.
➢ In step 3, the contents of register Z are transferred to the destination register,
R3. This last transfer cannot be carried out during step 2, because only one
register output can be connected to the bus during any clock cycle.
3. FETCHING A WORD FROM MEMORY
➢ To fetch a word of information from memory, the processor has to specify the
address of the memory location where this information is stored and request a Read
operation.
➢ This applies whether the information to be fetched represents an instruction in
a program or an operand specified by an instruction.
➢The processor transfers the required address to the MAR, whose output is connected to
the address lines of the memory bus. At the same time the processor uses the control
lines of the memory bus to indicate that a Read operation is needed.
➢When the requested data are received from the memory they are stored in register
MDR, from where they can be transferred to other registers in the processor.
➢The connections for register MDR are illustrated in Figure 1.4. It has
four control signals: MDR in, and MDR out control the connection to the
internal bus, and MDR inE and MDR outE control the connection to the
external bus.
➢The circuit in Figure 1.3 is easily modified to provide the additional
connections.
➢ A three-input multiplexer can be used, with the memory bus data line
connected to the third input. This input is selected when MDR inE =1.
➢ A second tri-state gate, controlled by MDR outE can be used to connect
the output of the flip-flop to the memory bus.
➢During memory Read and Write operations, the timing of internal
processor operations must be coordinated with the response of the
addressed device on the memory bus.
➢ The processor completes one internal data transfer in one clock
cycle. The speed of operation of the addressed device, on the other
hand, varies with the device.
➢ Typically, a cache will respond to a memory read request in one clock
cycle. However, when a cache miss occurs, the request is forwarded to
the main memory, which introduces a delay of several clock cycles.
➢ To accommodate the variability in response time, the processor
waits until it receives an indication that the requested Read
operation has been completed. A control signal called Memory-
Function-Completed (MFC) is used for this purpose.
➢ The addressed device sets this signal to 1 to indicate that the contents
of the specified location have been read and are available on the data
lines of the memory bus.
•Example: Read Operation
Consider the instruction Move (R 1 ),R2. The actions needed to execute this
instruction are:
[Link] ← [R1]
[Link] a Read operation on the memory bus
[Link] for the MFC response from the memory
[Link] MDR from the memory bus
5.R2 ← [MDR]
➢ These actions may be carried out as separate steps, but some can be combined into a
single step. Each action can be completed in one clock cycle, except action 3which
requires one or more clock cycles, depending on the speed of the addressed device.
➢ For simplicity, let us assume that the output of MAR is enabled all the time. Thus, the
contents of MAR are always available on the address lines of the memory bus. This is
the case when the processor is the bus master.
➢ When a new address is loaded into MAR, it will appear on the memory bus at the
beginning of the next clock cycle, as shown in Figure 1.5.
➢ A Read control signal is activated at the same time MAR is loaded. This signal will cause
the bus interface circuit to send a read command, MR, on the bus.
➢ With this arrangement, we have combined actions 1 and 2 above into a single control
step.
➢Actions 3 and 4 can also be combined by activating control signal MDRinE
while waiting for a response from the memory. Thus, the data received from
the memory are loaded into MDR at the end of the clock cycle in which the
MFC signal is received.
➢ In the next clock cycle, MDRout is activated to transfer the data to register
R2. This means that the memory read operation requires three steps, which
can be described by the signals being activated as follows:
1.R1out , MARin, Read
[Link], WMFC
[Link], R2in
•where WMFC is the control signal that causes the processor's control
circuitry to wait for the arrival of the MFC signal.
Figure 1.5. Timing of a memory Read operation
4. STORING A WORD IN MEMORY
➢Writing a word into a memory location follows a similar procedure.
➢ The desired address is loaded into MAR. Then, the data to be written are
loaded into MDR, and a Write command is issued.
• Hence, executing the instruction Move R2,(R 1) requires the following
sequence:
➢R1out, MARin
➢R2out, MDRin, Write
➢MDRoutE, WMFC
➢ As in the case of the read operation, the Write control signal causes the
memory bus interface hardware to issue a Write command on the memory
bus.
➢The processor remains in step 3 until the memory operation is completed
and an MFC response is received
2. EXECUTION OF A COMPLETE INSTRUCTION
•Let us now put together the sequence of elementary operations required to
execute one instruction. Consider the instruction
• Add (R3), R1
• which adds the contents of a memory location pointed to by R3 to register R1.
Executing this instruction requires the following actions: . . . .
[Link] the instruction,
[Link] the first operand (the contents of the memory location pointed to by
R3).
[Link] the addition.
[Link] the result into R1.
➢Figure 1.6 gives the sequence of control steps required to perform these
operations for the single-bus architecture of Figure 1.1.
Figure 1 6. Control Sequence for execution of the instruction Add [R3], R1
Instruction execution proceeds as follows.
• Step1--> The instruction-fetch operation is initiated by → loading
contents of PC into MAR & → sending a Read request to memory.
• The Select signal is set to Select4, which causes the Mux to select
constant 4.
• This value is added to operand at input B (PC‟s content), and the
result is stored in Z.
• Step2--> Updated value in Z is moved to PC. This completes the PC
increment operation and PC will now point to next instruction.
• Step3--> Fetched instruction is moved into MDR and then to IR. The
step 1 through 3 constitutes the Fetch Phase.
➢At the beginning of step 4, the instruction decoder interprets the contents of the
IR.
➢This enables the control circuitry to activate the control-signals for steps 4
through 7. The step 4 through 7 constitutes the Execution Phase.
➢ Step4--> Contents of R3 are loaded into MAR & a memory read signal is issued.
➢ Step5--> Contents of R1 are transferred to Y to prepare for addition.
➢Step6--> When Read operation is completed, memory-operand is available in
MDR, and the addition is performed.
➢ Step7--> Sum is stored in Z, then transferred to [Link] End signal causes a new
instruction fetch cycle to begin by returning to step1.
• This discussion accounts for all control signals in Figure 1.6
except Yin in step 2.
• There is no need to copy the updated contents of PC into
register Y when executing the Add instruction.
➢But in Branch instructions the updated value of the PC is needed
to compute the Branch target address. To speed up the execution
of Branch instructions, this value is copied into register Y in step
2.
➢ Since step 2 is part of the fetch phase, the same action will
be performed for all instructions. This does not cause any harm
because register Y is not used for any other purpose at that time.
1. Branch Instructions
•A branch instruction replaces the contents of the PC with the
branch target address. This address is usually obtained by adding an
offset X, which is given in the branch instruction, to the updated
value of the PC.
•UNCONDITIONAL BRANCHING
➢Figure 1. 7 gives a control sequence that implements an
unconditional branch instruction
Figure 1.7. Control Sequence for an unconditional
Branch instruction.
➢ Processing starts, as usual, with the fetch phase. This phase ends when the
instruction is loaded into the IR In step 3.
➢ The offset value is extracted from the IR by the instruction decoding circuit,
which will also perform sign extension if required.
➢Since the value of the updated PC is already available in register Y, the offset
X is gated onto the bus in step 4, and an addition operation is performed.
➢The result, which is the branch target address, is loaded into the PC in step 5.
➢ The offset X used in a branch instruction is usually the difference between
the branch target address and the address immediately following the branch
instruction.
•EXAMPLE:
➢ If the branch instruction is at location 2000 and if the branch
target address is 2050, the value of X must be 46.
➢ The PC is incremented during the fetch phase, before knowing
the type of instruction being executed.
➢ Thus, when the branch instruction is computed in step 4, the PC
value used is the updated value, which points to the instruction
following the branch instruction in the memory.
•CONDITIONAL BRANCHING
•In this case we need to check the status of the condition codes before loading
a new value into the PC.
•EXAMPLE:
•For Branch–on-negative (Branch <0) instruction, step 4 is replaced with
• Offset-field-of-IR , Add, Z
out in, If N = 0 then End
•Thus, if N = 0 the processor returns to step 1 immediately after step 4. If
N=1, step 5 is performed to load a new value into the PC, Thus performing the
branch operation. (N-Negative flag)
1.3 MULTIPLE BUS ORGANIZATION
•In simple single-bus structure of Figure 1.1 only one data item can be transferred over the bus
in a clock cycle. To reduce the number of steps needed, most commercial processors provide
multiple internal paths that enable several transfers to take place in parallel.
➢ Figure 1.8 depicts a three-bus structure used to connect the registers and the ALU of a
processor.
➢ All general-purpose registers are combined into a single block called the register file.
➢ The register file in Figure 1.8 is said to have three ports. There are two outputs, allowing
the contents of two different registers to be accessed simultaneously and have their contents
placed on buses A and B.
➢ The third port allows the data on bus C to be loaded into a third register during the same
clock cycle.
Figure 1.8. Three-bus Organization of the datapath
➢ Buses A and B are used to transfer the source operands to the A
and B inputs of the ALU, where an arithmetic or logic operation may
be performed.
➢ The result is transferred to the destination over bus C. If needed,
the ALU may simply pass one of its two input operands unmodified
to bus C.
➢We will call the ALU control signals for such an operation R=A or
R=B.
➢ A second feature in Figure 1.8 is the introduction of the
Incrementer unit, which is used to increment the PC by 4. Using the
Incrementer eliminates the need to add 4 to the PC using the main
ALU.
➢ The source for the constant 4 at the ALU input multiplexer is still
useful. It can be used to increment other addresses such as the
memory addresses in LoadMultiple and StoreMultiple
instructions.
•EXAMPLE:
• Consider the three-operand instruction
• Add R4, R5, R6
•The control sequence for executing this instruction is given in
Figure 1.9
Fig1.9 Control Sequence for Add R4, R5, R6
➢ In step 1 the contents of the PC are passed through the ALU, using the
R=B control signal, and loaded into the MAR to start a memory read
operation.
➢ At the same time the PC is incremented by 4. Note that the value loaded
into MAR is the original contents of the PC. The incremented value is loaded
into the PC at the end of the clock cycle and will not affect the contents of
MAR.
➢ In step 2, the processor waits for MFC and loads the data received into
MDR, then transfers them to IR in step 3.
➢Finally, the execution phase of the instruction requires only one control step
to complete,step 4.
➢ By providing more paths for data transfer a significant reduction in the
number of clock cycles needed to execute an instruction is achieved.
•1.4 HARDWIRED CONTROL
•To execute instructions, the processor must have some means of
generating the control signals needed in the proper sequence.
Computer designers use a wide variety of techniques to solve this
problem. The approaches used fall into one of two categories:
✓Hardwired control
✓Microprogrammed control.
•HARDWIRED CONTROL
➢ Consider the sequence of control signals given in Figure 1.6. Each step in
this sequence is completed in one clock period.
➢ A counter may be used to keep track of the control steps, as shown in
Figure 1.10. Each state, or count, of this counter corresponds to one control
step. The required control signals are determined by the following
information:
✓Contents of the control step counter
✓Contents of the instruction register
✓Contents of the condition code flags
✓External input signals, such as MFC and interrupt requests
Figure 1.10. Control Unit Organization
✓To gain insight into the structure of the control unit, we start with a
simplified view of the hardware involved.
✓ The decoder/encoder block in Figure 1.10 is a combinational
circuit that generates the required control outputs; depending on
the state of all its inputs.
✓ By separating the decoding and encoding functions, we obtain
the more detailed block diagram in Figure 1.11.
Figure 1.11. Separation of the decoding
and encoding functions
•DECODER/ ENCODER DESIGN
➢ The step decoder provides a separate signal line for each step, or time
slot, in the control sequence.
➢ Similarly, the output of the instruction decoder consists of a separate
line for each machine instruction.
➢ For any instruction loaded in the IR, one of the output lines INS1
through INSn is set to 1, and all other lines are set to 0.
➢ The input signals to the encoder block in Figure 1.11 are combined
to generate the individual control signals Yin, PCout, Add, End, and
so on.
• EXAMPLE1
➢ An example of how the encoder generates the Zin control signal for the
processor organization in Figure 1.1 is given in Figure 1.12. This circuit
implements the logic function
• Zin = T1 +T6 .ADD + T4 . BR + ∙ ∙ ∙ [EQUATION 1.1]
•This signal is asserted during time slot T1 for all instructions, during
T6 for an Add instruction, during T4 for an unconditional branch instruction,
and so on.
The logic function for Zin is derived from the control sequences in Figures
1.6 and 1.7.
in control signal for
Figure 1.12. Generation of the Z
the processor in Figure 1.1
EXAMPLE2
As another example, Figure 1.13 gives a circuit that generates the End control signal from the logic function
End = T7 ∙ ADD +T5 ∙ BR + (T5 ∙ N + T4 ∙ N’) ∙ BRN + ∙ … …
Figure 1.13. Generation of the End control signal
•END SIGNAL
The End signal starts a new instruction fetch cycle by resetting the control
step counter to its starting value.
•RUN SIGNAL
➢ Figure 1.11 contains another control signal called RUN. When set to 1, RUN
causes the counter to be incremented by one at the end of every clock cycle.
➢ When RUN is equal to 0, the counter stops counting. This is needed whenever
the WMFC signal is issued, to cause the processor to wait for the reply from the
memory. .
➢ The control hardware shown in Figure 1.10 or 1.11 can be viewed as a
state machine that changes from one state to another in every clock cycle,
depending on the contents of the instruction register, the condition codes,
and the external inputs.
➢ The outputs of the state machine are the control signals. The sequence
of operations carried out by this machine is determined by the wiring of
the logic elements, hence the name "hardwired."
➢ A controller that uses this approach can operate at high speed.
However, it has little flexibility, and the complexity of the instruction set it
can implement is limited.
COMPLETE PROCESSOR
• This has separate processing-units to deal with integer data and floating-point data.
• Integer Unit -To process integer data.
• Floating Unit -To process floating –point data.
• Data-Cache is inserted between these processing-units & main-memory. The integer and
floating unit gets data from data cache.
• Instruction-Unit fetches instructions → from an instruction-cache or → from main-
memory when desired instructions are not already in cache.
• Processor is connected to system-bus & hence to the rest of the computer by means of a
Bus Interface.
• Using separate caches for instructions & data is common practice in many processors
today.
• A processor may include several units of each type to increase the potential for
concurrent operations.
• The 80486 processor has 8-kbytes single cache for both instruction and data. Whereas
the Pentium processor has two separate 8 kbytes caches for instruction and data.
MICROPROGRAMMED CONTROL
• Microprogramming is a method of control unit design
• Control-signals are generated by a program similar to machine language
programs.
• Control Word(CW) is a word whose individual bits represent various
control-signals (like Add, PCin).
• Each of the control-steps in control sequence of an instruction defines a
unique combination of 1s & 0s in CW.
• Individual control-words in microroutine are referred to as
microinstructions .
• A sequence of CWs corresponding to control-sequence of a machine
instruction constitutes the microroutine.
• The microroutines for all instructions in the instruction-set of a computer
are stored in a special memory called the Control Store (CS).
• Control-unit generates control-signals for any instruction by
sequentially reading CWs of corresponding microroutine from CS.
• µPC(Microprogram Counter) is used to read CWs sequentially from
CS.
• Every time new instruction is loaded into IR, o/p of Starting Address
Generator is loaded into µPC.
• Then, µPC is automatically incremented by clock; causing successive
microinstructions to be read from CS. Hence, control-signals are
delivered to various parts of processor in correct sequence
[Link] of the microprogrammed control unit