MICROPROGRAMMED CONTROL
• Control Memory
• Sequencing Microinstructions
• Microprogram Example
• Design of Control Unit
• Microinstruction Format
TERMINOLOGY
1. Control Word:
- The control variables at any given time can be represented by a
string of 1’s and 0’s called control world.
2. Microinstruction
- Each word in the control memory contains within it a
microinstruction.
- It will specifies one or more micro operations.
- Vocabulary to write a micro program
3. Micro program
- Program stored in memory that generates all the control signals required
to execute the instruction set correctly
- Consists of microinstructions
4. Control Memory(Control Storage: CS)
- Storage in the micro programmed control unit to store the microprogram
TERMINOLOGY
5. Sequencer (Microprogram Sequencer)
- A Microprogram Control Unit that determines the microinstruction
address to be executed in the next clock cycle.
- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping
MICROPROGRAMMD CONTROL ORGANIZATION
MICROPROGRAMMD CONTROL ORGANIZATION
External input
Next Control
Address Control Control Control word
Generator address Memory data
(sequencer) register (ROM) register
Next-address information
Sequencing
MICROINSTRUCTION SEQUENCING
Instruction code
Mapping
logic
Status Branch MUX Multiplexers
bits logic select
Subroutine
register
Control address register (SBR)
(CAR)
Incrementer
Control memory (ROM)
select a status
bit
Microoperations
Branch address
Sequencing Capabilities Required in a Control Storage
- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return
Sequencing
MAPPING OF INSTRUCTIONS TO MICROROUTINES
Mapping from the OP-code of an instruction to the
address of the Microinstruction which is the starting
microinstruction of its execution microprogram
Machine OP-code
Instruction 1 0 1 1 Address
Mapping bits 0 x x x x 0 0
Microinstruction
address 0 1 0 1 1 0 0
Mapping function implemented by ROM
OP-code
Mapping memory
(ROM)
Control address register
Control Memory
Microprogram
COMPUTER-HARDWAR CONFIGURATION
Computer Configuration
MUX
10 0
AR
Address Memory
10 0 2048 x 16
PC
MUX
15 0
6 0 6 0 DR
SBR CAR
Control memory Arithmetic
128 x 20 logic and
shift unit
Control unit
15 0
AC
Microprogram
MACHINE INSTRUCTION FORMAT
Machine instruction format(16bit)
15 14 11 10 0
I Opcode Address
Sample machine instructions
Symbol OP-code Description
EA is the effective address
ADD 0000 AC AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC EA)
STORE 0010 M[EA] AC
EXCHANGE 0011 AC M[EA], M[EA]
AC
Microinstruction Format (20 bit)
3 3 3 2 2 7
F1 F2 F3 CD BR AD
F1, F2, F3: Microoperation fields
CD: Condition for branching
BR: Branch field
AD: Address field
Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3
F1 Microoperation Symbol F2 Microoperation Symbol
000 None NOP 000 None NOP
001 AC AC + DR ADD 001 AC AC - DR SUB
010 AC 0 CLRAC 010 AC AC DR OR
011 AC AC + 1 INCAC 011 AC AC DR AND
100 AC DR DRTAC 100 DR M[AR] READ
101 AR DR(0-10) DRTAR 101 DR AC ACTDR
110 AR PC PCTAR 110 DR DR + 1 INCDR
111 M[AR] DR WRITE 111 DR(0-10) PC PCTDR
F3 Microoperation Symbol
000 None NOP
001 AC AC DR XOR
010 AC AC’ COM
011 AC shl AC SHL
100 AC shr AC SHR
101 PC PC + 1 INCPC
110 PC AR ARTPC
111 Reserved
Microprogram
MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR
CD Condition Symbol Comments
00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC
BR Symbol Function
00 JMP CAR AD if condition = 1
CAR CAR + 1 if condition = 0
01 CALL CAR AD, SBR CAR + 1 if condition = 1
CAR CAR + 1 if condition = 0
10 RET CAR SBR (Return from subroutine)
11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0
Microprogram
SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent
by a microprogram assembler.
Sample Format
five fields: label; micro-ops; CD; BR; AD
1. Label: May be empty or may specify a symbolic address
terminated with a colon
2. Micro-ops: Consists of one, two, or three symbols separated by
commas
3. CD: One of {U, I, S, Z}, where U: Unconditional Branch
I: Indirect address bit
S: Sign of AC
Z: Zero value in AC
4. BR: One of {JMP, CALL, RET, MAP}
5. AD: One of {Symbolic address, NEXT, empty}
Microprogram
SYMBOLIC MICROPROGRAM - FETCH ROUTINE
During FETCH, Read an instruction from memory
and decode the instruction and update PC
Sequence of microoperations in the fetch cycle:
AR PC
DR M[AR], PC PC + 1
AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0
Symbolic microprogram for the fetch cycle:
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
Binary equivalents translated by an assembler
Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000
Microprogram
SYMBOLIC MICROPROGRAM
• Control Storage: 128 20-bit words
• The first 64 words: Routines for the 16 machine instructions
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60
Partial Symbolic Microprogram
Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH
ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH
ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH
ORG 12
EXCHANGE: NOP I CALL INDRCT
READ U JMP NEXT
ACTDR, DRTAC U JMP NEXT
WRITE U JMP FETCH
ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP
INDRCT: READ U JMP NEXT
DRTAR U RET
Microprogram
BINARY MICROPROGRAM
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR
AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00
1000000
3 0000011 000 000 000 00 00
1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00
1000000
11 0001011 000 000 000 00 00
1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00
0001110
14 0001110 100 101 000 00 00
0001111
15 0001111 111 000 000 00 00
1000000
This FETCH
microprogram64can1000000
be implemented
110
using 000
000
ROM 00 00 1000001
65 1000001 000 100 101 00 00
1000010
66 1000010 101 000 000 00 11
Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION -
microoperation fields
F1 F2 F3
3 x 8 decoder 3 x 8 decoder 3 x 8 decoder
7 6 54 3 21 0 7 6 54 3 21 0 76 54 3 21 0
AND
ADD AC
Arithmetic
logic and DR
DRTAC shift unit
PCTAR
DRTAR
From From
PC DR(0-10) Load
AC
Select 0 1
Multiplexers
Load Clock
AR
Design of Control Unit
MICROPROGRAM SEQUENCER
- NEXT MICROINSTRUCTION ADDRESS LOGIC -
Branch, CALL Address
External RETURN form Subroutine
(MAP)
In-Line
S1 S0 Address Source
00 CAR + 1, In-Line 3 2 1 0
S1 MUX1 L
01 CS(AD), Branch or CALL SBR Subroutine
S0 CALL
10 SBR RETURN Address
11 MAP source
selection
Incrementer
Clock CAR
Control Storage
MUX-1 selects an address from one of four sources and routes it into a CAR
- In-Line Sequencing CAR + 1
- Branch, Subroutine Call CS(AD)
- Return from Subroutine Output of SBR
- New Machine instruction MAP
Design of Control Unit
MICROPROGRAM SEQUENCER
External
(MAP)
L
I0 3 2 1 0
Input Load
I1 logic S1 MUX1 SBR
T S0
1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR
Control memory
Microops CD BR AD
... ...
Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -
1 L L(load SBR with CAR)
From I MUX2 Test
CPU S T for subroutine Call
BR field Input
Z Select I0 logic
of CS S0 for next address
I1
S1 selection
CD Field of CS
Input Logic
BR Field I 1I 0 T Meaning Source of Address S 1 S0 L
00 00 0 In-Line CAR+1 00 0
00 00 1 JMP CS(AD) 01 0
01 01 0 In-Line CAR+1 00 0
01 01 1 CALL CS(AD) and SBR <- CAR+1 01 1
10 10 x RET SBR 10 0
11 11 x MAP DR(11-14) 11 0
S1 = I 1
S0 = I1I0 + I1’T
L = I1’I0T
Definition
• Control Word
– The Control variables at any given time can be represented by string of 1’s
and 0’s called Control Word
• Microprogrammed Control Unit
– A control unit whose binary control variables are stored in memory is called
microprogrammed control unit.
• Micro Instruction
– Microinstruction specifies one or more microoperation for system.
• Micro Program
– The sequence of micro instruction constitutes Microprogram.
• Control Memory
– A memory that is part of a control unit is referred as control memory.