UNIT-5 PART-1

PIPELINING AND VECTOR PROCESSING

CHAPTER-9

• Parallel Processing

• Pipelining

• Arithmetic Pipeline

• Instruction Pipeline

• RISC Pipeline

• Vector Processing

• Array Processors
 Parallel Processing

PARALLEL PROCESSING

Execution of Concurrent Events in the computing

process to achieve faster Computational Speed

Levels of Parallel Processing

- Job or Program level

- Task or Procedure level

- Inter-Instruction level

- Intra-Instruction level
 Parallel Processing

PARALLEL COMPUTERS
Architectural Classification

– Flynn's classification
» Based on the multiplicity of Instruction Streams and Data
Streams
» Instruction Stream
• Sequence of Instructions read from memory
» Data Stream
• Operations performed on the data in the processor

Number of Data Streams

Single Multiple

Number of Single SISD SIMD

Instruction
Streams Multiple MISD MIMD
 Multiple Processor Organization

• Single instruction, single data stream - SISD

• Single instruction, multiple data stream - SIMD
• Multiple instruction, single data stream - MISD
• Multiple instruction, multiple data stream- MIMD
Taxonomy of Parallel Processor
Architectures
Single Instruction, Single Data Stream
- SISD
• Single processor
• Single instruction stream
• Data stored in single memory
• Uni-processor
Parallel Organizations - SISD
 Single Instruction, Multiple Data
Stream - SIMD
• Single machine instruction
• Controls simultaneous execution
• Number of processing elements
• Each processing element has associated data memory
• Each instruction executed on different set of data by
different processors
• Vector and array processors
Parallel Organizations - SIMD
 Multiple Instruction, Single Data
Stream - MISD
• Sequence of data
• Transmitted to set of processors
• Each processor executes different instruction sequence
• Never been implemented
 Parallel Processing

MISD COMPUTER SYSTEMS

M CU P

M CU P
Memory
• •
• •
• •

M CU P Data stream

Instruction stream

Characteristics
- There is no computer at present that can be
classified as MISD
 Multiple Instruction, Multiple Data
• Stream-
- Multiple processing units MIMD
- Execution of multiple instructions on multiple data
• Types of MIMD computer systems
• - Shared memory multiprocessors
• - Message-passing multicomputers
Parallel Organizations - MIMD Shared
Memory
Parallel Organizations - MIMD
Distributed Memory
 Parallel Processing

SHARED MEMORY MULTIPROCESSORS

M M ••• M

Buses,
Interconnection Network(IN) Multistage IN,
Crossbar Switch

P P ••• P

Characteristics
All processors have equally direct access to
one large memory address space
 Parallel Processing

MESSAGE-PASSING MULTICOMPUTER
Message-Passing Network Point-to-point connections

P P ••• P

M M ••• M

Characteristics
- Interconnected computers
- Each processor has its own memory, and
communicate via message-passing
 Pipelining

PIPELINING
A technique of decomposing a sequential process
into suboperations, with each subprocess being
executed in a partial dedicated segment that
operates concurrently with all other segments.
Ai * B i + C i for i = 1, 2, 3, ... , 7
Ai Bi Memory Ci
Segment 1
R1 R2

Multiplier
Segment 2

R3 R4

Adder
Segment 3

R5

R1  Ai, R2  Bi Load Ai and Bi

R3  R1 * R2, R4  Ci Multiply and load Ci
R5  R3 + R4 Add
 Pipelining

OPERATIONS IN EACH PIPELINE STAGE

Clock Segment 1 Segment 2 Segment 3

Pulse
Number R1 R2 R3 R4 R5
1 A1 B1
2 A2 B2 A1 * B1 C1
3 A3 B3 A2 * B2 C2 A1 * B1 + C1
4 A4 B4 A3 * B3 C3 A2 * B2 + C2
5 A5 B5 A4 * B4 C4 A3 * B3 + C3
6 A6 B6 A5 * B5 C5 A4 * B4 + C4
7 A7 B7 A6 * B6 C6 A5 * B5 + C5
8 A7 * B7 C7 A6 * B6 + C6
9 A7 * B7 + C7
 Pipelining

GENERAL PIPELINE
General Structure of a 4-Segment Pipeline
Clock

Input S1 R1 S2 R2 S3 R3 S4 R4

Space-Time Diagram
1 2 3 4 5 6 7 8 9 Clock cycles
Segment 1 T1 T2 T3 T4 T5 T6
2 T1 T2 T3 T4 T5 T6
3 T1 T2 T3 T4 T5 T6
4 T1 T2 T3 T4 T5 T6
 Pipelining

PIPELINE SPEEDUP
n: Number of tasks to be performed

Conventional Machine (Non-Pipelined)

tn: Clock cycle
: Time required to complete the n tasks
 = n * t n

Pipelined Machine (k stages)

tp: Clock cycle (time to complete each suboperation)
: Time required to complete the n tasks
 = (k + n - 1) * tp

Speedup
Sk: Speedup

Sk = n*tn / (k + n - 1)*tp
tn
= ( = k, if tn = k * tp )
tp
 Pipelining

PIPELINE
Example
- 4-stage pipeline
- subopertion in each stage; tp = 20nS
- 100 tasks to be executed
- 1 task in non-pipelined system; 20*4 = 80nS

Pipelined System
(k + n - 1)*tp = (4 + 99) * 20 = 2060nS

Non-Pipelined System
n*k*tp = 100 * 80 = 8000nS

Speedup
Sk = 8000 / 2060 = 3.88

4-Stage Pipeline is basically identical to the system

with 4 identical function units
TWO TYPES OF PIPE LINE:

Arithmetic Pipeline

Instruction Pipeline


An arithmetic pipeline divides an arithmetic operation into sub operations
for execution in the pipeline segments.


An instruction pipeline operates on a stream of instructions by overlapping
the fetch, decode, and execute phases of the instruction cycle.
 Arithmetic Pipeline

ARITHMETIC PIPELINE
Floating-point adder Exponents Mantissas
a b A B
X = A x 2a
Y = B x 2b R R

[1] Compare the exponents Compare Difference

Segment 1: exponents
[2] Align the mantissa by subtraction
[3] Add/sub the mantissa
[4] Normalize the result R

Segment 2: Choose exponent Align mantissa

Segment 3: Add or subtract

mantissas

R R

Segment 4: Adjust Normalize

exponent result

R R
 Instruction Pipeline

INSTRUCTION CYCLE
Six Phases* in an Instruction Cycle
[1] Fetch an instruction from memory
[2] Decode the instruction
[3] Calculate the effective address of the operand
[4] Fetch the operands from memory
[5] Execute the operation
[6] Store the result in the proper place

* Some instructions skip some phases

* Effective address calculation can be done in
the part of the decoding phase
* Storage of the operation result into a register
is done automatically in the execution phase

==> 4-Stage Pipeline

[1] FI: Fetch an instruction from memory

[2] DA: Decode the instruction and calculate
the effective address of the operand
[3] FO: Fetch the operand
[4] EX: Execute the operation
 Instruction Pipeline

INSTRUCTION PIPELINE

Execution of Three Instructions in a 4-Stage Pipeline

Conventional

i FI DA FO EX

i+1 FI DA FO EX

i+2 FI DA FO EX

Pipelined

i FI DA FO EX
i+1 FI DA FO EX
i+2 FI DA FO EX
 Instruction Pipeline

INSTRUCTION EXECUTION IN A 4-STAGE PIPELINE

Segment1: Fetch instruction

from memory

Decode instruction
Segment2: and calculate
effective address

yes Branch?
no
Fetch operand
Segment3: from memory

Segment4: Execute instruction

Interrupt yes
Interrupt?
handling
no
Update PC

Empty pipe
Step: 1 2 3 4 5 6 7 8 9 10 11 12 13
Instruction 1 FI DA FO EX
2 FI DA FO EX
(Branch) 3 FI DA FO EX
4 FI FI DA FO EX
5 FI DA FO EX
6 FI DA FO EX
7 FI DA FO EX
 Instruction Pipeline
PIPELINE CONFLICTS:

MAJOR HAZARDS IN PIPELINED EXECUTION

Structural hazards(Resource Conflicts) :
Resource conflicts caused by access to memory by two segments at the
same time. Most of these conflicts can be resolved by using separate
Instruction and data memories.
Data hazards (Data Dependency Conflicts) :
Data Dependency conflicts arise when an instruction depends on the
Result of a previous instruction, but this result is not yet available.
ADD R1,B,C ;R1<-- B+C
INC R1 ;R1<--R1+1

Control hazards (Branch Difficulties)

Branch difficulties arise from branch and other instructions that
change the value of PC
 Instruction Pipeline

STRUCTURAL HAZARDS
Structural Hazards

Occur when some resource has not been

duplicated enough to allow all combinations
of instructions in the pipeline to execute

Example: With one memory-port, a data and an instruction fetch

cannot be initiated in the same clock
i FI DA FO EX

i+1 FI DA FO EX

i+2 stall stall FI DA FO EX

The Pipeline is stalled for a structural hazard

<- Two Loads with one port memory
-> Two-port memory will serve without stall
 Instruction Pipeline

DATA HAZARDS
Data Hazards

Occurs when the execution of an instruction

depends on the results of a previous instruction
ADD R1, R2, R3
SUB R4, R1, R5
Data hazard can be dealt with either hardware
techniques or software technique
Hardware Technique

Interlock
- hardware detects the data dependencies and delays the scheduling
of the dependent instruction by stalling enough clock cycles
Forwarding (bypassing, short-circuiting)
- Accomplished by a data path that routes a value from a source
(usually an ALU) to a user, bypassing a designated register. This
allows the value to be produced to be used at an earlier stage in the
pipeline than would otherwise be possible

Software Technique
Instruction Scheduling(compiler) for delayed load
 Instruction Pipeline

CONTROL HAZARDS
Branch Instructions

- Branch target address is not known until

the branch instruction is completed
Branch
FI DA FO EX
Instruction
Next FI DA FO EX
Instruction

Target address available

- Stall -> waste of cycle times

Dealing with Control Hazards

* Prefetch Target Instruction

* Branch Target Buffer
* Loop Buffer
* Branch Prediction
* Delayed Branch
 Instruction Pipeline

CONTROL HAZARDS
Prefetch Target Instruction
– Fetch instructions in both streams, branch not taken and branch taken
– Both are saved until branch branch is executed. Then, select the right
instruction stream and discard the wrong stream
Branch Target Buffer(BTB; Associative Memory)
– Entry: Addr of previously executed branches; Target instruction
and the next few instructions
– When fetching an instruction, search BTB.
– If found, fetch the instruction stream in BTB;
– If not, new stream is fetched and update BTB
Loop Buffer(High Speed Register file)
– Storage of entire loop that allows to execute a loop without accessing
memory
Branch Prediction
– Guessing the branch condition, and fetch an instruction stream based on
the guess. Correct guess eliminates the branch penalty
Delayed Branch
– Compiler detects the branch and rearranges the instruction sequence
by inserting useful instructions that keep the pipeline busy
in the presence of a branch instruction
 RISC Pipeline

RISC PIPELINE
RISC
- Machine with a very fast clock cycle that
executes at the rate of one instruction per cycle
<- Simple Instruction Set
Fixed Length Instruction Format
Register-to-Register Operations
Instruction Cycles of Three-Stage Instruction Pipeline
Data Manipulation Instructions
I: Instruction Fetch
A: Decode, Read Registers, ALU Operations
E: Write a Register

Load and Store Instructions

I: Instruction Fetch
A: Decode, Evaluate Effective Address
E: Register-to-Memory or Memory-to-Register

Program Control Instructions

I: Instruction Fetch
A: Decode, Evaluate Branch Address
E: Write Register(PC)
 RISC Pipeline

DELAYED LOAD
LOAD: R1  M[address 1]
LOAD: R2  M[address 2]
ADD: R3  R1 + R2
STORE: M[address 3]  R3
Three-segment pipeline timing
Pipeline timing with data conflict

clock cycle 1 2 3 4 5 6
Load R1 I A E
Load R2 I A E
Add R1+R2 I A E
Store R3 I A E

Pipeline timing with delayed load

clock cycle 1 2 3 4 5 6 7 The data dependency is taken

Load R1 I A E care by the compiler rather
Load R2 I A E than the hardware
NOP I A E
Add R1+R2 I A E
Store R3 I A E
 RISC Pipeline

DELAYED BRANCH
Compiler analyzes the instructions before and after
the branch and rearranges the program sequence by
inserting useful instructions in the delay steps
Using no-operation instructions
Clock cycles: 1 2 3 4 5 6 7 8 9 10
1. Load I A E
2. Increment I A E
3. Add I A E
4. Subtract I A E
5. Branch to X I A E
6. NOP I A E
7. NOP I A E
8. Instr. in X I A E

Rearranging the instructions

C lock cycles: 1 2 3 4 5 6 7 8
1. Load I A E
2. Increment I A E
3. B ranch to X I A E
4. A dd I A E
5. Subtract I A E
6. Instr. in X I A E
 Vector Processing

VECTOR PROCESSING
Vector Processing Applications
• Problems that can be efficiently formulated in terms of vectors
– Long-range weather forecasting
– Petroleum explorations
– Seismic data analysis
– Medical diagnosis
– Aerodynamics and space flight simulations
– Artificial intelligence and expert systems
– Mapping the human genome
– Image processing

Vector Processor (computer)

Ability to process vectors, and related data structures such as matrices
and multi-dimensional arrays, much faster than conventional computers

Vector Processors may also be pipelined

 Vector Processing

VECTOR PROGRAMMING

DO 20 I = 1, 100
20 C(I) = B(I) + A(I)

Conventional computer
Initialize I = 0
20 Read A(I)
Read B(I)
Store C(I) = A(I) + B(I)
Increment I = i + 1
If I  100 goto 20

Vector computer

C(1:100) = A(1:100) + B(1:100)

 Vector Processing

MULTIPLE MEMORY MODULE AND INTERLEAVING

Multiple Module Memory

Address bus
M0 M1 M2 M3

AR AR AR AR

Memory Memory Memory Memory

array array array array

DR DR DR DR

Data bus

Address Interleaving

Different sets of addresses are assigned to

different memory modules
 ARRAY PROCESSORS

An array processor is a processor that performs computations on
large arrays of data.

Two types of array processors:

An Attached array processor is an auxiliary processor attached to a

general purpose computer.

An SIMD array processor is a processor has a single instruction multiple data

Organization.
Attached Array
Processor :
To improve the performance of the
host computer in numerical
computational tasks auxiliary
processor is attached to it.

[Link] output interface to a

common processor.
[Link] with a local memory.

Here local memory interconnects

main memory. Host computer is
general purpose computer. Attached
processor is back end machine
driven by the host computer.
The array processor is connected
through an I/O controller to the
computer & the computer treats it as
an external interface.
SIMD array processor :
This is computer with multiple process unit operating in
parallel Both types of array processors, manipulate
vectors but their internal organization is different.
SIMD is a computer with multiple processing units
operating in parallel.
The processing units are synchronized to perform the
same operation under the control of a common control
unit. Thus providing a single instruction stream,
multiple data stream (SIMD) organization. As shown in
figure, SIMD contains a set of identical processing
elements (PES) each having a local memory M.
Each PE includes –
•ALU
•Floating point arithmetic unit
•Working registers

Master control unit controls the operation in the PEs.

The function of master control unit is to decode the
instruction and determine how the instruction to be
executed. If the instruction is scalar or program control
instruction then it is directly executed within the master
control unit.
Main memory is used for storage of the program while
each PE uses operands stored in its local memory.