AY-2025-
2026
ODD SEM
Department of ECE
MIXED SIGNAL IC DESIGN
22VLS3505
Topic:
Submicron CMOS:CMOS Process
Flow
Session - 2
AIM OF THE SESSION
1. To provide an in-depth understanding of submicron CMOS technology, including device modeling, process flow, and its application
in digital and analog circuit design.
2. To enable students to apply CMOS principles in designing and analyzing both digital logic blocks and analog building blocks using
modern submicron processes.
INSTRUCTIONAL OBJECTIVES
This Session is designed to:
1. Explain the CMOS process flow and identify key fabrication steps including capacitor and resistor formation.
2. Describe how MOSFETs function as switches in digital circuits and analyze delay elements and adder circuits.
3. Illustrate analog design principles such as biasing, operational amplifier configuration, and key noise sources.
4. Relate the role of compact models and short-channel effects to performance in submicron CMOS technologies.
LEARNING OUTCOMES
At the end of this session, you should be able to:
1. Analyze and design basic digital and analog circuits using submicron CMOS models.
2. Interpret CMOS process flow diagrams and recognize how passive elements like capacitors and resistors are integrated on-
chip.
3. Evaluate the impact of process and device-level parameters on the performance and noise behavior of analog and digital
circuits.
Introduction to CMOS Process
CMOS = Complementary Metal Oxide
Semiconductor
Submicron refers to feature sizes < 1 µm
Process flow involves multiple steps to
create NMOS and PMOS on a single
wafer.
Importance: Determines performance, Fig: Schematic view of the CMOS process flow.
yield, cost.
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Starting Material – Silicon Wafer
High-purity single-crystal
silicon
Types:
p-type (doped with Boron)
n-type (doped with
Phosphorus)
Typical diameter: 200mm,
Fig: Silicon Wafer Process
300mm
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Oxidation
Thermal oxidation forms SiO₂ layer on Si
Acts as gate oxide or isolation
Dry oxidation (thin, high quality)
Wet oxidation (thicker, faster growth)
Fig: Semiconductor Wafer Thermal Oxidation Method
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Photolithography
Patterning technique using light and
masks
Coating
Aligning
Exposing
Developing photoresist
Positive vs Negative resists
Resolution limited by wavelength
Deep UV Fig: Photolithography process steps:
(A) coating of photoresist on the substrate, mask placed
EUV over upper layer and exposed to UV radiation,
(B) resist development and stripping
(C) ion etching process,
(D) final QD structure after process.
Etching
Removes layers not protected by
photoresist
Types:
Wet (chemical)
Dry (plasma, RIE)
Submicron tech uses anisotropic dry
etching for vertical profiles
Selectivity: Etch one layer without
damaging other
Fig: Anisotropic and isotropic plasma
etching
Doping – Ion Implantation
Introduce carriers (electrons/holes) by
implanting dopant ions
NMOS: Phosphorus/Arsenic
PMOS: Boron
Precise control of dose, depth, and
location
Followed by annealing to activate and
repair crystal damage
Fig: basic structure of an ion implanter
with magnetic analysis.
Gate Formation
Gate oxide: ultra-thin SiO₂ (~1-2 nm in
submicron)
Gate electrode: polysilicon (older) or metal
(modern)
Defines channel length (L) → critical in
submicron scaling
Modern nodes use High-k / Metal Gate
(HKMG) for leakage control
Fig: MOSFET
Structure
Spacer Formation and S/D Engineering
Spacer: Deposited sidewall layer (usually
Si₃N₄)
Forms after gate etch to protect gate side
LDD (Lightly Doped Drain) near channel
HDD (Heavily Doped Drain) after spacers
Reduces hot-carrier and SCE effects
Fig: submicron
MOSFET with sidewall
spacers:
Passivation, Dicing & Testing
Final passivation layer: protects IC from
environment
Wafer : diced into individual dies
Electrical testing: functional, parametric
Good dies are packaged into ICs (e.g., QFN, Fig: Wire Bonding Process in
BGA, DIP) Semiconductor industry
Conclusion and Future Trends
Submicron CMOS drives modern electronics
Key is balancing performance, power, and
area (PPA)
Future:
CFET (Complementary FET)
3D stacked transistors
AI-assisted chip design
Need for improved models and tools
Fig: Evolution of Transistors
THANK YOU
Team – LOW POWER VLSI DESIGN
Prepared by Dr. [Link]
Sravani
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