Asynchronous Jn Kn Qn+1 T Qn+1
Counters Qn
0 0 0 Qn T is J=K
0 1 0 1 Q'n
1 0 1
1 1 Q'n
• From the timing diagram, we can observe that Q0 changes
state only during the negative edge of the applied clock.
• Initially, the flip flop is at state 0.
• Flip-flop stays in the state until the applied clock goes
from 1 to 0. As the J and K values are 1, the flip flop
should toggle. So, it changes state from 0 to 1.
• The process continues for all pulses of the clock.
3-bit Asynchronous Counter
Counter State Clock QC QB QA
0 Initially 0 0 0
1 1st falling edge 0 0 1
2 2nd falling edge 0 1 0
3 3rd falling edge 0 1 1
4 4th falling edge 1 0 0
5 5th falling edge 1 0 1
6 6th falling edge 1 1 0
7 7th falling edge 1 1 1
8 8th falling edge 0 0 0
4-bit Asynchronous Counter
Asynchronous Decade Counter
Counter Clock Q4 Q3 Q2 Q1
State
0 Initially 0 0 0 0
1 1st falling 0 0 0 1
edge
2 2nd falling 0 0 1 0
edge
3 3rd falling 0 0 1 1
edge
4 4th falling 0 1 0 0
edge
5 5th falling 0 1 0 1 Q1
edge
6 6th falling 0 1 1 0
edge Q2
7 7th falling 0 1 1 1
edge Q3
8 8th falling 1 0 0 0
edge Q4
9 9th falling 1 0 0 1
edge
10 10th falling 0 0 0 0
edge