MODULE 4: CONTROL UNIT

1. Basic concepts,
• buses-bidirectional
• single bus organization
• 2 bus organization
• 3 bus organization,
2. Design methods: comparison of hardwired and micro-programmed approach
2.1 hardwired control design
• Booth’s multiplier design,
• processing section design of booths multiplier,
• Booth’s multiplier controller,
• Sequence controller design,
2.2 Microprogrammed control unit
• Micro-programmed control organization,
• Microprogrammed multiplier control unit for booths multiplier.
 Introduction

• A CPU can be viewed as a collection of two major components: Processing section and Control unit
• The processing section typically includes the hardware elements (ALU, shift registers, comparators, and
multipliers) to operate on data such as integer or real numbers. character codes, operation codes, and offset
values.
• The purpose of the control unit is to control system operations by routing the selected data items to the
selected processing hardware at the right time. A control unit responsibility is to drive the associated
processing hardware by generating a set of signals that are synchronized with a master clock. This
synchronization establishes a time- reference for system analysis and design.
• The signals generated by a control unit actually initiate an operation within the system. In order to carry out
a task such as ADD, the control unit must generate a set of control signals in a predefined sequence
governed by the hardware structure of the processing section. Sometimes, the control unit decides the
operation sequence based on the status information provided by the status register (for example, Z and N
condition codes) or the command signals generated by an external agent (such as RESET and ABORT
signals issued from the operator's console).
• The inputs to the control unit are the master clock, status information from the processing section,
and command signals from the external agent.
• The outputs produced by the typical control unit are the signals that drive the processing section and
responses to an external environment (operation complete and operation aborted) due to exceptions
(integer overflow or underflow).
• A control unit undertakes the following responsibilities: Instruction interpretation and Instruction
sequencing.
• In the interpretation phase, the control unit reads instructions from the memory (using the PC as a
pointer). It then recognizes the instruction type, gets the necessary operands, and routes them to the
appropriate functional units of the execution unit.
• In the sequencing phase, the control unit determines the address of the next instruction to be executed
and loads it into the PC.
 Basic concepts
• The fundamental concepts forming the basis for control unit
design are the register transfer operations and their analytical
descriptions.
• A digital processing system is a collection of registers where a
processing activity is performed by a sequence of data-
transfer operations among the registers either directly or with
processing hardware (ALU).
Example: 8 bits of information are to be moved from register A
to register B. This means transferring a copy of A to B.
 • The fundamental concepts forming the basis for control unit design are the register transfer operations
and their analytical descriptions. A digital processing system is a collection of registers where a
processing activity is performed by a sequence of data- transfer operations among the registers either
directly or with processing hardware (ALU).
Example:

• 8-bit info moved from Register A to Register B.

Such operation is described as BA
Declare registers A[8], B[8]
• Register can be defined as a portion of some other register. For example, if the higher order byte of 16-bit
PC is considered as one 8-bit register, the following declarations are made:
Declare registers PC[16]
Declare subregisters PCHI[8]= PC[15-8]
//"PCHI[8]" refers to the 8th bit of a register named "PCHI.“
//"PC[15-8]" refers to bits 8 through 15 of another register named "PC."
• Assigning individual bits: B[0]  A[7] means MSB of A is copied to LSB of B.
• Normally, the information transfer between two registers is controlled by an enable signal E,
• Generally, two inputs are associated with each register.

Enable input or control input

Data input
• The enable input controls the data flow from register A to B. The B
register loaded with the contents of the A register only when the
enable input E is held high; otherwise the contents of the register
remain the same. Such a conditional transfer can be expressed as

• The possible hardware implementation of a register with an

enable input is shown in the figure.
• The bit , in this figure is only loaded with bit , when the enable
input E is high.
• The purpose of the enable input is to make sure that data transfer
between the A and B registers takes place only under a
predetermined condition and not after every clock pulse. For this
reason, this input is called the control input and is driven by the
control unit.
• Sometimes, the control input may be a function of more than one variable. Consider the following
register transfer involving three 8-bit registers A, B, and D.
IF A > B and D [0] = 0 then AB
• The condition A>B can be determined by using an 8-bit comparator. If we assume that the comparator
output G goes high when A>B, then this conditional transfer can be described as follows:
: AB where = G ˄ D [0]’

Fig: Hardware implementation of : AB where = G ˄ D [0]’

• It may often be necessary to perform some register transfer
operation selection.
For example:
if x = 0 and t = 1 then A B
else AD
Where A, B, and D are 8-bit registers, such a selective register
transfer can be expressed as follows:
: AB
: AD Fig: Hardware implementation if x = 0
where = and = = x + . and t = 1 then A B else AD
• The MUX selects register B if = 1; otherwise register D is
selected.
• The mnemonics LSL, ASL, ROR (shifts each bit to the right), and ROL(shifts each bit to the left) are used to
indicate logical left shift, arithmetic left shift, rotate right and rotate left operations respectively.
• For this notation the $ symbol is used as the concatenation operator. For example, if A and Q are two 8-bit
registers and ASR (A$Q) is written, the contents of AQ are arithmetically shifted one position to the right.
• This operation is a 16-bit operation with high- and low-order bytes held in the A and Q registers,
respectively.
• Whenever a read/write memory (RWM) is a part of the processing section, the data transfers are described
with respect to the RWM unit.
• Each word in the RWM is considered as an addressable register, thus, the whole memory unit can be
viewed as a collection of such addressable registers.
• RWM unit are two registers:
 Memory address register (MAR): The MAR is used as a pointer to a memory word. It holds the
address of the desired memory word.
 Memory buffer register (MBR) : The purpose of the MBR is to act as a buffer register in all data
transfer operations.

• The general structure of a RWM is shown in figure.

Fig: A basic RWM Unit

• The two basic operations performed by the RWM unit are read and write operations, expressed in register transfer
notation as
 R: MBRM ((MAR))
 W: M ((MAR)) MBR
• The letter M is used to indicate a memory. M ((MAR)) indicates the memory word X addressed by the contents of the
MAR.
• In a typical read operation, the contents of the memory word, whose address is specified in MAR, are transferred into
the MBR.
• Similarly, a write operation refers to the data transfer from MBR to the memory word whose address is specified in
MAR.

• Bidirectional data bus : Since the data flows in

and out of MBR, the set of data lines or the data
bus between the RAM unit and MBR should be
bidirectional. Such a bidirectional data bus is
easily implemented using tristate buffers shown
in below figure.
• When C =1 in bidirectional data bus, data
transfer takes place from X to Y. and vice versa
when C= 0. Fig: Bidirectional data bus
• Buses are also used to route data in • Declare registers A [8], M [8], Q [8];
and out of a digital processing
system. For example, in a typical • Declare buses inbus [8], outbus [8];
digital system, there will be a pair
• Start: A  0, M  inbus ;
of buses ("inbus" and "out- bus") to // Transfer the multiplicand and clear accumulator
transfer data from the external
environment into the processing Q  inbus ; //Transfer the multiplier
section, and vice versa.
• By sequencing a set of register • Loop: A  A + M, Q  Q – 1;
transfer operations and including // Add multiplicand
typical control structures such as
if-then and go-to, an algorithm If Q < > 0 then go to Loop; //repeat if Q≠0
implemented by a digital system
Outbus = A;
can be described. Consider the
following description: • Halt: Go to Halt
• The hardware for the preceding description includes an 8-bit inbus, an 8-bit out- bus, an 8-bit parallel adder, and
three 8-bit registers-A. M, and Q. This hardware performs unsigned multiplication by repeated addition, much
like a program written using a combination of high-level and assembly languages.
• Therefore, a distinguishing feature of this description is the ability to concurrent operations. For example, the
operations A  0, and M  Inbus can be executed at the same time. As a general rule, a comma is inserted
between operations that can be executed simultaneously.
• Similarly, a semicolon between two register transfer operations dictates that they must be performed serially. This
restriction is primarily due to the data paths provided in the hardware. For example, in the description just
presented, there is only one input bus. The operations M  inbus and Q  inbus must be performed serially.
However, either one may be overlapped with the operation A  0, since the operation does not use the input bus.
• Operations such as A  O and A  A + M are called microoperations, since they are completed in one clock
cycle. In principle, any task can be expressed as a sequence of microoperations.
• The rate which a computer processes operation such as A  A + B, and A  A ˄ B is determined by its bus
structure. Similarly, bus organization determines the cost of the system. Therefore, a less-complex bus
organization is less expensive.
• Several types of bus structure within the CPU:
i) Single-bus oriented ALU
ii) Two-bus oriented ALU
iii) Three-bus oriented ALU
1. Single Bus Oriented RALU: The simplest of all bus structures is the single-bus organization. All CPU
registers are connected to the same bus. At any given time, data may be transferred between any two CPU
registers or between a CPU register and the ALU. Whenever the ALU requires the two operands (such as in the
case of addition), the operands can be transferred only one at a time.
• Single-bus architecture should have the following features:
 The bus must be multiplexed among various operands.
 The ALU must have buffer registers to hold the transferred operand.

• In figure (RALU =Register Arithmetic Logic

Unit), an operation such as R2  R0 + R1, is
completed in three clock cycles:
 In the first clock cycle, the contents of register
R0, are transferred to buffer register A of the
ALU.
 During the second clock cycle the contents of
register R1, are transferred to buffer register B
of the ALU.
 The sum produced by the ALU is loaded into
register R2, when the third clock pulse arrives.
• Single-bus organization reduces the speed of the addition operation when the
operands are already in the CPU registers. If the operands are in memory, two
clock cycles are required to retrieve the required operands. Therefore, this
organization affects the speed of execution of a typical two-operand memory-
reference instruction.
• To carry out a binary operation (such as addition), the control logic must follow a
three-step sequence. Each step represents a control state. Therefore, a single-bus
architecture increases the number of states in the control logic. More hardware
may be required to design the control unit. Since all data transfers take place
through the same bus, one at a time, the design effort required to build the control
logic is greatly reduced.
• A single-bus organization's speed of operation is not as high as that of a two-bus
organization.
2. Two Bus Oriented RALU: The architecture of a Two-bus oriented RALU is shown in below figure.
• All general-purpose registers are connected to both buses (bus A and bus B) to form a two-bus
organization.
• The two operands required by the ALU are, therefore, routed in one clock cycle.
• Instruction execution is faster, since the ALU does not wait for the second operand, as in the case with a
single-bus organization.
• The information flowing on a bus may be from a general-purpose register or a special-purpose register. In
this arrangement, the special-purpose registers are often divided into two groups. Each group is connected
to one of the buses. The data from two special-purpose registers of the same group cannot be transferred
to the ALU at the same time.
• The contents of the PC are always transferred to the right input of the ALU, since it is connected to bus
A. Similarly, the contents of the special-purpose register MBR are always transferred to the left input of
the ALU, since it is connected to bus B.
• Whenever there is a need to process simultaneously the contents of two special-purpose registers of the
same group, the contents of one of the registers must be transferred to one of the general-purpose
registers prior to processing.
• The initialization step requires the execution of an additional instruction.
• The output of the ALU may be routed to either a special-purpose or a general-purpose register.
• Since the ALU does not have any input buffer registers, both buses carry operands and are busy during
binary operations. Therefore, the output produced by the ALU will first be routed to the output register.
• Transfer of the required operands and loading of the ALU output buffer register takes place in one cycle.
The result held in the ALU output buffer register is then routed to the required destination in the second
clock cycle. The contents of the ALU output buffer register can be gated to either bus A or bus B.
• Besides the data paths there may be additional dedicated data paths between special-purpose registers.
For example, a dedicated data path is often provided between the MAR and PC because the register
transfer operation MAR  PC appears at the beginning of each instruction cycle.
• The performance of a two-bus organization can be further improved by adding a third bus, bus C. at the
output of the ALU. The resulting structure is known as a three- bus organization.
3. Three-bus-Oriented RALU: The architecture of a Three-bus oriented RALU is shown in below figure.
• From this figure notice that a three-bus structure is reduced to the two-bus structure if bus C is replaced with the ALU
output buffer register.
• The addition of bus C allows the system to perform all ALU operations, such as R2  R0 + R1, in one cycle, since
three separate data paths or buses are provided with the system. These data paths include routing for the two operands
and the result.
• A finite delay will occur due to the transferring of operands to the ALU and the time taken by the ALU for producing
the result. This delay must be taken care of when transferring the result to the third bus.
• The addition of the third bus will increase the system cost. The design of the control logic will be complicated
because of the critical time delays involved.
• Another important concept closely related to the control unit design is the generation of timing signals.
• One task of a control unit is properly to sequence a set of operations. Normally, a sequence of N
consecutive operations will occur in response to N consecutive clock pulses. To carry out an operation, P,
at the clock pulse, a control unit must count the clock pulses and produce a timing signal T1. T2, will
assume a value of 1 during the duration of the clock pulse. For example, the input clock pulse and the
four timing signals , , and . are shown in below figure.
• In the below figure, the timing signal , marks when the clock pulse has occurred and stays high until the
next pulse. The frequency of the signal is one-fourth the input clock pulse, since one clock period of
accommodates four clock periods of the input pulse.
• An easy way to generate this type of timing signals is by designing a ring counter shown below.

Timing signal: [Link]

Ring counter: [Link]
• This circuit is also known as a circular shift register,
since the least-significant bit shifted is not lost.
• The chief advantages of this circuit are design simplicity
and the ability to generate timing signals without a
decoder. Nevertheless, N flip-flops are required to
generate N timing signals. This approach is not
economically feasible for large values of N.
• To generate timing signals economically, a new approach
is used.
• A modulo- counter is first designed using N flip-flops.
The N outputs from this counter are then given to a N-to-
decoder as input to generate timing signals.
• The below circuit shows how to generate four timing
signals using a modulo-4 counter and a 2-to-4 decoder:

• In the preceding circuit, the Boolean equation for each timing signal can be derived as, To = A’B’, T₁ = A’B, T₂ = AB’,
and T3 = AB.
• These equations show that four 2-input AND gates are needed to derive the timing signals (assuming single-level
decoding). The main advantage of this approach is that timing signals using only n flip-flops are generated.
• In this method, (n- input) AND gates are required to decode the n-bit output from the flip-flops into different timing
signals. Yet the ring counter approach requires flip-flops to accomplish the same task.
 Design Methods [Link]

• Control units are designed in two different ways: Hardwired and Microprogramming approach
Hardwired Control Unit Microprogrammed Control Unit
Hardwired control unit generates the control signals Microprogrammed control unit generates the control
needed for the processor using logic circuits signals with the help of micro instructions stored in
control memory
Hardwired control unit is faster when compared to This is slower than the other as micro-instructions are
microprogrammed control unit as the required control used for generating signals here.
signals are generated with the help of hardwares
Difficult to modify as the control signals that need to be Easy to modify as the modification need to be done
generated are hard wired only at the instruction level
More costlier as everything has to be realized in terms Less costlier than hardwired control as only micro
of logic gates instructions are used for generating control signals

It cannot handle complex instructions as the circuit It can handle complex instructions
design for it becomes complex
Only limited number of instructions are used due to the Control signals for many instructions can be generated
hardware implementation
Used in computer that makes use of Reduced Used in computer that makes use of Complex
Instruction Set Computers(RISC) Instruction Set Computers(CISC)
1. Hardwired Control Design

The steps involved in this method:

2. Define the task to be performed.

3. Propose a trial processing section.
4. Provide a register-transfer description of the algorithm based on the processing section outlined in
the previous step.
5. Validate the algorithm by using trial data.
6. Describe the basic characteristics of the hardware elements to be used in the processing section.
7. Complete the design of the processing section by establishing necessary control points.
8. Propose a block diagram of the controller.
9. Specify the state diagram of the controller.
10. Specify the characteristics of the hardware elements to be used in the controller.
11. Complete the controller design and draw a logic diagram of the final circuit.

[Link]
Example: Hardwired Control Design

Step 1: Task Definition: Design a Booth's multiplier to multiply two 4-bit 2's complement numbers.

Step 2: Propose a trial processing section.

• The 4-bit register M will hold the multiplicand.
• The Q register is 5 bits wide. Initially, the high-order 4-bits of this
register will hold the 4-bit multiplier. The least-significant bit of this
register is initialized with the fictitious zero discussed in the previous
chapter.
• The 4-bit adder/subtracter is used to perform the operations A + M or A -
M. The result produced by this hardware is always routed to the 4-bit
accumulator register A.
• In this implementation the multiplicand is not shifted to the left; rather
the accumulated partial product is shifted right. When the computation
terminates, the high- and low-order 4 bits of the final product are found
in registers A and Q, respectively.
• The L register is used to keep track of the iteration count. In this
particular case, this register is initialized with () and is decremented by
1 at the completion of each iteration. Therefore, the algorithm terminates
when 000 is in the L register.
• The 4-bit data buses, inbus and outbus, are used to transfer data into and
out of the processing section, respectively.
Step 3: Register-transfer description of the algorithm based on the processing section outlined in the
previous step.
Step 4: Validate the algorithm by using trial data.
 Step 5: Describe the basic characteristics of the hardware elements to be used in the processing section.
• The processing section includes three main
components:
 General-purpose storage registers
 4-bit adder/subtractor
 Tristate buffers
• The functional characteristics of these parts are
summarized as shown in figure.
• Notice that the general register is basically a trailing-
edge-triggered device. Typically, four operations
(clear, parallel load, right shift, and decrement) can be
performed by introducing the proper values to control
inputs C, L, R, and D. All these operations are
synchronized with the trailing edge (high to low) of l +r
the clock pulse. l-r
• The 4-bit adder/subtractor is implemented by using a
4-bit parallel adder chip (7483) and four 2-input
exclusive-OR gates.
• The tristate buffers are used to control the data transfer
to the outbus.
Note: The 7483 chip performs binary addition of the two 4-bit inputs (A and B) along
with the carry input (Cin). It produces a 4-bit binary sum output (S) representing the
result of the addition.
Step 6: Complete the design of the processing section by establishing necessary control points.

• From this figure, we observe that

there are 10 control points, C0, C1,
C2... C9
• If C0 is held high, the A register will
be cleared with the trailing edge of
the next clock. The other control
points are interpreted similarly. One
control point is introduced for each
microoperation specified in the
register-transfer description.
• The processing section extends three
outputs Q [1], Q[0], and Z; Z=1 only
when the contents of the L register
become zero.
• These outputs are the status outputs
and are used as inputs to the
controller to allow the controller to
decide the future course of action.
Step 7: Propose a block diagram of the controller.

• From the block diagram, it can be

seen that the controller has 5 inputs
and 10 outputs.
• The RESET input is an
asynchronous input used to reset the
controller, so a new computation can
begin.
• The clock input is used to
synchronize the controller's action.
• All activities are assumed to be
synchronized with the trailing edge
of the clock pulse.
 Step 8: Specify the state diagram of the controller.

• Initially, the controller is in the state . At this point

the control signals , and are high . Operations A 
0, L  4, and M  Inbus are carried out with the
trailing edge of the next clock pulse.
• The controller moves to the state , with this clock.
• When the control is in the state , A  A + M is
performed. If it is in A  A - M is performed.
• All these transfers take place with only the trailing
edge of the next clock. If the controller is in the
state , or it moves to the state , with the next
trailing edge of the clock.
• The controller moves to the state , only when a
computation is completed, so it stays in that state
forever.
• A hardware RESET input causes the controller to
switch to the state , and a new computation
begins.
• In this state diagram, selection of states is made according to the following guidelines:
 If the operations are independent of each other and can be completed within one clock cycle, they are grouped
within one control state operations. EX: A  0, M  Inbus, and L  4 are independent of each other. With this
hardware they are executed in one clock cycle. That is, they are microoperation’s. If these operations cannot be
performed within the selected clock cycle, however, either clock duration is increased or the operations are
divided into a sequence of microoperations.
 Conditional testing usually implies introduction of new states. For example the conditional testing of the bit pair
Q [1] Q [0] introduces the new state T2
 One should not make an attempt to minimize the number of states. When in doubt, new states must be introduced.

• There are 9 states in the controller state diagram. Nine nonoverlapping timing signals (To through T8.) must be
generated so only one will be high for a clock pulse. The below figure shows the first 3 timing signals.
Step 9: Specify the characteristics of the hardware elements to be used in the controller design.

• A mod-16 counter and and a 4-to-16 decoder

can be used to accomplish this task.
• The characteristics of the mod-16 counter is
discussed in the figure.
Step 10: Complete the controller design and draw a logic diagram of the final circuit.

• The controller and its logic diagram are shown in the

figure. The key element of this implementation is the
sequence controller (SC) hardware, which sequences
the controller as indicated in the state diagram (see step
8).
• For example: Consider the logic involved in deriving
the first entry of the SC truth table. Observe that the
mod-16 counter is loaded (or initialized) with the
specified external data if the counter control inputs C
and L are 0 and 1, respectively. (step 9)
• From the controller's state diagram, it can be seen that
if the present control state is (counter output =0010)
and if the bit pair inspected is 00, (that is, Q[1] Q[0] =
00), then the next control state is . When these input
conditions occur, the counter must be loaded with
external value 0101 along with the trailing edge of the
next clock pulse ( 1 only when = 0101). Therefore, the
SC generates L= 1 and = 0101.
• Using the same reasoning, the fifth entry of the SC truth table is obtained as follows.
• From the controller's state diagram, it can be seen that if the present control state is ,
and if Z = 0, the next control state is .
• The SC must generate the outputs L= 1 and = 0010 to achieve the desired state
sequence. Other entries of the SC truth table are derived in the same manner.
• When the counter load control input L= 0, the counter will automatically count up in
response to the next clock pulse (because the enable input E is tied to high). Such
normal sequencing activity is desirable in the following situations:
• Present control state is ,
• Present control state is and Q [1] Q [0] = 01
• Present control state is and Z= 1
• If the SC is removed and the counter load control input L is tied to low, the counter-
decoder combination acts as a ring counter. By including the SC, a status- dependent
ring counter is achieved.
Sequence controller Design

b. PLA Implementation
• This implementation follows the • The PLA generates five  The controller design is completed
SC truth table. For each row of the outputs: L, d3, d2, d1, and d0. by relating the control unit (T0-T8)
SC truth table, a product term is Each output is directly with control signals (C0-C9) as
generated in the PLA(programmed generated by using the SC truth below:
logic array). The product terms table and the product terms. C0 = C1 = C2 = T0
generated are summarized as The Boolean equations that
C3 = T1
below: govern the relationship
between the product terms and C4 = T3
the PLA outputs are C5 = T3 + T4
summarized below.
C6 = C7 = T5
L= P0 + P1 + P2+ P3 + P4 + P5 C8 =T6
d3 = P5 C9 = T7
d2= P0 + P1+P2+ P3
d1= P4
d0= P0 + P1+P3
2. Microprogrammed Control Unit

• A microprogrammed control unit's control words are held in a separate memory called the control
memory (CM). Each control word contains signals to activate one or more microoperations. When
these words are retrieved in a sequence, a set of microoperations are activated that will complete the
desired task.
• Retrieval and interpretation of the control words are done the same as a conventional program. The
instructions of a processor are held in the main store. They are fetched and executed in a sequence. By
changing the instructions stored in the main memory, the processor can perform different functions.
Similarly, by changing the contents of the CM, the control unit can execute a different control
function. Therefore, the microprogrammed approach offers greater flexibility than its hardwired
counterpart. since it provides an easy means for altering the contents of the CM.
• Generally, all microinstructions have two important fields:
• Control field: The purpose of the control field is to indicate which control lines are to be
activated.
• Next-address field: The purpose of the next address field is to specify the address of the next
microinstruction to be executed.

[Link]
• In the figure (Wilke’s design)
shown, the decoder and
diode( ) matrix utilize an 8
x 8 ROM.
• Each ROM holds an 8-bit
control word whose low-
order three positions specify
the next address and high-
order five positions indicate
control signals.
• The contents of the ROM are
retrieved by specifying the
address in the control
memory address register
(CMAR). For example, if
=010, then control lines
and , are enabled, and the
next ROM address, 011, is
fed back to the CMAR at the
same time.
[Link]
• It is possible to load the CMAR with an externally specified new starting address. Whenever the
external load input E is 1, the CMAR is loaded with an externally specified address. It is then possible to
keep several microprograms in the control memory and execute any desired microprogram by
specifying the starting address as an external address.
• Another important feature of this organization (Wilke’s design) is the ability to implement conditional
branching. The external condition sets or resets the condition flip-flop. For instance, if the external
condition sets the condition flip-flop to 1, control is transferred to ROM address 1 (=001) after
execution of microinstruction at ROM address 5. If the external condition is zero, the condition flip-flop
will be reset. Therefore, after execution of the microinstruction at ROM address 5, the control will be
transferred to ROM address 6 ( = 110).
• The microprogramming approach involves the inclusion of a control memory in addition to the
conventional main memory. Therefore, a major design effort has its emphasis on minimizing the length
of the microinstruction. The length of the microinstruction decides the size of the control store, as well
as the cost involved with this approach. The length of a microinstruction is directly related to the
following factors.
• The degree of parallelism, or how many microoperations can be activated simultaneously.
• The control field organization.
• The method by which the adders of the next microinstruction is specified.
• Consider the following situation shown in figure
(simple register transfer). Assume there are four
registers, A, B, C, and D, and each communicates
with the outbus when the appropriate control line is
activated:
Outbus = A
Outbus = B
Outbus = C
Outbus = D

• Since there is only one output bus, it is impossible

to allow more than one transfer at any given time. If
one bit is allocated for each control in the control
field, the result will appear as shown next.
• This method is also known as unencoded format
• There are only five valid binary patterns in the preceding
format; but from the basic switching theory, five distinct binary
patterns can be represented by using only 3 bits. Such an
arrangement is shown in figure (Encoded control arrangement).
• In the Figure shown, the control information is encoded into a
3-bit field, and a decoder is needed to extract the actual control
information. The relationship between the encoded and the
actual control information is specified as shown next:
• This method is known as encoded format, which leads to a
short control field and short microinstructions. The price paid
for such a reduction is the need to have a decoder. Therefore, a
compromise must be sought. Fifteen control lines can be
specified in a fully unencoded form as shown next:
• The same information can be specified in the
encoded form as shown next:
• A 4-to-16 decoder is needed to derive the
actual control signals. As a measure of
compromise, the control information is given
by a partial encoding as shown next:
• The control signals are partitioned into
disjoint groups, so two signals of different
groups can be activated in parallel. The
control signals have been divided into two
groups:

Group 1: C1, C2, C3, C4, C5, C6, C7

Group 2: C8, C9, C10. C11, C12, C13 C14, C15

• With the above grouping, C8, and C1, are

activated simultaneously but not C1 and C2.
The actual control signals are derived by
using one 3 to 8 and one 4 to 10 decoders.
• Microinstructions are classified into two groups, which express parallelism ability and the amount of encoding called:
• Horizontal
• Vertical
• The horizontal microinstruction has the following features:
• Long microinstructions
• Capability of expressing a high degree of parallelism
• Very little encoding
• The vertical instruction possesses the following basic attributes:
• Short instructions
• Limited scope for expressing parallelism
• Needs considerable amount of decoding

• In the original design proposed by M. V. Wilkes, the next address is specified in each microinstruction. A close
examination reveals that except in the case of a branch instruction, the address of the next micro-instruction to be
executed is the address of the memory word that follows the current microinstruction word. Therefore, the next
address field from the microinstruction can be eliminated by introducing a separate register used as a pointer to the
next instruction to be executed. This register is, in principle, the same as the PC. For this reason, it is known as the
microprogram counter (MPC). The MPC is usually incremented after each microinstruction fetch so it will always
point to the next microinstruction to be executed.
 Microprogrammed Control Organization
• Various components included in this organization are:
1. Control memory buffer register (CMBR): The CMBR functions the same as the MBR of
the main memory. It is basically a latch, and acts as a buffer for the microinstructions
retrieved from the CM. Typically, each microinstruction will have three distinct fields:
Condition Select Field Branch Address Field Control Function Field

• The condition select field selects the external condition to be tested. If the selected
condition is true, the output of the MUX will be 1.
• Since the output of the MUX is connected to the load input of the MPC, the MPC will be
loaded with the address specified in the branch address field of the microinstruction.
• However, if the selected external condition is false, the MPC will point to the next
microinstruction to be executed. Therefore, this arrangement allows conditional
branching. The control function field of the microinstruction may hold the control
information in an encoded form.
2. The micro-program counter (MPC): The MPC holds
the address of the next microinstruction to be executed.
Initially, it is loaded from an external source to point to the
starting address of the microprogram to be executed. From
then on, the MPC is incremented after each
microinstruction fetch, and the instruction fetched is
transferred to the CMBR. When a branch instruction is
encountered, the MPC will be loaded with the contents of
the branch address field of the microinstruction that is held
in the CMBR.
3. External condition selects MUX: This MUX selects one
of the external conditions according to the contents of the
condition select field of the microinstruction. Therefore,
the condition to be selected must be specified in an
encoded form. Any encoding leads to a short
microinstruction, which implies a small control memory;
hence, the cost is reduced. Suppose six external conditions.
X1, X2, X3, X4, X5, X6 are to be tested; then the
condition-select field and the MUX can be organized as
shown in figure.
• The contents of the Condition-select Field and Actions taken are summarized below.

• If the condition-select field contains 000, the output of the MUX is 0. The MPC will then be incremented to point the
next address. Therefore, no branching will take place.
• When the condition-select field is 111, the output of the MUX is 1, causing the MPC to down-load a branch address.
Since this happens regardless of any external condition, an unconditional branch is formed.
• When the condition-select field is 010, the output of the MUX is the same as the value of the external condition variable
X2.
• Therefore, the MPC will be loaded with a branch address only when X2 = 1; otherwise it is incremented.
• Conditional branching is achieved. The structure of the control memory will now be addressed. In the early days, the
control memory was organized as a ROM. ROM's were constructed by using a diode matrix, since it accessed faster than
ferrite-core read-write memories. Since the control program had little likelihood to change, it was economical to use a
ROM rather than a read-write memory. Present technology allows the use of control memories whose contents may be
rewritten.
 Micro Programmed Multiplier Control Unit For Booths Multiplier
STEP1: Write µprogram in a symbolic form.

• CM holds 13 words, requiring a 4-bit branch address field.

STEP2: Q[1]Q[0]=01, Q[1]Q[0]=10 and Z=0 are checked.
 These conditions are applied as i/ps to condition select MUX.
 MUX must have atleast 5 data i/ps and 8:1 data selector.
 3-bit cond .select field is used to encode 5 diff cond:

Cond Select Field Action Taken

0 0 0 No branching
0 0 1 Branch if Q[1]Q[0]=01
0 1 0 Branch if Q[1]Q[0]=10
0 1 1 Branch if Z=0
1 0 0 Unconditional branch
 Size of CW = Size of Cond. select field + Size of branch(size of address bits) + No of functions field
= 3 + 4 + 10
= 17 bits
 Size of CMDB is 17 bits and CM is 13 x 17 =221bits
Fig Microprogrammed Multiplier Control Unit
• For each line of the symbolic program listing, there exists a control word. For example, consider the first
line of the symbolic listing shown in figure 4.33. This instruction introduces no branching. Therefore, the
conditional select field should be 000. Thus, the contents of the branch address field are irrelevant.
However, the contents of this field can be reset to 0000 without any loss of generality. In this instruction,
three microoperations , and are activated. Therefore, only the corresponding bit positions in the control
function field are set to 1. This results in the following binary microinstruction:
Condition Select Branch Address Control Function
000 0000 1110000000
• The binary microinstructions corresponding to the tenth line of the symbolic microprogram does not
activate any microoperations. Therefore, all bits of the control function field must be reset to 0. Since the
branching is based on the value of the external condition variable Z, the condition select field must be set
to 011. If the condition is met, the program control must branch to execute the microinstruction whose
symbolic address is LOOP. Since this label appears in line number 2 of the symbolic listing, the branch
address is 2 (0010). The value of the branch address field must be 0010. The following binary
microinstruction is obtained:

Condition Select Branch Address Control Function

011 0010 0000000000
• Continuing in this manner, the complete binary-microprogram can be produced as shown in figure.
Exercise:
Consider the following register transfer description algorithm

Declare Registers: A[8], B[8], C[8];

START: A ← 0;
B ← 00001010;
LOOP: A ← A + B;
B ← B - 1;
If B< > 0 then go to LOOP;
C ← A;
HALT: Go to HALT

A. Design the processing section for implementing the above algorithm identifying all the control points.
B. Draw a neat state diagram. Write the operations performed and the control signals to be activated in
each state
C. Design controller using decoder, counter and sequence controller and draw the diagram
D. Draw the PLA diagram for implementing the sequence controller
D. Design a Modern Microprogrammed control unit and give the binary listing of the microprogram
Additional
• If the "enable" input signal (control unit) is false, the tri-state buffer passes a high impedance (or
hi-Z) signal, which effectively disconnects its output from the circuit. Tri-state buffers are often
connected to a bus which allows multiple signals to travel along the same connection.

Ref:
• 4-bit Adder/Subtractor: [Link]
• Serial i/o: [Link]
• Tristate: [Link]