INPUT OUTPUT

ORGANIZATION
INPUT-OUTPUT INTERFACE
 Peripheral devices
◦ IO subsystem provides an efficient mode of
communication between central system and outside
environment
◦Keyboard – common input device
◦Speed of keyboard is slow when compared to CPU
◦So CPU will be idle, waiting for data
◦So data & programs must be prepared in Magnetic
disks and tapes
peripherals

◦Input and output devices attached to the computer are called

peripherals
3 types
◦Input
◦Output
◦Input-output
 keyboard, display unit, printers
Magnetic disks and tapes –provide auxillary storage
Peripheral devices
INPUT-OUTPUT INTERFACE
◦Input-output interface provides a method for transferring
information between internal storage and external I/O devices.
◦Peripherals connected to a computer need special
communication links for interfacing them with the central
processing unit.
Differences b/w peripheral & CPU

◦Peripherals are electromechanical and electro

magnetic devices, whereas CPU and memory are
electronic devices. Therefore, a conversion of the
signal values may be required
◦Data transfer rate of peripherals is slower. So a
synchronization mechanism may be needed
◦ Data codes and formats in peripherals differ from
word format in CPU and memory
◦ Operating modes of peripherals are different
from each other
I/O Interface
◦Interface unit : special h/w components between CPU and
peripherals to supervise and synchronize all IO transfers
◦Types of interface: CPU interface, IO interface
◦CPU interface corresponds to the system bus
◦I/O interface depends on the nature of i/o devices
Functions of i/o interface
◦ Data conversion: conversion between digital and
analog signals, and between serial and parallel
data formats
◦ Synchronization: matching of operating speeds of
CPU and other peripherals
◦Device selection: selection of IO device by CPU in a
queue manner
 • I/O bus
I/O Bus and Interface Modules consists of
data lines,
address
lines and
control lines
•Each
peripheral
device has
an interface
unit
I/O bus and interface modules
◦Each interface decodes the address and control received from the
I/O bus, interprets them for peripheral , and provides signals for
peripheral controller
◦ It also synchronizes the data flow and supervises the transfer
between peripheral and processor
◦Each interface contains an address decoder
◦ To communicate with a device, processor places the device
address on address lines
◦ It also provides a function code (I/O command) in control lines.
 I/O BUS AND INTERFACE MODULE

◉ There are four types of commands that an interface may

receive
◼ Control Command
◼ Status Command
◼ Data Output Command
◼ Data Input Command
Commands

◦Control command: to activate peripheral and to

inform it what to do. E.g rewind the tape
◦ Status command is used to test various status
conditions in the interface and the peripheral.
◦For example, the computer may wish to check the
status of the peripheral before a transfer is initiated.
Commands

◦Data output command: causes the interface to

respond by transferring data from the bus into one of
its registers. The interface then communicates with
the device controller and sends the data to be stored
on the device
◦Data input command: interface receives the data
from the peripheral and places it in its buffer register.
I/O versus memory bus
◦Processor communicate with I/O and memory in 3 different
ways
1. Use separate buses for I/O and memory.
2. Use one common bus for m/y and i/o with separate control
lines
◦ IOP is used • Separate control lines
3. Common bus for memory and I/O with common control
lines
◦In the first method, CPU has independent set
of buses for both memory and IO. It is done in
computers that has separate IOP and CPU.
◦In second method computers use common
bus to transfer data between IO or memory
and CPU. And separate read and write lines.
◦IO read/write is enabled during IO transfer
and memory read/write is enabled during
memory transfer.
I/O versus memory bus
◦This configuration isolates all I/O interface address with the
memory address and is referred to as Isolated IO method.
◦ In third method same address space is used for both memory
and IO interface. They have only one set of read and write
signals.
Isolated I/O
◦ uses a common bus to transfer data/address between CPU
and memory or I/O
◦Isolates memory addresses from I/O interface addresses
◦Uses distinct input/output instructions
◦ uses separate read/write lines
◦ I/O read
◦ I/O write
◦ memory read
◦ memory write
◦Enables the corresponding r/w lines for the transfer of data
between CPU and I/o, or between CPU or memory
Memory‐mapped I/O

◦ Same address space for both memory and I/O

◦Segment of the total address space is reserved
for interface registers
– reduces memory address range

◦ Same instructions for I/O transfers and memory

transfers
◦ One set of read/write signals
◦Considers Interface register to be part of the
memory
◦Internal operations in a digital system are synchronised by
means of clock pulses supplied by common pulse generator.
◦Clock pulses are applied to all registers within a unit and all
data transfers among internal registers occur simultaneously
during a clock pulse
Example of I/O interface
MODES OF
TRANSFER
 Modes of transfer
◦CPU holds the data temporarily and the
ultimate source and destination is the
memory

◦Data transfer to and from peripherals can

be handled in one of 3 possible modes
◦ 1. Programmed I/O
2. Interrupt initiated I/O
3. Direct Memory Access(DMA)
Programmed I/O

◦ I/O device does not have direct access to memory

◦ I/O operations are the result of I/O instructions written in

computer programs

◦ Each data item transfer is initiated by an instruction in the program

◦ Transferring data under program control requires constant monitoring

of the peripheral by CPU

◦ CPU (busy) stays in a program loop until I/O unit indicates that
it is ready for data transfer. It is a time consuming process
 Programmed I/O example
Eg. Data transfer from an I/O device thru an
interface into CPU
•IO device places a byte of data in the I/O bus and enables
data valid line
•Interface accepts data into data register and enables
data accepted line
•Interface also sets F bit to 1 in the status register
•Device disables the data valid line
•IO device will not transfer next byte until
the data accepted line is disabled

•CPU checks the flag bit of the status

register to determine whether there is data
in the data register.

•If flag=1, CPU reads the data from data

register and clears the flag bit to 0 and
interface then disables data accepted line

•Now the IO device can transfer the next

byte
◦ The transfer of data requires three instructions:
 status

dat
a
Interrupt initiated I/O
◦ while CPU executes a program, interface may be monitoring the
device and informs the CPU when it is ready to transfer data.
◦When the device is ready for data transfer, interface generates an
interrupt request to the computer
◦ CPU suspend the current task, branches to a service program
to handle the I/O, and then resumes the original task
◦2 methods for choosing branch address of the service
routine
◦Vectored interrupt
◦Nonvectored interrupt
Vectored interrupt:

◦ Devices that use vectored interrupts are assigned an interrupt vector.

◦ This is a number that identifies a particular interrupt handler.
◦ This vector may be fixed, configurable (using jumpers or switches), or programmable.
◦ Vectored interrupts are achieved by assigning each interrupting device a unique
code, typically four to eight bits in length.
◦ When a device interrupts, it sends its unique code over the data bus to the
processor, telling the processor which interrupt service routine to execute.
◦ The source that interrupts supplies the branch information to the
computer. This information is called interrupt vector
◦ interrupt vector can be either
◦ first address of the service program
◦ address that point to a location in memory where first address of
the service routine is stored
Nonvectored interrupt
◦ branch address is assigned to a fixed location in memory.
◦Non-Vectored Interrupts are those in which vector address is not
predefined. The interrupting device gives the address of sub-
routine for these interrupts

◦ DMA: interface transfers data into and out of memory through memory bus

◦ CPU initiates the operation by giving starting address and number of word to
be transferred to the interface