Unit-II Operating Modes of Microprocessor

CO-To gain knowledge of Processor Operating Modes.

Santushti Betgeri
Introduction to Pentium Processor
• The Pentium processor was invented by the Intel Corporation in 1993.
• This processor is also called Pentium 1, P5 otherwise Intel 80586 as it was the 5th
generation of Intel microprocessors.
• It taken lead in Personal Computer market
• Used every where from dedicated control systems to super fast network file servers.
• Compatible with previous 80 x 86 machine with many improvement
• Pentium1 processor mainly include; 32-bit processing, 16 KB – 32KB L1 cache, FSB
(Fast serial bus) up to 66 MHz and base CLK speed ranges from 66HZ onwards.
• There are different Pentium microprocessors available in addition to the Pentium I like
Pentium II, III, IV, M, and dual core.
• This microprocessor includes approximately 3.1 million transistors, a 64-bit external
data bus & also a 32-bit address bus .
• As address bus is 32 bit it provides 4 GB of physical memory space.
What is superscalar Processor?
A translation look aside buffer is a memory cache
that is used to reduce the time taken to access a
user memory location.
 80286 80386 80486 Pentium
No of Pin 68 132 168 237
Width of data bus 16 32 32 64
With of address 24 32 32 32
bus
Width of Internal 16 32 32 32
Register
Clock Speed 10-16 12-66 16-100 60-100
(MHz)
Availability of NO YES YES YES
Instruction Pipeline
Operating Modes Real mode only Real, Protected Real, Protected All Modes
Virtual Virtual
Physical Memory 16MB 4GB 4GB 4GB
Virtual Memory 1GB 64TB 64TB 64TB
Segment Register CS,DS,ES,SS CS,DS,CS,SS,FS, CS,DS,CS,SS,FS, CS,DS,CS,SS,FS,
GS GS GS
Real Mode, Protected Mode
• The first processor in 80x86 family is 8086 which is 16 bit microprocessor.
• It provides 20 bit address bus i.e.1048576=1 MB
• The advanced processors 80286,80386,80486 and Pentium provides 32 bit
address bus i.e 4GB
• Due to large addressing space these processors supports many operating system
,such as multitasking which is difficult for 8086.
• All intel microprocessors work in 2 modes
1. Real mode
2. Protected mode
Real mode:- In real mode Pentium simply operates like very fast 8086 mode
with associated 1MB memory limit Real mode operation is automatically
selected upon when it power-ups.
So a Pentium-based PC that boots up into DOS is operating in real mode (DOS is
a real mode operating system).
• Protected mode :-
• In protected mode, the full 4096MB (4 gigabytes) of memory is available to the
processor, as are special privileged instructions and many other support for
multitasking, virtual memory addressing, memory management and protection,
and control over the internal data and instruction cache.
• The Windows operating system runs in protected mode to take advantage of these
features.
• Writing programs that run in protected mode requires special background
knowledge of O.S. theory.
• System management mode. This mode is designed for fast state snapshot and
resumption which is useful for power management.
• There is also a virtual-8086 mode that allows the processor to execute 8086 code
software in the protected, multi-tasking environment.
Difference between real mode and protected mode
Real mode: Protected mode:
•In this mode processor works as •In this processor works in full
8088 / 8086. capacity.
• This mode has only 1 MB memory •This mode has more than 1MB to few
addressing capability. GB memory addressing capability.
• This mode handles only one task at •This mode handles multiple task at
a time. time.
• In this memory address translation • In this memory address translation is
is not required. required.
• In this mode processor or computer • In this processor communicates with
directly communicate with ports and ports and devices through OS.
devices.
• This mode is not supporting • This mode is supporting memory
memory management. management
Software Model of Pentium
• The Pentium microprocessor contains EAX, EBX, ECX,EDX, EBP, ESI, and EDI are referred
to as general purpose registers.
• All are 32 bits wide.
• The four general purpose registers EAX, EBX, ECX , and EDX referred as data registers.
• The lower 16 bits of each register are called AX, BX, CX, and DX and may be split up into
halves of 8 bits each.
• Five other 32-bit registers are available for use as pointer or index registers.
• These registers are the stack pointer (ESP), base pointer (EBP), source index (ESI), destination
index (EDI), and instruction pointer (EIP).
• Pointer and index register can not be divided as data register.
• In all cases, the ‘E’ in the register stands for extended. Thus, EAX refers to extended AX
• Normally the 32-bit registers are not fully available when the processor is operating
in real mode.
• To maintain compatibility with 80x86 machines, only the 16-bit registers AX, BX, CX, DX, BP,
SI, and DI are available for use.
• A special technique can be used to utilize a 32-bit register (such as EAX) on an instruction-by-
instruction basis.
• A major difference between the Pentium and many other CPUs is in, the segment
registers.
• Six segment registers are used by the processor to control all accesses to memory and I/O,
and must be maintained by the programmer.
• The code segment (CS) is used during instruction fetches, the data segment (DS) is mostly
used while reading or writing data, the stack segment (SS) is used during in stack
operations such as subroutine calls and returns, and the extra segment (ES) is used as per
programmers need.
• Two additional segment registers, FS and GS, were added with the 80386. These may be
used as per need.
• All segment registers are 16 bits long.
• A 32-bitflag register is used to indicate the results of arithmetic and logical instructions.
• Included are sign, zero, carry, and parity flags, as well as flags that are used only in
protected mode.
Functional
Description
of
Pentium
• The Pentium processor is a complex machine with many inter locking parts.
• Pentium processor involves a parallel approach for instruction execution called instruction-level
parallelism through which more than one instruction gets executed in one clock cycle is called
superscalar processors.
• The superscalar processor uses the approach of simultaneously executing two instructions in one
clock cycle. The various functional units are as follows:
• Bus unit
• Paging unit
• Control ROM
• Execution unit with two integer pipeline (U-pipe and V-pipe)
• Instruction Cache
• Data cache
• Prefetch buffer
• Instruction decode
• Branch target buffer
• Dual processing logic
• Floating Point Unit
• Advanced programmable interrupt controller.(APIC)
[Link] Unit:-The Pentium communicates with the outside world via a 32-bit address bus and a
64- bit data bus. The bus unit is capable of performing burst reads and writes of 32 bytes to
memory, and through bus cycle pipelining, allows two bus cycles to be in progress
simultaneously.
[Link] Unit:-The page unit offers optional extensions of approximately 2 to 4 Mb page sizes.
[Link] ROM:-The control unit controls the five-stage integer pipelines U and V, and the
eight-stage floating-point .In the Architecture of Pentium Processor, the integer pipelines are used
for all instructions which are not involved in any floating-point operations. Therefore, the
Pentium can transmit two integer instructions in the same clock cycle and performance of the
processor is improved. This method is called superscalar architecture,
[Link] unit with two integer pipeline (U-pipe and V-pipe):-
The execution unit within the Pentium microprocessor contains two integer pipelines namely U-
pipe and V-pipe and each one has its separate ALU. There are five stages in which these pipelines
operate, namely, prefetch, decode-1, decode-2, execute, writeback. The U-pipe is responsible for
executing all integer as well as floating-point instructions while V-pipe executes simple integer
and some floating-point instructions.
• Here, the instruction fetch reads the instruction one at a time and stores them
in the instruction queue. During the execution of an instruction, the processor
does not sit idle and checks for the next two instructions in the queue. If the
two instructions are independent of each other then U-pipe and V-pipe are
assigned instructions individually so that execution can occur simultaneously.
However, in the case, the queued instructions are dependent on each other
then both the instructions are assigned to U-pipe for execution one after the
other and V-pipe remains idle.
• The U-pipeline is able to handle the full instruction set of the Pentium but the
V-pipeline has limited handling capability. The V-pipeline is able to handle
only simple instructions without any microcode support. The V-pipeline is
used to execute ‘simple integer instructions’ such as load/store type
instructions.
• Architecture of Pentium Processor use a set of pairing rules to select a simple
instruction which can go through the V pipeline. When instructions are
paired, initially the instruction is issued to the U-pipe and then the next
sequential instruction is issued to the V-pipe.
Each integer unit has the basic
five-stage pipeline as given
below:

Prefetch (PF)
Decode-1 (D1)
Decode-2 (D2)
Execute (E)
Write Back (WB)
Prefetch (PF):- In the prefetch stage of integer pipeline of the Pentium processor,
instructions are fetched from the instruction cache .
Decode-1 (D1):- In the decode-1 (D1) pipeline stage, the CPU decodes the instruction and
generates a control word.
Decode-2 (D2) The decode-2(D2) pipeline stage is required whenever the control word from
D1 stage is decoded the CPU generates addresses for data memory.
Execute (E) The execution stage is used for both ALU operations and data cache access.
Write Back (WB) The final stage of the five-stage pipeline is Write Back (WB). In the WB
stage, the CPU updates the contents of registers and status of the flag register after
completion of execution. In this stage, the V-pipeline conditional branch instructions are
verified for correct branch prediction.
5 Instruction cache:-
• In order to load the instructions into the execution unit, code cache, branch target buffer
and prefetch buffers operate together. The code cache or the external memory holds the
instructions from where these are fetched. While the branch target buffer holds the address
of the respective branch and the TLB (translational lookaside buffer) within the code cache
converts the linear address into the physical address that is used by the instruction cache.
• An 8KB instruction cache is used to provide quick access to frequently used
instructions. When an instruction is not found in the instruction cache, it is read
from the external data bus and a copy placed into the instruction cache for future
references.
[Link] cache :-A separate 8KB data cache stores a copy of the most frequently
accessed memory data. Since memory accesses are significantly longer than
processor clock cycles, it pays to keep a copy of memory data in a fast-reading
cache. The data and code caches may both be enabled/disabled with hardware or
software. Both also employ the use of a translation lookaside buffer, which converts
logical addresses into physical addresses when virtual memory is employed.
7. Prefetch buffer :-
The branch target buffer and prefetch buffers work together with the instruction
cache to fetch instructions as fast as possible. The prefetch buffers maintain a copy
of the next 32 bytes of prefetched instruction code, and can be loaded from the cache
in a single clock cycle, due to the 256-bit wide data output of the instruction cache.
This processor contains pairs of prefetch buffers having a size of 32-byte that
combinedly operate with branch target buffer BTB. Both the buffers operate
independently but not at the same time. One of the prefetch buffers starts fetching the
instructions in a sequential manner till the time branch instruction has not occurred.
However, as soon as the branch instruction is fetched by the prefetch buffer then BTB
will check for the branch but once it is checked by BTB that branch has not occurred
then linear fetching of instruction will continue.
[Link] decode:- It is part of Prefetch buffer only. It decodes the instruction kept
in instruction queue.
9. Branch target buffer BTB:-The Pentium uses a technique called branch prediction
to maintain a steady flow of instructions into the pipelines. To support branch
prediction, the branch target buffer maintains a copy of instructions in a different part of
the program located at an address called the branch target. The BTB is used to store the
target address and statistical information about the branch operation. Hence, the branch
prediction is able to predict branches and cause the Pentium to use the most likely target
address for instruction fetching. Pipeline freeze up caused by pipeline flushes and the
subsequent fetching operations are reduced and the program execution is accelerated
[Link] processing logic :- 2 prefetch buffer +2 ALU in execution unit.
Both data and code cache within the processor is organized in the 2-way
associated set cache. Each cache has 128 sets and each set has 2 lines
which are 32 bytes wide..
11. Floating Point Unit :-The floating point unit of the Pentium
maintains a set of floating point registers and provides 80-bit precision
when performing high-speed math operations. This unit has been
completely redesigned from the one used inside the 80486 and is also
pipelined. The floating point unit uses hardware in the U and V
pipelines to perform the initial work during a floating point instruction
(such as fetching a 64-bit operand), and then uses its own pipeline to
complete the operation. Since both integer pipelines are used, only one
floating point instruction may be executed at a time.
12. advanced programmable interrupt controller. :-There is an on-
chip Advanced Programmable Interrupt Controller that manages
interrupt and offers 8259A compatibility.
 Register Set of Pentium.
• There are three types of registers: General-purpose data registers, segment
registers, and status and control registers. The following figure shows these
registers:
• General-purpose Registers
• The eight 32-bit general-purpose data registers are used to hold operands for
logical and arithmetic operations, operands for address calculations and
memory pointers. The following shows what they are used for:
• EAX:-Accumulator for operands and results data.
• EBX:-Pointer to data in the DS segment.
• ECX:-Counter for string and loop operations.
• EDX:-I/O pointer.
• ESI:-Pointer to data in the segment pointed to by the DS register; source
pointer for string operations.
• EDI:-Pointer to data (or destination) in the segment pointed to by the ES
register; destination pointer for string operations.
• ESP:-Stack pointer (in the SS segment).
• EBP:-Pointer to data on the stack (in the SS segment).
• The lower 16 bits of the general-purpose registers can be used with the names
AX, BX, CX, DX, BP, SP, SI, and DI (the names for the corresponding 32-bit
ones have a prefix "E" for "extended"). Each of the lower two bytes of the
EAX, EBX, ECX, and EDX registers can be referenced by the names AH, BH,
CH, and DH (high bytes) and AL, BL, CL, and DL (low bytes).(in the real
mode)
• Segment Registers
• There are six segment registers that hold 16-bit segment selectors. A segment selector is a
special pointer that identifies a segment in memory. The six segment registers are:
• CS: code segment register
• SS: stack segment register
• DS, ES, FS, GS: data segment registers
• EFLAGS Register
• The 32-bit EFLAGS register contains a group of status flags, a control flag, and a group
of system flags.
The upper 16 bits of the flag register are used for protected mode operation
The flags are divided into two groups: control flags and status flags. The control
flags are IF (interrupt enable flag), DF (direction flag), and TF (trap flag). The status
flags are CF (carry flag), PF (parity flag), AF (auxiliary carry flag), ZF (zero flag), SF
(sign flag), OF(overflow flag), NT (nested task), and IOPL (input/output privilege
level). Most of the instructions that require the use of the ALU affect the flags.
Remember that the flags allow ALU instructions to be followed by conditional
instructions.
• The content/operation of each flag is as follows:
• CF: Contains carry out of MSB of result
• PF: Indicates if result has even parity
• AF: Contains carry out of bit 3 in AL
• ZF: Indicates if result equals zero
• SF: Indicates if result is negative
• OF: Indicates that an overflow occurred in result
• IF: Enables/Disables interrupts
• DF: Controls pointer updates during string operations
• TF: Provides single-step capability for debugging
• IOPL: Priority level of current task
• NT: Indicates if current task is nested
Generating a 20-bit address in the Pentium’s real mode

• The six segment registers, CS, DS, SS, ES, FS,

and GS, are all 16-bit registers controlled by the
programmer. A real mode segment, as defined by
Intel™, is a 64KB block of memory starting on
any 16-byte boundary. Thus, 00000, 00010,
00020, 20000, 8CE90, and E0840 are all valid
segment addresses.
• The information contained in a segment register
is combined with the address contained in
another 16-bit register to form the required 20-bit
address.
Problems for solving
Problems for solving

a) If CS contains 03E0H and IP contains 1F20H, from what address is

the next instruction fetched?
b) If SS contains 0400H and SP contains 3FFEH, where is the top of
the stack located?
c) If a data segment begins at address 24000H, what is the address of
the last location in the segment?
Problems for solving

a) If CS contains 03E0H and IP contains 1F20H, from what address is

the next instruction fetched?
The next instruction is fetched from address 05D20H.
b) If SS contains 0400H and SP contains 3FFEH, where is the top of
the stack located?
The top of the stack is located at 07FFEH.
c) If a data segment begins at address 24000H, what is the address of
the last location in the segment?

24000H+FFFFH=33FFFH
The last location in the segment is 33FFFH.
• Show the contents of stack memory after an interrupt has
been initiated. Assume that the stack pointer is at address
4500H prior to the interrupt and that CS, IP, and the flag
register containing 05F0H, 1A20H, and 0026H respectively
• Memory location 3000H has the word 7A20H stored in it.
What will each memory location contain after the
instruction is executed?
• When an interrupt is initiated in an 8086 microprocessor (or a similar architecture), the CPU automatically pushes the **Flags
Register (FLAGS)**, **Code Segment (CS)**, and **Instruction Pointer (IP)** onto the stack in that order.
• Given:
• - **Initial Stack Pointer (SP) = 4500H**
• - **CS = 05F0H**
• - **IP = 1A20H**
• - **FLAGS = 0026H**

• ### Stack Memory after Interrupt:

• | Address | Content | Description |

• |----------|---------|------------|
• | 44FEH | 0026H | Flags Register (Pushed first) |
• | 44FCH | 05F0H | Code Segment (Pushed second) |
• | 44FAH | 1A20H | Instruction Pointer (Pushed third) |

• ### Final Stack Pointer (SP):

• Since each push operation decreases the stack pointer by **2 bytes** (since stack operates in **LIFO** order and grows
downward in memory), the new SP after pushing three 16-bit values will be:
If DS contains 2000H and DI contains 1FE0H, from what address
in the memory location

• 21FE0