PVT Variations
Process Variation
• Variations in the semiconductor manufacturing process leads the change in the parameters
of the device such as threshold voltage, mobility of electrons.
• This variation will effect the device performance such as power consumption and speed.
• All the transistors in a chip cannot be expected to have the same process.
• Factors which can cause process variation;
o Wavelength of the UV light
o Manufacturing defects.
• The effects of process varition are
o Oxide thickness variation
o Dopant and mobility fluctuation
o Transistor width, length variation.
Voltage Variation
• Voltage variation can occur due to IR drop, noise.
• Lower voltage slows down the transistor switching thereby increases
delays, higher voltage speeds up the transistors switching thereby reducing
delay.
• Voltage variations can affect the speed and power efficiency of the
transistor.
• The supply voltage reaching the power pins will not be the same for all
standard cells. The power network has a finite resistance.
• The cell connected near to power net will behave differently and cell
connected farther to power network will behave differently due to IR drop
in nets resistance and capacitance.
Temperature Variation
• The temperature variation is with respect to junction and not ambient
temperature. The temperature at the junction inside the chip can vary
within a big range and that’s why temperature variation need to be
considered.
• Some regions of the chip have higher cell density and higher
switching, resulting in a higher power dissipation.
• Hence the junction temperature at these regions are higher, forming
localized hot spots. This variation in temperature across the chip can
result in different delays.
Temperature Inversion
• The delay depends on the output capacitance and I D current. When the
temperature increases, delay also increases. But when temperature increases,
delay variation shows different characteristics for lower technologies.
• Consider the current equation of a MOSFET.
ID = (1/2)μnCox (W/L)(VGS – VTh)2
• In higher tech node, mobility of electrons reduces with increase in
temperature which slows down the transistor thereby increasing delay.
• In lower tech node, as temperature increases, mobility of electron increases,
lowering threshold voltage, making switching faster, hence delay decreases.
Types of PVT variations
1. Global Variations: also know as inter die variations that effect the entire
chip uniformly.
Causes:
• Differences in manufacturing across different chips (DIE – to – DIE variations).
• All transistors on a chip experience similar changes in Process parameters.
Effects:
• One chip might be faster than another chip because of Global doping
Concentration differences.
2. Local Variation: also known as intra chip variations that occur Within
the same chip.
Causes:
• Random fluctuations during fabrication, voltage drops, and Localized
temperature changes.
Effects:
• Some transistors or circuit paths becomes faster or slower than others
within the same chip.
Types of On Chip Variations
• Traditional OCV (On-Chip Variation):
• Applies fixed derate factors (multipliers) to cell and net delays.
• Conservative approach with uniform margins to account for variations.
• Over-pessimistic for advanced technology nodes.
• AOCV (Advanced On-Chip Variation):
• Uses table-based derates varying based on path depth (number of gates/stages in the logic path).
• Longer paths get lower derates (less pessimism), shorter paths get higher derates (more
pessimism).
• Improves accuracy over traditional OCV but still somewhat pessimistic.
• POCV (Parametric On-Chip Variation):
• Statistical modeling using Gaussian distributions to represent variation in delay.
• Considers correlation between cells to provide realistic delay estimates.
• Reduces pessimism, improves timing accuracy especially for advanced nodes (7nm, 5nm, 3nm).
• Computationally intensive and harder to debug.
References
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• LinkedIn Materials.