18ECC311J -
MICROCONTROLLERS
AND INTERFACING
Krishna Kant, “Microprocessor and Microcontrollers, Architecture, Programming and System
Design 8085, 8086, 8051, 8096”, PHI, 2011
-Dr. A. Mohanbabu AP/ECE
Introduction to Microprocessor
Memory Banking:
Here we shall consider an 8086 processor which can hold 1MB of memory due to
its 20 address lines ( 2^20 = 1MB ). So this 1MB memory is divided into two parts
( two banks ), where one bank consists of all even addresses and the other bank
consists of odd addresses.
Purpose of memory banking:
• As the 16-bit data is stored in 2 locations, lower byte in lower address
and upper byte in next consecutive address location.
• The data stored here is 1345H. This is representation of data in
hexadecimal form. So whenever the processor needs to fetch this , it
first gives the address to the address bus and fetches 45H and then it
gives the next address, then it fetches 13H. So overall a 16-bit
processor needs 2 cycles to perform a 16-bit operation, which is
completely a wrong concept. This thing led to memory banking.
• If the memory can be divided into two parts, with some algorithm,
two 8-bit datas can be fetched in one cycle.
• As Even bank starts from 00000H and goes up to FFFFEH , it stores the
lower byte so also known as lower bank. Odd bank locations start
from 00001H and go upto FFFFFH , this stores higher byte , thus also
known as Higher bank in 8086.
How does Memory banking work?
• There are totally 20 address lines in 8086, that can access the
locations. Each location is decided by these 20 address lines ( A0 ,
A1 ……. A19 ).
• If observed, for every consecutive location starting from even
location, there is only change in address ( A0 is only different ).
• For Eg:
• Locations 0H and 1H are consecutive and have the same address
except A0.
• Locations 3H and 4H are consecutive but their addresses don’t have
that similarity.
Aligned data:
Locations 0H and 1H is the example of aligned data. 8086 can fetch this
type of data in one cycle.
Misaligned data:
Locations 3H and 4H are the example of misaligned data, 8086 needs 2
cycles to fetch this type of data.
• Now we would learn how we can access 16-bit aligned data in one
cycle.
• 8086 can only perform 16-bit operations, and cannot perform 8-bit
operations.
So we need that
• 8086 can be able to select lower bank only for 8-bit operations.
• 8086 can be able to select higher bank only for 8-bit operations.
• 8086 can be able to select both banks at single time for 16-bit operations.
• Then BHE, comes into picture. It stands for bus high enable or bank high
enable, and it is pronounced as BHE bar.
• MOV AL, 85 # 8 bit data from Lower bank (Even)
• MOV AH, 90 # 8 bit data from Higher bank (Odd)
• MOV AX, 1234H # 16 bit data from both banks (Odd & Even)
An example of memory
segmentation.
The starting addresses of the various segments and the segment
register contents are:
Hexadecimal and decimal equivalent
Architecture of 8086:
The main component of BIU are
a) Segment registers
1. Code Segment (CS)
2. Data Segment (DS)
3. Stack segment (SS)
4. Extra Segment (ES)
b) Special purpose register
1. Stack pointer (SP) – 16 bit
2. Base pointer (BP) – 16 bit
3. Source Index (SI) – 16 bit
4. Destination Index (DI) – 16 bit
Instruction sets in 8086
Hexadecimal and decimal equivalent
0
JUMP condition with sum and carry
JUMP condition to find smallest
number
Microprocessor buses and signals
• The pin configuration of the 8086 has been shown in Figure.
• As mentioned before, the 8086 can work either in minimum mode or in maximum mode by assigning the pin MN/MX to 5
V or GND.
• In minimum mode ( MN/MX= 5 V), the 8086 works in single processor environment whereas in maximum mode (MN/MX =
GND), it works in multiprocessor complex environment.
• A set of the 8086 pins change their functions based on the mode set by the MN/MX pin. Other pins have common
functions in both the modes.
8086 pins and signals
• Now we would learn how we can access 16-bit aligned data in one
cycle.
• 8086 can only perform 16-bit operations, and cannot perform 8-bit
operations.
8086 minimum mode configuration
8086 maximum mode configuration
DIRECT MEMORY ACCESS
• In direct memory access, the external logic is allowed to access the memory directly and to perform the
read/write operation. The 8086 floats its address/data lines during this period
• DMA in minimum mode ( = 5 V)
• Very much like the 8085, the direct memory access in minimum mode of the 8086 is facilitated through
HOLD and HLDA signals.
• When the external logic wishes to access the memory directly, it makes a request through high signal at
HOLD pin.
• The 8086 samples the HOLD input at low-to-high transition of CLK.
• The 8086 acknowledges the HOLD request through high-level at HLDA (HOLD Acknowledge) pin at the end
of the current bus cycle, or during an idle clock period (if no bus cycle is being executed).
• The 8086 floats the address, data and control lines at the same time.
• The external logic accesses the memory and on completion, it withdraws the HOLD request by making the
signal at HOLD pin low.
• The 8086 is sampling HOLD at every low-to-high transition of CLK. On detecting low signal at HOLD, it will
make the signal at HLDA low.
Timing diagram for direct memory access (minimum mode).
• DMA in maximum mode ( = GND)
• In maximum mode, two signals and are dedicate for the direct
memory access operation. In this case, the DMA request and the DMA
acknowledgement are received on the same line. Thus, and are two channels for
DMA, and using which, two separate external logics may access the
memory directly.
Timing diagram for direct memory
access (maximum mode).
• The 8086 microprocessor maintains an Interrupt Vector Table which stores the information regarding the location of interrupt
service routines of various interrupts.
• In a very simple way, whenever an interrupt occurs, the memory location of ISR is determined using the vector table, and the
program control branches to ISR after saving the flags and the program location (Instruction Pointer and Code Segment
Register) in stack.
• The IRET (Return from Interrupt Service Routine) is the last instruction of ISR. When it occurs the 8086 pops and restores the
contents of flags, Instruction Pointer and Code Segment Register and the execution of the main program restarts from the place
where it was interrupted.
• The interrupt vector table can be up to 1 KB starting from 00000H to 003FFH of main memory. For each interrupt, the
following is stored:
• Code Segment Register (16 bits)
• Instruction Pointer (16 bits)
• These two determine the memory location, i.e. where the ISR for the interrupt is located. The total 256 numbers of interrupts
may be represented (each in 4 bytes) in the vector table. These are identified as Type 0 to 255 or Vector 0 to 255 interrupts.
The 8086 vector table is shown in Figure
• IRET (1 byte)—Interrupt Return
Returns control to the point of interruption by popping IP, CS and then the Flags from the stack and continues the execution
at this location.
HALT STATE
• When HLT (Halt) instruction is executed, the 8086 enters the Halt
state.
• In this state, the 8086 stops fetching and executing instructions. In the
Halt state, no signals are floated. The Halt state can be terminated by
an Interrupt request or a Reset.
• During the Halt state, DMA request on HOLD (minimum mode) pin or
RQ/GT (maximum mode) pin gets recognized and the DMA operation
takes place. However, on the completion of DMA, the 8086 returns to
Halt state.
WAIT FOR TEST STATE
• When the 8086 executes the WAIT instruction, it enters WAIT FOR
TEST state. In this state, the 8086 generates an endless sequence of
idle clock periods. During these clock periods, the Address/Data and
control lines are not floated and BIU may execute memory read bus
cycles to fill up the instruction object code queue.
• A low signal on input pin terminates this wait state. If a valid
interrupt request is received in this wait state, the interrupt will be
processed. But after the processing of interrupt, the 8086 will come to
wait state.