Static Timing Analysis

(22LVS233)
Course Handling Faculty

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Module - 3

Interconnect Parasitics

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 Introduction
• Interconnect Parasitics: These are characteristics (like resistance and capacitance) of wires that
affect the timing of a digital design.

• Net: A wire that connects pins of standard cells and blocks in a digital design. It typically has one
driver but can connect to multiple cells or blocks (fanout).

• Physical Implementation: After placing the design components, the net can span across multiple
metal layers on the chip.

• Metal Layers: Different layers have distinct resistance and capacitance values.

• Segmenting the Net: For accurate electrical representation, the net is divided into smaller parts,
each with equivalent parasitics.

• Interconnect Trace: This refers to a specific segment of the net on a particular metal layer,
representing the wire’s electrical behavior. 3

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 RLC for Interconnect
1. Interconnect Resistance:
•Comes from the metal traces and vias in the design.

•It is the resistance between the output pin of one

cell and input pins of connected cells.

2. Interconnect Capacitance:
•Includes grounded capacitance and capacitance
between neighboring signal routes.
•It also comes from the metal traces.

3. Interconnect Inductance:
•Caused by current loops but is usually ignored at
the chip level due to short, narrow loops.
•Inductance is more important for board and
package-level analysis. 4

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 RLC for Interconnect
4. RC Representation:
•Interconnect resistance and capacitance are modeled as a distributed RC tree.
•The total resistance (Rt) and capacitance (Ct) are calculated as Rt = Rp * L and Ct = Cp * L, where Rp
and Cp are per-unit length values, and L is the trace length.

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 RLC for Interconnect
5. Simplified Models:
•T-model: The capacitance is placed in the middle of the resistive tree, and the resistance is split into
two equal sections.
•Pi-model: The capacitance is divided into two equal parts and placed on either side of the resistive
section.

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 RLC for Interconnect
6. N-section Model:
•A more accurate model by breaking Rt and Ct into multiple sections.
•The end sections can follow the T-model or Pi-model.

7. Pre-layout and Post-layout Analysis:

•Parasitic interconnects are used during design stages—estimated during pre-layout and detailed
extraction in post-layout. 7

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 Wireload Models
1. Purpose of Wireload Models:
• Used before layout or floorplanning to estimate
capacitance, resistance, and area overhead of
interconnects.
• Estimate net length based on the number of
fanouts.

2. Factors Affecting Wireload Models:

• Depend on the area of the block, meaning
different areas might use different models.
• Correlation: Larger block areas lead to longer
average net lengths.

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 Wireload Models
3. Components of Wireload Models:
•Resistance: Per unit length of the wire.
•Capacitance: Per unit length of the wire.
•Area Overhead: Area consumed by interconnects.
•Slope: Used for linear extrapolation when the fanout is
not listed.

4. Wireload Example:
•Shows a model where resistance, capacitance, area, and
fanout lengths are predefined.
•Example values:
- Resistance: 5.0 units
- Capacitance: 1.1 units
- Area overhead: 0.05 units
- Slope for extrapolation: 0.5 units
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 Wireload Models
5. Extrapolation for Non-listed Fanouts:
•If a fanout isn’t listed, the wire length is calculated by extrapolating from known values using the
slope.
•Example: For fanout 8, the length is 5.6 units, and based on that, capacitance, resistance, and area
overhead are computed.

6. Practical Calculation Example:

•Fanout of 8:
- Length: 5.6 units
- Capacitance: 6.16 units (Length × Capacitance coefficient)
- Resistance: 28 units (Length × Resistance coefficient)
- Area overhead: 0.28 units (Length × Area coefficient)

7. Usage in Design:
•Wireload models help in early-stage design to predict parasitics, ensuring accurate planning before
actual routing occurs. 10

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Wireload Models
Interconnect Trees

1. Interconnect RC Estimation:
•Resistance (Rwire) and capacitance (Cwire) of a pre-layout interconnect are first estimated.
•The delay in interconnect depends on how its resistance and capacitance are structured with respect
to the driver and load pins.

2. Delay Dependence on Interconnect Structure:

•The interconnect delay from the driver pin to the load pin depends on the topology (structure) of the
interconnect, affecting the path's resistance and capacitance.

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Wireload Models
Interconnect Trees

3. RC Tree Representations:
The RC structure can be represented in three different ways:

• Best-case tree:
- The load pin is assumed to be adjacent to the driver.
- There is no wire resistance between them.
- Wire and pin capacitance still load the driver.

•Balanced tree:
- Each destination pin shares an equal portion of wire resistance and capacitance.

•Worst-case tree:
- All destination pins are assumed to be at the far end of the wire.
- Each destination pin experiences the full wire resistance and capacitance. 12

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Wireload Models
Interconnect Trees

4. Conclusion:
•Although the total wire length and estimates for resistance and capacitance are the same, the
interconnect delay differs depending on the topology (best-case, balanced, or worst-case). 13

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Wireload Models
Specifying Wireload Models

1. Wireload Model Definition:

•A wireload model is specified using the ‘set_wire_load_model’ command.
•Example: set_wire_load_model “wlm_cons” -library “lib_stdcell” selects the ‘wlm_cons’ model
from the ‘lib_stdcell’ library.

2. Wireload Modes:
•Different wireload models can be applied to different parts of a net that crosses hierarchical
boundaries.
•Three modes exist:
- Top: All nets inherit the top-level wireload model.
- Enclosed: The wireload model of the block fully containing the net is used.
- Segmented: Each net segment within a block gets its wireload model from that block.

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Wireload Models
Specifying Wireload Models

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 Wireload Models
Specifying Wireload Models

3. Wireload Mode Specification:

•Use ‘set_wire_load_mode enclosed’ to set the wireload mode.

4. Examples of Wireload Modes:

•Top Mode: Top-level wireload model takes precedence over lower levels.
•Enclosed Mode: The block fully containing the net defines the wireload model for the entire net.
•Segmented Mode: Each segment of the net uses the wireload model of the block it passes through.

5. Wireload Models Based on Area:

•Wireload models can be assigned based on block area.
•Example: Use different wireload models for area ranges like 0–400, 400–1000, etc.

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Wireload Models
Specifying Wireload Models

6. Default Wireload Model:

•A default wireload model can be set in the cell library (e.g., ‘default_wire_load: "wlm_light"’).

7. Wireload Selection Groups:

•Wireload selection groups allow the use of different models based on area.
•Example: Use the ‘wire_load_selection’ group to define models for different area ranges.

set_wire_load_selection_group WireAreaSelGrp

8. Pre-layout Parasitics:
•These wireload models are used to estimate parasitics before the physical layout of the circuit.

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Representation of Extracted Parasitics

1. Parasitic Extraction:
•It refers to capturing unintended resistances, capacitances, and inductances from the layout.

2. Formats of Parasitics:
•DSPF (Detailed Standard Parasitic Format): A more detailed format that provides all the parasitic details with
high accuracy.
•RSPF (Reduced Standard Parasitic Format): A simplified version of DSPF, providing less detail but still
sufficient for many applications.
•SPEF (Standard Parasitic Extraction Format): A standard format that is widely used and provides necessary
parasitic data.

3. Proprietary Formats:
•SBPF (Proprietary Binary Format): Some tools offer proprietary binary formats, like SBPF, to reduce file size
and improve processing speed.

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Representation of Extracted Parasitics

Detailed Standard Parasitic Format

[Link] (Detailed Standard Parasitic Format):

•Used for representing parasitics (resistances and capacitances) in a SPICE-compatible format.
•Includes details about cell types, cell pins, and their capacitances.

2. SPICE Syntax:
•Parasitic elements (resistances and capacitances) are written using standard SPICE syntax.
•The file can be directly used as input for a SPICE simulator.

3. File Structure:
•Contains comments marked with "SPICE Comment statements" that describe cell types, nets, and
instances.
•Example DSPF file shows the interconnection between two components (primary input to buffer,
buffer to output).
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Representation of Extracted Parasitics

Detailed Standard Parasitic Format

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Representation of Extracted Parasitics

Detailed Standard Parasitic Format

4. Advantages and Drawbacks:

•Advantage: Can be used for detailed simulation as input to SPICE.
•Drawback: The syntax is verbose, leading to very large file sizes, making it impractical for larger
blocks.

5. Use Cases:
•Typically used for a small group of nets due to its large file size.

6. DSPF Comment Format:

•Net Definitions: Begin with "*|NET" followed by net name and capacitance.
•Instance Pins: Start with "*|I" and define the instance, pin, and associated properties.
•Subnodes and Ground Nets: Identified with "*|S" and "*|GROUND_NET" respectively.

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Representation of Extracted Parasitics

Detailed Standard Parasitic Format

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Representation of Extracted Parasitics

Reduced Standard Parasitic Format

1. RSPF (Reduced Standard Parasitic Format):

•Represents parasitics in a simplified form using a voltage source and a controlled current source.
•It is a SPICE-compatible format used in simulators.

2. Parasitic Reduction:
•Parasitics must be reduced and converted into the RSPF format.
•This reduction process is a drawback as it may affect the extraction accuracy.

3. Limitations:
•Bidirectional signal flow cannot be represented in the RSPF format.

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Representation of Extracted Parasitics

Reduced Standard Parasitic Format

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Representation of Extracted Parasitics

Reduced Standard Parasitic Format

4. File Example (RSPF File for TEST1 Design):

•The design includes resistances (R1, R2, R3) and capacitances (C1, C2, C3, C4) that represent
parasitics.
•Voltage sources (E1, E2) drive the circuit, and ideal components are used to simplify parasitic
representation.

5. Key Modeling Elements:

•Pin-to-pin interconnect delays are modeled using resistors and capacitors.
•RC delays are tuned to match real-world delays.
•Ideal voltage sources drive gate inputs for simplification.

This simplifies how parasitics are represented in simulations, though with certain trade-offs in detail
and flexibility.
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Representation of Extracted Parasitics

Standard Parasitic Exchange Format

1. SPEF Overview: SPEF is a format used to represent parasitics (like resistance and capacitance) in
electronic designs, helping to capture detailed information about these elements.

2. Compact and Detailed: It is a compact and efficient way to represent parasitics, crucial for accurate
simulations of signal behavior.

3. Example of a Net: The example shows a net (NET_27) with two fanouts and provides connections
and parasitic values:
•CONN: Defines connections (like pins or instances) in the net.
•CAP: Lists capacitance values between different nodes in the net.
•RES: Lists resistance values between different nodes.

4. Units: The units for resistance (R) and capacitance (C) are specified at the beginning of the SPEF
file. 26

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Representation of Extracted Parasitics

Standard Parasitic Exchange Format

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Representation of Extracted Parasitics

Standard Parasitic Exchange Format

5. Importance of SPEF: It is widely used in design tools due to its efficiency and detailed
representation of parasitics.

This format helps in ensuring accurate signal integrity and timing analysis in complex chip designs.

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Representing Coupling Capacitances

1. Capacitance Representation:
• Earlier, net capacitances were represented as grounded.
• In nanometer technologies, capacitances are mainly sidewall, meaning they should be represented
as signal-to-signal coupling capacitances.

2. Coupling Capacitance in DSPF:

• The DSPF (Detailed Standard Parasitic Format) includes coupling capacitances as an addition to
its standard.
• Coupling capacitances are duplicated between the two coupled nets.
• This duplication prevents direct use of DSPF in SPICE simulators.
• Some tools resolve this by splitting the coupling capacitance equally between the nets.

3. Limitations of RSPF:
• RSPF (Reduced Standard Parasitic Format) is a simplified representation and cannot handle
coupling capacitances.
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Representing Coupling Capacitances

4. SPEF Standard:
•SPEF (Standard Parasitic Exchange Format) handles coupling capacitances uniformly and
unambiguously.
•It is the preferred format for crosstalk timing analysis and is compact in file size.
•SPEF can represent parasitics with and without coupling.

5. File Size Management in SPEF:

•SPEF uses a name directory at the beginning of the file to map net names to indices, reducing
verbosity and file size.
•This method is widely used in extraction tools to optimize file size.

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Hierarchical Methodology
• Large designs use hierarchical methodology to manage parasitic extraction and timing verification.

• Parasitics at the block level are extracted first, then used at higher design levels.

• A block’s extracted parasitics can be used for timing verification with other blocks that aren't fully
laid out yet.

• Wireload model estimates are used for blocks that are still in the pre-layout stage (not completed).

• In a hierarchical flow, pre-layout blocks are treated as "black boxes" using wireload estimates,
while the top-level layout parasitics are fully extracted.

• Once all blocks are complete, parasitics from both the blocks and top-level layout are combined for
final verification.

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Hierarchical Methodology
Block Replicated in Layout:

•If a block is repeated multiple times in the layout, the parasitic extraction for one instance can be
reused for all instances.

•The layout of the block must be identical in all instances (e.g., no top-level nets affecting the internal
block).

•To achieve this, ensure no nets are routed over the block and that there’s sufficient shielding or
spacing near its boundary.

This approach helps manage the complexity of large designs and ensures accurate timing verification
across multiple levels of hierarchy.

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Reducing Parasitics for Critical Nets

1. Reducing Parasitics for Critical Nets
• Parasitics (like resistance and capacitance) can slow down signals in critical nets.
• The goal is to minimize the parasitic impact to improve performance.

2. Reducing Interconnect Resistance

• Low slew values: Important for faster transition times.
• Two methods to reduce resistance:
 Wide trace: A wider trace lowers resistance without significantly increasing parasitic capacitance.
 Routing in upper (thicker) metals: Upper layers have lower resistivity, helping reduce resistance,
delay, and transition times.

3. Increasing Wire Spacing

• Reduce coupling capacitance: Increasing space between wires reduces total capacitance and
crosstalk, which is critical in long, adjacent signal routes.

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Reducing Parasitics for Critical Nets

4. Parasitics for Correlated Nets
•In some cases, multiple nets (e.g., data signals in a DDR interface) need matched parasitics for
consistent timing.
•Matched routing: To maintain identical parasitics, the nets should be routed in the same metal layer
to avoid mismatched variations in different layers.

This way, you ensure that critical nets perform optimally by managing parasitics and timing
constraints.

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Module - 3

Delay Calculation

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Overview
Delay Calculation Basics

1. Design Components: A typical design consists of

combinational and sequential cells.

2. Pin Capacitance: Each cell in the library specifies pin

capacitance values for input pins, contributing to the
total capacitive load on a net.

3. Net Capacitance Calculation:

•Net capacitance is the sum of input pin capacitances
from connected cells (fanout) plus interconnect
contributions (ignored for simplicity in this section).
•Example: In NET0, the capacitance comes from the
UAND1 and UNOR2 cells’ input pins.
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Overview
Delay Calculation Basics

4. Input/Output Capacitance:
•Inputs like I1 and I2 have pin capacitances from
associated cells (UAND1 and UINV0).
•The output O1 has capacitance from the UNOR2 cell
and any external loads.

5. NLDM Timing Models: The cell library contains

Non-Linear Delay Models (NLDM), representing
timing through two-dimensional tables based on:
- Input transition time
- Output capacitance

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Overview
Delay Calculation Basics

6. Delay Calculation:
•Delays and output transition times for cells (like UINV0 and UAND1) can be calculated based on
input transition times and capacitance values.
•For multi-input cells, different pins may have different output transition times.

7. Slew Merge: For multi-input cells, the output transition time choice depends on the slew merge
option.

8. General Approach: Using this method, the delay through any logic cell can be calculated based on
the input pin transition time and the output pin capacitance.

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Overview
Delay Calculation with Interconnect

Pre-layout Timing:

1. Uses wireload models to estimate interconnect parasitics.

2. Sometimes, resistance in these models is ignored, focusing only on capacitance.

3. Capacitive-only delay calculation is done based on previously discussed methods.

4. If resistance is included, delay is calculated using NLDM models and total net capacitance.

5. Resistance adds extra delay between the driver and fanout cells.

6. Interconnect delay process is further explained in another section.

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Overview
Delay Calculation with Interconnect

Post-layout Timing:
1. Interconnect parasitics form an RC network between
driver and destination cells.
2. Example figures illustrate how nets map into
multiple subnodes (e.g., NET0).
3. The output load is now an RC structure, making
NLDM tables less applicable.
4. The use of NLDM with resistive interconnect is
covered in more detail in a later section.
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Cell Delay using Effective Capacitance

• Challenge with NLDM Models: Traditional
NLDM models can't handle output loads that
include interconnect resistance. Therefore, the
"effective capacitance" approach is used.

• Effective Capacitance Approach: This method

finds a single capacitance (Ceff) that makes the
circuit behave similarly to the original design
with interconnect resistance in terms of timing.

• RC Interconnect: The interconnect, represented as

an RC PI-network, is simplified to an equivalent
capacitance (Ceff), which gives the same output
delay as the original RC load.

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Cell Delay using Effective Capacitance

• Waveform Comparison: Output waveforms
with total capacitance, effective
capacitance, and actual RC interconnect
vary, but Ceff ensures the delay is the same
as in the actual design.

• Ceff Calculation:
- Formula: Ceff = C1 + k * C2 (0 ≤ k ≤ 1)
- C1 is near-end capacitance, and C2 is far-
end capacitance.
- If interconnect resistance is small,
Ceff ≈ total capacitance; • Factors Influencing Ceff:
if large, 1. Driving cell strength.
Ceff ≈ near-end capacitance (C1). 2. Load characteristics (input impedance).
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Cell Delay using Effective Capacitance

• Effect of Driving Strength: A weaker driving cell sees a higher effective capacitance, while a
stronger cell sees a lower one.

• Iterative Process: The delay calculation involves matching the charge transfer between the actual
RC load and the effective capacitance through an iterative process until convergence.

• Limitations: Ceff is a good model for delay but doesn't accurately predict the full output waveform,
particularly the trailing half.

• Thevenin Model: The procedure also derives an equivalent Thevenin voltage source (a ramp
source with series resistance) to compute timing through the RC interconnect.

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Interconnect Delay
Interconnect Delay:

•Interconnect parasitics are modeled as RC circuits (pre-layout or post-layout).

•Post-layout parasitics include coupling to neighboring nets, but all capacitances are treated as
grounded for delay calculations.
•Delay is calculated using the effective capacitance approach, which separately computes delays
through the driving cell and the interconnect.
•The Thevenin equivalent source is used to compute delays from the driving cell output to multiple
destination pins.
•For pre-layout analysis, interconnect delay is determined by the type of RC tree selected by the
library (best-case, typical-case, or worst-case).

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Interconnect Delay
Elmore Delay:

•Applicable to RC trees with a single input, no

resistive loops, and all capacitances grounded.
•Elmore delay calculates delay at each node as a
sum of resistances and capacitances from
source to sink.
•The delay for a wire is modeled as Rwire *
(Cwire/2 + Cload).
•Two models:
- Balanced tree model: resistance and
capacitance are evenly divided among branches.
- Worst-case tree model: total resistance and
capacitance are used for each endpoint.

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Interconnect Delay
Elmore Delay:

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Interconnect Delay
Higher-Order Interconnect Delay Estimation:

•Elmore delay uses the first moment of the impulse response.

•Higher-order methods like AWE and Arnoldi provide more accurate delay estimation by considering
additional response moments.

Full Chip Delay Calculation:

•Delays for cells and their interconnects are computed stage by stage across the entire design.
•The delay at the output of one stage is used as the input to the next stage, ensuring accurate delay
propagation across the whole chip.

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Slew Merging
1. Slew Merge Point:
•When multiple signal slews converge at a point (e.g., in
multi-input cells), the point is referred to as a slew merge
point.
•The timing and nature of these slews can vary, creating
a choice about which slew to propagate forward.

2. Types of Slews:
•One slew can arrive earlier but rise slowly (slow slew).
•Another slew may arrive later but rise quickly (fast
slew).

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Slew Merging
3. Max Path Analysis:
•Worst Slew Propagation: Selects the slowest rising (worst) slew at the merge point. Accurate for
early-arriving paths (A->Z), but pessimistic for later-arriving paths (B->Z).
•Worst Arrival Propagation: Selects the slowest arriving slew at the merge point. Accurate for later-
arriving paths (B->Z), but optimistic for early-arriving paths (A->Z).

4. Min Path Analysis:

•Best Slew Propagation: Selects the fastest rising (best) slew at the merge point. Exact for later-
arriving paths (B->Z), but pessimistic for earlier paths (A->Z).
•Best Arrival Propagation: Selects the earliest arriving slew. Exact for early-arriving paths (A->Z), but
optimistic for later-arriving paths (B->Z).

5. Static Timing Analysis (STA):

•STA tools typically use worst or best slew propagation to be conservative.
•Exact slew propagation is an option for more precise analysis of specific paths, though it may require
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Slew Merging
6. Design Consideration:
•The designer should know which slew propagation mode is being used in the tool to avoid overly
pessimistic or optimistic results, especially during max and min path analysis.

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Different Slew Thresholds

1. Slew Thresholds:
•Slew or transition time is the time taken for a signal to switch from one level to another (low to high
or high to low). It is characterized by different percentage thresholds, such as 20-80%, 10-90%, etc.

2. Problem with Different Slew Thresholds:

•When a cell characterized by one set of slew thresholds drives other cells with different slew
threshold settings, it creates a situation where the transition times must be recalculated based on the
thresholds of each cell.

3. Example Setup (U1, U2, U3):

- Cell U1 is characterized with 20-80% slew thresholds.
- Cell U2 has 10-90% thresholds.
- Cell U3 has 30-70% thresholds with a slew derate factor of 0.5.

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Different Slew Thresholds

3. Example Setup (U1, U2, U3):
- Cell U1 is characterized with 20-80% slew thresholds.
- Cell U2 has 10-90% thresholds.
- Cell U3 has 30-70% thresholds with a slew derate factor of
0.5.

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Different Slew Thresholds

4. Slew Propagation:
•When U1 drives U2 and U3, the transition time (slew) at U1's output pin (Z) is used to calculate the
input slews for U2 and U3, based on their respective slew threshold settings.

5. Impact of Different Thresholds:

•U2’s slew is calculated using 10-90% settings.
•U3’s slew is calculated using 30-70% settings, then adjusted (derated) by the slew derate factor (0.5).

6. Calculation of Slews Between Different Thresholds:

•The relationship between different slew thresholds can be computed using proportionality. For
example:
- A slew measured at 500ps with 10-90% corresponds to 375ps with 20-80%.
- A slew of 600ps with 20-80% corresponds to 800ps with 10-90%.

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 BANGALORE INSTITUTE OF TECHNOLOGY

Different Slew Thresholds

7. Pre-layout Design Phase:
•During early design phases, where interconnect resistance is ignored, these slew conversions are
important to accurately estimate transition times.

This demonstrates how tools calculate delays and slews in circuits when cells with different slew
threshold settings interact.

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 BANGALORE INSTITUTE OF TECHNOLOGY

Different Voltage Domains

1. Different Power Supply Levels: A chip can have various sections operating at different voltage
levels.

2. Level Shifting Cells: Special circuits called level shifting cells are used to handle signals between
sections of the chip that operate at different voltages.

3. Input and Output Handling: These cells take input at one voltage (e.g., 1.2V) and provide output at
a different voltage (e.g., 0.9V).

4. Delay Calculation: The delay in the circuit is measured from the 50% voltage threshold points of
the signal, which vary depending on the voltage level of each pin in the interface cells.

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 BANGALORE INSTITUTE OF TECHNOLOGY

Slack Calculation
1. Definition of Slack:
- Slack is the difference between the required time and the actual time a signal arrives.

2. Example:
- In the given case, the data is required to be stable at 7ns to meet the setup requirement.
- However, the data becomes stable at 1ns.
- Slack is calculated as the difference: 7ns - 1ns = 6ns.

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 BANGALORE INSTITUTE OF TECHNOLOGY

Slack Calculation
3. Formula for Slack:
- Slack = Required Time - Arrival Time.
- Required Time is determined by the setup time of the capture flip-
flop.

4. Required Time Calculation:

- Required Time = Clock Period (Tperiod) - Setup Time of the
capture flip-flop (Tsetup).
- For example: Required Time = 10ns - 3ns = 7ns.

5. Arrival Time:
- The signal arrives at 1ns.

6. Final Slack Calculation:

- Slack = 7ns (Required Time) - 1ns (Arrival Time) = 6ns. 57

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 BANGALORE INSTITUTE OF TECHNOLOGY

Slack Calculation
7. Skew Example:
- If there is a skew requirement of 100ps and the measured skew is 60ps, the slack in skew is 40ps
(100ps - 60ps).

This demonstrates that slack is a measure of the timing margin or the difference between what is
required and what actually occurs.

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING