Static Timing Analysis

(22LVS233)
Course Handling Faculty: Keshava A

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Module - 2

Standard Cell Library

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 Introduction
Overview of Timing Information in Library Cell Descriptions

1. Library Cell Types:

•Cells can be standard cells, IO buffers, or complex IP blocks (e.g., USB core).

2. Library Cell Attributes:

•Besides timing information, descriptions include attributes like cell area and functionality.
•These attributes are essential for RTL synthesis but are not related to timing.

3. Focus on Timing and Power:

•This chapter concentrates on attributes relevant to timing and power calculations.

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Introduction
Overview of Timing Information in Library Cell Descriptions

4. Standard Formats for Library Descriptions:

•Library cells can be described using various standard formats.
•The content across different formats is similar, but examples in this chapter use the Liberty
syntax.

5. Timing Models Covered:

•The chapter begins with linear and non-linear timing models.
•Advanced timing models for nanometer technologies are also discussed in this chapter.

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 Pin Capacitance
1. Capacitance Specification:
•Every input and output pin of a cell can have a specified
capacitance.
•Typically, capacitance is specified for input pins; output pin
capacitance is often set to 0 in most cell libraries.

2. Example Specification for Input Pin (INP1):

•Capacitance: A single value of 0.5 units (likely picofarads) is
specified for INP1.
•Rise Capacitance: 0.5 units for the rising transition at INP1.
•Fall Capacitance: 0.45 units for the falling transition at INP1.
•Capacitance Ranges:
Rise Capacitance Range: 0.48 to 0.52 units.
Fall Capacitance Range: 0.435 to 0.46 units.
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Pin Capacitance
3. Basic vs. Detailed Capacitance:
•Basic Form: Capacitance specified as a single value (e.g., 0.5 units).
•Detailed Form: Separate values for rise and fall capacitance, with optional ranges to account
for variation.

4. Units and Library File:

•Capacitance is usually measured in picofarads.
•The unit of capacitance is specified at the beginning of the cell library file.

5. Importance in Design:
•Capacitance values influence the timing and behavior of the circuit, especially during signal
transitions.
•Specifying different rise and fall capacitances helps in accurately modeling the cell’s
performance for different signal transitions.
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Timing Modeling
1. Purpose of Timing Models:
•Provide accurate timing information for
various instances of a cell in a design.
•Derived from detailed circuit simulations to
reflect real operation scenarios.

2. Timing Arcs in an Inverter Cell:

•Rising Input Transition: Causes a falling
transition at the output.
•Falling Input Transition: Causes a rising
transition at the output.
•Two key delays are characterized:
- Tr: Output rise delay.
- Tf: Output fall delay.
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Timing Modeling
3. Measurement of Delays:
•Delays are measured from when the input
crosses its threshold point to when the output
crosses its threshold point.
•Typically, these threshold points are at 50% of
Vdd.

4. Factors Affecting Delay:

•Output Load (Capacitance): Larger load
capacitance leads to larger delay.
•Input Transition Time: The time it takes for the
input signal to change from one state to another.
•Generally, longer input transition time increases
delay.
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Timing Modeling
5. Non-Monotonic Delay Behavior:
•In some scenarios, where the input threshold differs from the cell's internal switching point,
delays may behave unexpectedly (non-monotonic).
•A larger input transition time might sometimes result in a smaller delay, particularly with
light output loads.

6. Output Slew and Transition Time:

•Output Slew: The rate of change at the output, mainly influenced by output capacitance.
•Larger output capacitance increases output transition time (slew).
•Input slew can either improve or worsen the output transition time, depending on the cell
type and load.

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Timing Modeling
7. Examples of Output Transition Behavior:
•Figure illustrates cases where output
transition time can either improve or
deteriorate based on the output load and the
cell type.

8. Summary:
•Timing models help predict cell behavior in
a design, considering factors like load
capacitance and input transition time.
•Understanding these factors is crucial for
accurate timing analysis and optimization in
digital circuit design.

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Timing Modeling
Linear Timing Model

[Link] Delay Model:

•Simplifies timing by representing delay and output transition time as linear functions.
•Based on two parameters: input transition time and output load capacitance.

2. Formula for Delay (D):

•D = D0 + D1 * S + D2 * C
•D0, D1, D2: Constants specific to the cell.
•S: Input transition time (how quickly the input changes).
•C: Output load capacitance (the capacitive load the cell drives).

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Timing Modeling
Linear Timing Model

3. Limitations of Linear Models:

•Not accurate for submicron technologies where the range of input transition time and output
capacitance varies widely.
•Due to this inaccuracy, more complex models, such as non-linear delay models, are
preferred in modern cell libraries.

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Timing Modeling
Non-Linear Timing Model

1. Purpose of NLDM Models:

•Used to specify delays, output slew, and other
timing checks for various timing arcs of a cell.
•Common in cell libraries, especially for
nanometer technologies.

2. Table-Based Representation:
•Delays are presented in a two-dimensional table.
•Independent variables: Input Transition Time and
Output Load Capacitance.
•The table entries indicate the delay values for
specific combinations of these variables.
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Timing Modeling
Non-Linear Timing Model

3. Structure of NLDM Tables:

•Cell Rise (cell_rise): Represents the delay when the output transitions from low to high.
•Cell Fall (cell_fall): Represents the delay when the output transitions from high to low.
•Rise Transition (rise_transition): Time taken for the output to rise based on input transition
and output load.
•Fall Transition (fall_transition): Time taken for the output to fall.

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Timing Modeling
Non-Linear Timing Model

4. Template Specification:
•Lookup table templates define the order and nature
of variables.
•Example: delay_template_3x3 with indices for input
transition and output capacitance.
•The first index is usually the row (input transition),
and the second is the column (output capacitance).

5. Example of Table Lookup:

•For an input transition time of 0.3ns and an output
load of 0.16pF, the rise delay could be found in the
cell_rise table.
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Timing Modeling
Non-Linear Timing Model

6. Timing Sense:
•The timing_sense field indicates whether the cell is inverting (e.g., negative_unate means
the output changes in the opposite direction to the input).

7. Interpolation for Non-Exact Matches:

•If the input transition time or output capacitance doesn’t exactly match the table, two-
dimensional interpolation is used.
•The delay value is calculated by interpolating between the nearest table entries.

8. Example of Interpolation:
•Given input transition time and output capacitance not directly in the table, interpolation
formulas are used to find the delay.
•This process works even for values outside the characterized range (extrapolation). 16

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Timing Modeling
Non-Linear Timing Model

9. 3-Dimensional Tables:
•In complex cells like flip-flops with multiple outputs, NLDM tables can be three-
dimensional.

10. Overall Use:

•NLDMs are widely used in timing analysis to predict how different factors like input slew
and output load affect the timing performance of cells.

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Timing Modeling
Threshold Specifications and Slew Derating

The slew values are based upon the measurement thresholds specified in the library. Most of
the previous generation libraries (0.25μm or older) used 10% and 90% as measurement
thresholds for slew or transition time.

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Timing Modeling
Threshold Specifications and Slew Derating

The slew thresholds are chosen to correspond to the linear portion of the waveform. As
technology becomes finer, the portion where the actual waveform is most linear is typically
between 30% and 70% points.

Thus, most of the newer generation timing libraries specify slew measurement points as 30%
and 70% of Vdd.

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Timing Modeling
Threshold Specifications and Slew Derating

However, because the transition times were previously measured between 10% and 90%, the
transition times measured between 30% and 70% are usually doubled for populating the
library. This is specified by the slew derate factor which is typically specified as 0.5.

The slew thresholds of 30% and 70% with slew derate as 0.5 results in equivalent
measurement points of 10% and 90%.An example settings of threshold is illustrated below.

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Timing Modeling
Threshold Specifications and Slew Derating

The above settings specify that the transition times in the library tables have to be multiplied
by 0.5 to obtain the transition times which correspond to the slew threshold (30-70) settings.

This means that the values in the transition tables (as well as corresponding index values) are
effectively 10-90 values.

During characterization, the transition is measured at

30-70 and the transition data in the library corresponds
to extrapolation of measured values to 10% to 90%
((70- 30)/(90- 10) = 0.5).

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Timing Modeling
Threshold Specifications and Slew Derating

Another example with a different set of slew threshold settings may contain:

• In this example of 20-80 slew threshold settings, there is no slew derate from library
specified (implies a default of 1.0),which means that the transition time data in the library is
not derated.
• The values in the transition tables correspond directly to the 20-80 characterized slew
values.
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Timing Modeling
Threshold Specifications and Slew Derating

Here is another example of slew threshold settings in a cell library.

In this case, the slew derate from library is set to 0.6 and characterization slew trip points are
specified as 20% and 80%.

This implies that transition table data in the library corresponds to 0% to 100% ((80-
20)/(100- 0) = 0.6) extrapolated values.

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 Timing Modeling
Threshold Specifications and Slew Derating

When slew derating is specified, the slew value internally used

during delay calculation is:

library_transition_time_value * slew_derate

This is the slew used internally by the delay calculation tool

and corresponds to the characterized slew threshold
measurement points.

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Timing Modeling
Threshold Specifications and Slew Derating

[Link] of Slew Values:

•Slew values, or transition times, are based on specific measurement thresholds in the timing
library.

2. Older Generation Libraries:

•Used 10% and 90% of Vdd as thresholds for measuring slew.

3. Newer Generation Libraries:

•Typically use 30% and 70% of Vdd for measuring slew.
•This range corresponds to the most linear portion of the waveform.

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Timing Modeling
Threshold Specifications and Slew Derating

4. Slew Derate Factor:

•To maintain consistency with older measurements (10%-90%),
a slew derate factor (usually 0.5) is applied.
•This factor doubles the 30%-70% measurement to approximate
10%-90% values.

5. Threshold Example:
•A library might specify:
- Slew lower threshold (fall): 30%
- Slew upper threshold (fall): 70%
- Slew derate factor: 0.5
•Transition times in the library must be multiplied by 0.5 to
obtain 30%-70% values. 26

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Timing Modeling
Threshold Specifications and Slew Derating

6. Alternative Slew Thresholds:

•Some libraries may use different thresholds, like 20%-80%.
•If no slew derate factor is specified, the transition times directly reflect the 20%-80%
measurement.

7. Impact of Slew Derating:

•When a slew derate is specified (e.g., 0.6), it adjusts the library transition times to
correspond to different threshold ranges, like 0%-100%.
•The internal delay calculation uses these derated values.

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Timing Modeling
Threshold Specifications and Slew Derating

8. Practical Example:
•If a library uses 20%-80% thresholds with a slew derate of 0.6, the library's transition data
reflects a range of 0%-100%.
•The delay calculation tool internally uses the derated transition time for accurate timing
analysis.

In summary, slew values are crucial in timing analysis, and the use of a slew derate factor
allows consistent comparison across different threshold ranges.

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 Timing Modeling – Combinational Cells
1. Timing Arcs:
• The cell in question is a two-input AND gate.
• Timing arcs represent the relationship between the input transitions and the output
transitions.

2. Positive Unate:
• Both timing arcs are "positive_unate," meaning:
 An input pin rising edge corresponds to the output rising.
 An input pin falling edge corresponds to the output falling.

3. Four Delays:
• There are four specific delays to consider in this AND gate:
 A -> Z: Output rise
 A -> Z: Output fall
 B -> Z: Output rise
 B -> Z: Output fall 29

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Timing Modeling – Combinational Cells

4. NLDM Model:
• The NLDM (Non-Linear Delay Model) requires four table models to specify these delays.
• Additionally, four similar table models are needed to specify the output transition times.

This structure helps in accurately modeling the behavior of the AND gate during simulation.

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Timing Modeling – Combinational Cells

Delay and Slew Models

1. Timing Model Description:

•The exmple describes a timing model for a three-input NAND gate
from input pin `INP1` to output pin `OUT`.

2. Timing Parameters:
•Max Transition: The maximum allowed transition time at the output
pin `OUT` is specified as 1.0.
•Related Pin: The timing is related to the input pin `INP1`.
•Timing Sense: It is specified as negative unate, meaning the output
transitions in the opposite direction to the input.

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Timing Modeling – Combinational Cells

Delay and Slew Models

3. Cell Delay Tables:

•cell_rise: Specifies the delay when the output rises due to the input
falling.
•cell_fall: Specifies the delay when the output falls due to the input
rising.
•These tables use two index parameters and a 3x3 matrix to define
the delay values.

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Timing Modeling – Combinational Cells

Delay and Slew Models

4. Transition Tables:
•rise_transition: Defines the transition time for a rising output.
•fall_transition: Defines the transition time for a falling output.
•Similar to the delay tables, these use a 3x3 matrix format with two
index parameters.

5. Unate Concept:
•Negative Unate: In the case of the NAND gate, the timing arc is
negative unate, meaning that if the input pin transition is in one
direction (e.g., falling), the output pin transition will be in the opposite
direction (e.g., rising).
•Positive Unate (comparison): In contrast, gates like AND or OR are
positive unate, where the input and output transitions are in the same
direction. 33

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Timing Modeling – Combinational Cells

General Combinational Block

[Link] Block Example:

•A block with three inputs and two outputs.

2. Timing Arcs:
•Represent the possible paths from each input to each output.
•Determine the propagation delays through the block.

3. Positive and Negative Unate Timing Arcs:

•Positive Unate (Non-Inverting): Output has the same polarity as the
input (e.g., if input rises, output rises).
•Negative Unate (Inverting): Output has the opposite polarity to the
input (e.g., if input rises, output falls).
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Timing Modeling – Combinational Cells

General Combinational Block

4. State-Dependent Timing Arcs:

•Some arcs can be both positive and negative unate depending on the input states.
•Example: A two-input XOR gate can produce an output transition in the same or opposite
direction, depending on the other input's state.

5. Non-Unate Arcs:
•Describes timing arcs where the relationship between input and output transitions is not
fixed.
•Timing models for such arcs can be described as non-unate or as separate positive and
negative unate models, depending on the state.

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Timing Modeling – Combinational Cells

General Combinational Block

6. State-Dependent Tables:
•These tables capture the timing behavior of state-dependent arcs and are detailed further in
the Section.

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 Timing Models - Sequential Cells
1. Synchronous Inputs (e.g., Pin D, SI, SE):
•Setup Check Arc: Ensures data is stable before the clock
edge (checked for both rising and falling edges).
•Hold Check Arc: Ensures data remains stable after the clock
edge (checked for both rising and falling edges).

2. Asynchronous Inputs (e.g., Pin CDN):

•Recovery Check Arc: Ensures proper recovery time after an
asynchronous signal is deactivated before the next clock
edge.
•Removal Check Arc: Ensures proper time for an
asynchronous signal to be removed before the clock edge.

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 Timing Models - Sequential Cells
3. Synchronous Outputs (e.g., Pins Q, QN):
•CK-to-Output Propagation Delay Arc: Measures the delay
from the clock edge to the change in output (checked for
both rising and falling edges).

4. Clock and Asynchronous Pin Checks:

•All synchronous timing arcs are referenced to the active
clock edge, the edge that causes the sequential cell to
capture data.
•Clock and asynchronous pins may have pulse width timing
checks to ensure proper operation.

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 Timing Models - Sequential Cells
5. Timing Checks Visualization:
•Figure illustrates these timing checks with various signal waveforms, showing how data and
clock interactions are analyzed.

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Timing Models - Sequential Cells

Synchronous Checks: Setup and Hold

[Link]:
•Ensure proper data propagation through sequential cells like flip-flops.
•Verify that data is stable and unambiguous at the clock's active edge, allowing correct data
latching.

2. Setup Time:
•Definition: The minimum time before the active clock edge during which the data input
must remain stable.
•Measurement: Time interval from the last data signal crossing its threshold (usually 50% of
Vdd) to the active clock edge crossing its threshold.

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 Timing Models - Sequential Cells
Synchronous Checks: Setup and Hold

3. Hold Time:
•Definition: The minimum time the data input must remain stable immediately after the
active clock edge.
•Measurement: Time interval from the active clock edge crossing its threshold to the earliest
data signal crossing its threshold.

[Link] Setup and Hold Checks:

•Setup Check: Describes the required timing for data stability before the clock's rising edge.
•Hold Check: Describes the required timing for data stability after the clock's rising edge.
•Two-dimensional tables (rise and fall constraints) describe these timings based on data and
clock transition times.

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 Timing Models - Sequential Cells
Synchronous Checks: Setup and Hold

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Timing Models - Sequential Cells

Synchronous Checks: Setup and Hold

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 Timing Models - Sequential Cells
Synchronous Checks: Setup and Hold

5. Negative Values:
•Negative Hold Time: Occurs when the data path is longer than the clock path, allowing the
data to change before the clock and still meet the hold check.
•Negative Setup Time: Allows the data to change after the clock and still meet the setup time
check.
•Consistency: The sum of setup and hold values must be positive, ensuring the data is stable
for the required duration.

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 Timing Models - Sequential Cells
Synchronous Checks: Setup and Hold

6. Practical Implications:
•Negative Hold Time: Useful in scan mode for testing, providing flexibility and reducing the
need for additional buffers.
•Setup + Hold Time: Represents the total time window during which the data must remain
steady.

7. Application to Asynchronous Pins:

•Similar timing constraint checks are also applied to asynchronous pins, though these are
discussed separately.

In summary, setup and hold checks are crucial for ensuring that data is correctly captured by
sequential cells at the right time relative to the clock signal. They ensure that the timing of
data relative to the clock edge is within acceptable bounds for reliable operation. 45

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 Timing Models - Sequential Cells
Asynchronous Checks

Recovery, Removal, and Pulse Width Checks in Timing Analysis

1. Asynchronous Pins:
•Asynchronous clear/set pins override the synchronous behavior of a cell.
•When active, the output is controlled by the asynchronous pin, not the clock.

2. Recovery and Removal Checks:

•Recovery Time: The minimum time an asynchronous input must be stable after de-assertion
before the next clock edge.
•Removal Time: The minimum time after a clock edge that the asynchronous pin must stay
active before it can be de-asserted.
•These checks ensure the asynchronous pin is stable and inactive before the clock latches the
data. 46

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 Timing Models - Sequential Cells
Asynchronous Checks

Recovery, Removal, and Pulse Width Checks in Timing Analysis

3. Pulse Width Checks:

•Ensures the input pulse width meets the minimum required duration.
•If the clock pulse is too short, it may fail to properly latch data.
•Pulse width checks can be applied to both synchronous and asynchronous pins, for both high
and low pulses.

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 Timing Models - Sequential Cells
Asynchronous Checks

Recovery, Removal, and Pulse Width Checks in Timing Analysis

4. Example Scenario:
•Consider a flip-flop with an asynchronous clear pin (CDN).
•Recovery and Removal Checks:
Focus on the rising edge of the CDN pin concerning the clock pin (CK).
Only rise constraints are defined since these checks are for when the asynchronous pin is
de-asserted.
•Pulse Width Check:
Ensures the low pulse width on the CDN pin meets the minimum requirement.
Since CDN is active low, no high pulse width constraint is specified.

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Timing Models - Sequential Cells

Asynchronous Checks

Recovery, Removal, and Pulse Width Checks in Timing Analysis

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Timing Models - Sequential Cells

Asynchronous Checks

Recovery, Removal, and Pulse Width Checks in Timing Analysis

5. Technical Details:
•The example specifies capacitance and timing constraints for the CDN pin.
•Recovery Timing: Relates to the clock pin (CK) and defines rise constraints based on data
and clock transitions.
•Removal Timing: Also relates to the clock pin and specifies rise constraints for the CDN pin
during de-assertion.

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 Timing Models - Sequential Cells
Propagation Delay

1. Sequential Cell Propagation Delay:

•Delay measured from the active clock edge to the output transition (rising or falling edge).
•Example: Delay from clock pin CKN to output Q in a negative edge-triggered flip-flop.

2. Non-Unate Timing Arc:

•The active clock edge can cause either a rising or falling edge on the output.
•This type of timing arc is called "non-unate."

3. Delay Table Structure:

•Related Pin: The pin related to the timing measurement (e.g., CKN).
•Timing Type: Specifies the active edge (e.g., falling_edge for a negative edge-triggered flip-
flop).
•Timing Sense: Indicates whether the timing arc is non-unate. 51

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Timing Models - Sequential Cells

Propagation Delay

4. Two-Dimensional Delay Tables:

•Delay values are presented in tables with two indices:
 Index 1: Input transition time (e.g., clock transition time).
 Index 2: Output capacitance.
•The table provides delay values for different combinations of these indices.

5. Example Delay Values:

•Delays are shown for different input transition times (e.g., 0.1, 0.3, 0.7) and output
capacitances (e.g., 0.16, 0.35, 1.43).

6. Timing Types:
•Falling Edge-Triggered: Uses falling transition time at the clock pin (CKN).
•Rising Edge-Triggered: Uses rising transition time at the clock pin (CKP). 52

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 Timing Models - Sequential Cells
Propagation Delay

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 Timing Models - Sequential Cells
Propagation Delay

7. Delay Components:
•Cell Rise/Fall: Time for the output to rise or fall after the active clock edge.
•Rise/Fall Transition: Time for the output transition to complete.

8. Application:
•These timing arcs are used to determine how quickly a sequential cell responds to a clock
signal, impacting the overall timing analysis of the circuit.

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 State-Dependent Models
1. State-Dependent Timing:
• Timing arcs between inputs and outputs in combinational blocks can depend on the state
of other pins.
• These timing arcs can be positive unate, negative unate, or both.

2. Example: XOR/XNOR Cells:

• In a two-input XOR cell, the timing from input A1 to output Z is positive unate when A2
is logic-0 and negative unate when A2 is logic-1.
• Different timing models are specified depending on the state of input A2, using state-
dependent models.

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 State-Dependent Models
3. Specification of Timing
Models:
•When Condition: Specifies the
state of a pin (e.g., when A2 is
logic-0 or logic-1) for which the
timing model applies.
•SDF Condition (sdf_cond):
Defines the state used when
generating Standard Delay Format
(SDF) files.

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 State-Dependent Models
3. Specification of Timing
Models:
•When Condition: Specifies the
state of a pin (e.g., when A2 is
logic-0 or logic-1) for which the
timing model applies.
•SDF Condition (sdf_cond):
Defines the state used when
generating Standard Delay Format
(SDF) files.

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 State-Dependent Models
3. Specification of Timing
Models:
•When Condition: Specifies the
state of a pin (e.g., when A2 is
logic-0 or logic-1) for which the
timing model applies.
•SDF Condition (sdf_cond):
Defines the state used when
generating Standard Delay Format
(SDF) files.

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 State-Dependent Models
4. Sequential Cells:
•State-dependent models are also used in sequential cells for setup or hold timing constraints.
•Example: A scan flip-flop might have different timing models for hold constraints
depending on whether the scan enable pin (SE) is active or inactive.

5. Fallback to Non-State-Dependent Models:

•If a state-dependent model doesn't cover a particular condition, the non-state-dependent
model is used.
•For example, if only one state-dependent model is provided for SE at logic-0, and SE is at
logic-1, the non-state-dependent model for the hold constraint is used.

6. State-Dependent Attributes:
•State-dependent models can apply to various attributes in the timing library, including
power, leakage power, transition time, rise and fall delays, and timing constraints.
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 State-Dependent Models
7. Example of Leakage Power:
•State-dependent leakage power can be specified based
on the state of certain pins. For instance:
When A1 is logic-1 and A2 is logic-0, the leakage
power might be 259.8.
When both A1 and A2 are logic-1, the leakage power
might increase to 282.7.

This approach ensures accurate timing analysis by considering different states of the
circuit and how they influence timing behavior.

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 Interface Timing Model for a Black Box
1. Definition:
• The timing model captures the input/output (I/O) interface timings of a black box (an
arbitrary module or block).
• It includes combinational and sequential timing arcs, which can also be state-dependent.

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 Interface Timing Model for a Black Box
2. Types of Timing Arcs:
•Combinational Arc: Direct path from an input to an output, e.g., from input port FIN to
output port FOUT.
•Input Sequential Arc: Setup and hold time requirements for an input connected to a flip-
flop's D-pin, e.g., setup check at port DIN with respect to clock ACLK.
•Asynchronous Input Arc: Similar to recovery or removal timing constraints for
asynchronous pins, e.g., ARST to the asynchronous clear pin of a flip-flop.
•Output Sequential Arc: Clock-to-output propagation delay, e.g., from clock BCLK to the
output port DOUT via flip-flop UFF1.

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 Interface Timing Model for a Black Box
3. Additional Timing Constraints:
•Pulse Width Checks: Ensure the external clock pins have sufficient pulse width.
•Internal Nodes and Generated Clocks: Timing arcs can be defined to/from internal nodes,
and generated clocks can be specified for these nodes.

4. Summary of Timing Arcs in a Black Box:

•Input to Output: For combinational logic paths.
•Setup/Hold Arcs: Between synchronous inputs and related clock pins.
•Recovery/Removal Arcs: For asynchronous inputs related to clock pins.
•Output Propagation Delay: From clock pins to output pins.

5. Purpose:
•This model focuses solely on the timing at the black box's interfaces, not on its internal
timing details.
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 Advanced Timing Modeling
1. NLDM (Non-Linear Delay Model) Overview:
•NLDM models cell delay based on output load capacitance and input transition time.
•Assumes the output load is purely capacitive, which becomes inaccurate when interconnect
resistance (RC) is significant.

2. Effective Capacitance Approach:

•In designs with resistive interconnects, NLDM is adjusted using "effective capacitance" to
better model delays.
•This method approximates the actual delay caused by both resistance and capacitance (RC)
on the output net.

3. Limitations of NLDM:
•As feature sizes shrink, the impact of interconnect resistance becomes more significant,
causing non-linear waveform behavior, leading to inaccuracies in NLDM.
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 Advanced Timing Modeling
4. Advanced Models for Accuracy:
•CCS (Composite Current Source) and ECSM (Effective Current Source Model) are used for
more accurate timing.
•These models use time-varying, voltage-dependent current sources to better represent cell
behavior.

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 Advanced Timing Modeling
Receiver Pin Capacitance

[Link] Pin Capacitance:

•Refers to the capacitance at the input pins of a cell.
•Unlike NLDM, CCS models separate the capacitance for different parts of the transition
waveform (leading vs. trailing).

2. Capacitance at Pin and Timing Arc Levels:

•Capacitance can be specified at:
 Pin level: One-dimensional table for rising/falling waveforms.
 Timing arc level: Two-dimensional table accounting for both input transition time and
output load.

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 Advanced Timing Modeling
Receiver Pin Capacitance

2. Capacitance at Pin and Timing Arc Levels:

•Capacitance can be specified at:
 Pin level: One-dimensional table for rising/falling waveforms.
 Timing arc level: Two-dimensional table accounting for both input transition time and
output load.

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 Advanced Timing Modeling
Receiver Pin Capacitance

3. Capacitance Table Details:

•Tables provide values for receiver capacitance based on conditions like input transition time
and output load.
•Separate values for the leading and trailing portions of rising and falling waveforms (e.g.,
`receiver_capacitance1_rise`, `receiver_capacitance2_rise`).

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 Advanced Timing Modeling
Receiver Pin Capacitance

3. Capacitance Table Details:

•Tables provide values for receiver capacitance based on conditions like input transition time
and output load.
•Separate values for the leading and trailing portions of rising and falling waveforms (e.g.,
`receiver_capacitance1_rise`, `receiver_capacitance2_rise`).

4. Edge Transitions:
•The model accounts for different capacitance behaviors during rising/falling transitions in
the leading and trailing portions.

This more advanced modeling allows for accurate timing predictions, especially in modern
designs with smaller feature sizes and complex interconnects.
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 Advanced Timing Modeling
Output Current in CCS Model

1. Non-linear Timing Representation:

•In the CCS (Composite Current Source) model, non-linear timing is represented by output
current.
•The output current depends on input transition time and output load.

2. Lookup Table Format:

•Output current is specified in a lookup table format.
•The table varies based on combinations of input transition time and output capacitance.

3. Current Waveform:
•The output current waveform shows current values as a function of time.
•For example, for a falling output waveform, `output_current_fall` represents the output
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 Advanced Timing Modeling
Output Current in CCS Model

4. Key Attributes in Lookup Table:

•reference_time: Time when the input
waveform crosses the delay threshold.
•index_1: Input transition time (one specific
value).
•index_2: Output capacitance (one specific
value).
•index_3: Time values at which the output
current is measured.
•values: Corresponding output current
values at different time points.

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 Advanced Timing Modeling
Output Current in CCS Model

5. Current Waveform Interpretation:

•For a given input transition and output capacitance, the table provides the output current
waveform as a function of time.

6. Rising Output Current:

•The same structure applies to rising output waveforms, using `output_current_rise`.

7. Multiple Lookup Tables:

•Additional tables can be used for different combinations of input transition times and output
capacitance values.

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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

[Link] Models Overview:

•CCSN (CCS Noise) models analyze crosstalk noise or glitches in CMOS cells.
•Used to model Channel Connected Blocks (CCBs) within a cell.
•CCBs represent the source-drain channel-connected parts of a cell.

2. Single and Multi-Stage Cells:

•Single-stage cells (e.g., inverters, NAND, NOR) contain one CCB.
•Multi-stage cells (e.g., AND, OR) contain multiple CCBs.

3. First and Last CCBs:

•CCSN models typically focus on the first CCB (driven by the input) and the last CCB
(driving the output).
•These models include steady-state current, output voltage, and propagated noise analysis.73
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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

4. Single-Stage Cell Noise Models:

•For cells like NAND and NOR, noise models are specified for each timing arc.
•These models capture input-to-output behavior, including pull-up and pull-down transitions.

5. Attributes of CCS Noise Models:

•ccsn_first_stage: Refers to the first CCB stage.
•is_needed: True for functional cells.
•stage_type: Specifies the presence of both pull-up and pull-down structures.
•miller_cap_rise / miller_cap_fall: Represent Miller capacitances for rising and falling
transitions.

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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

6. DC Current Tables:
•Show DC current at the output pin for various input and output voltages.
•Example: Input voltage of -0.9V and output voltage of 0V gives a current of 0.42mA.

7. Output Voltage (Rise and Fall):

•Output rise and fall voltages are represented in multi-dimensional tables.
•Tables include data for different input transition rates and output capacitances.

8. Propagated Noise Models:

•Represent crosstalk glitch (noise) propagation through the CCB.
•Multi-dimensional tables include input glitch magnitude, width, capacitance, and time.

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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

9. Noise Models for Multi-Stage Cells:

•In two-stage cells (e.g., AND, OR), noise models are specified separately for the first and
last CCB stages.
•Noise propagation is analyzed through both stages.

10. Sequential and Complex Cells:

•CCSN models for complex combinational or sequential cells are often part of pin
specifications.
•Some models may be included in the timing arc for multi-stage cells.

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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

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 Advanced Timing Modeling
Models for Crosstalk Noise Analysis

11. Example of Flip-Flop CCS Noise Model:

•Flip-flop cells may have noise models at input pins (ccsn_first_stage) and output pins
(ccsn_last_stage).
•Models can be defined in both the pin description and timing group.

Key Takeaways:
•CCSN models analyze crosstalk noise and glitches in CMOS circuits.
•These models focus on first and last stages of Channel Connected Blocks.
•Single-stage cells have simpler models, while multi-stage cells require more detailed
analysis across stages.
•Multi-dimensional tables represent various parameters like voltage, capacitance, and timing
for noise analysis.
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 Advanced Timing Modeling
Other Noise Models

1. CCS Noise Models:

•Commonly used for characterizing noise in cell libraries.
•Older noise models were used before CCS noise models but are not needed if CCS models
are available.

2. DC Margin Model:
•Defines the largest DC voltage variation at the input pin that won’t affect the output.
•DC Margin for Input Low: Maximum input low voltage without causing a transition at the
output.

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 Advanced Timing Modeling
Other Noise Models

3. Noise Immunity Models:

•Specify the maximum glitch magnitude that can be tolerated at the input pin without
propagating to the output.
•Presented in two-dimensional tables, using glitch width and output capacitance as indices.
•A glitch smaller than the specified magnitude and width will not affect the output.

4. Types of Noise Immunity Models:

•noise_immunity_high: Defines tolerance for larger glitches.
•noise_immunity_low: Defines tolerance for smaller glitches.
•noise_immunity_above_high: Refers to overshoot immunity (voltage above the high
threshold).
•noise_immunity_below_low: Refers to undershoot immunity (voltage below the low
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 Power Dissipation Modeling
1. Types of Power Dissipation:
•Active Power: Power consumed when the cell is actively switching.
•Standby (Leakage) Power: Power consumed when the cell is idle due to leabkage currents.

2. Active Power Components:

•Output Switching Power: Depends on output capacitive load, switching frequency, and
power supply.
•Internal Switching Power: Consumed within the cell during input/output transitions,
specified in the cell library as "internal power."

3. Internal Power Specification:

•Internal power is measured for each transition (rise or fall) at input/output pins.
•Described using tables (e.g., input transition at a pin and output capacitance).

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 Power Dissipation Modeling

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 Power Dissipation Modeling
4. Power Pin and Ground Pin Specification:
•Cell libraries define power (‘VDD’) and ground (‘VSS’) pins along with power-down
functions that manage multiple power supplies.

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 Power Dissipation Modeling
5. Sequential Cell Power Dissipation:
•Flip-flops and sequential cells dissipate power during clock transitions, even if the outputs
do not switch.
•Power due to clock pin toggling is specified separately to avoid double counting.

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 Power Dissipation Modeling

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 Power Dissipation Modeling
6. Leakage Power:
•Leakage Sources: Comes from subthreshold current and gate oxide tunneling in MOS
devices.
•Significant in advanced process nodes (e.g., 65nm or below).
•Cells are designed with trade-offs between speed (low V t = faster but more leakage) and
power consumption (high Vt = slower but less leakage).

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 Power Dissipation Modeling
8. Design Trade-offs:
•Designers balance between speed, leakage, and power by selecting cell strengths and voltage
thresholds (Vt).

By specifying active and leakage power in cell libraries, designers can optimize power usage
in complex digital circuits.

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 Other Attributes in Cell Library
1. Area Specification:
• Describes the area occupied by the cell or cell group.
• Example: ‘area : 2.35;’ represents 2.35 area units, either as actual silicon area or a relative
measure.

2. Function Specification:
• Specifies the logic functionality of a cell pin.
• Example: ‘pin (Z) { function: "IN1 & IN2"; }’ means pin Z behaves as a two-input AND
gate.

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 Other Attributes in Cell Library
3. SDF Condition (Standard Delay Format):
•Supports timing backannotation during SDF file generation.
•Specifies conditions for state-dependent timing usage.
•Example:
- ‘when : "!A2";’ sets a condition for timing analysis (when A2 is not true).
- ‘sdf_cond : "A2 == 1'b0";’ matches the condition during SDF annotation (A2 is 0).

4. Timing Sense:
•Describes how input changes affect output timing.
•Example: ‘timing_sense : positive_unate;’ means a rising input causes a rising output.

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 Characterization and Operating Conditions
1. Library Characterization:
•Each cell library is characterized based on nominal environmental conditions such as
process, temperature, and voltage.
•Example:
- Nominal process = 1.
- Nominal temperature = 0°C.
- Nominal voltage = 1.1V.

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 Characterization and Operating Conditions
2. Operating Conditions:
•Specifies the actual conditions under which the library cells will be used.
•If different from characterization conditions, timing values must be adjusted.

3. Derating Factors:
•Used to adjust (derate) timing values when operating and characterization conditions differ.
•Involves using "k-factors" for derating, which introduces inaccuracies.
•Derating is used when it's not feasible to characterize at specific conditions.

4. Process Variable:
•Unlike temperature or voltage, process is not a physical quantity.
•Process is typically classified as slow, typical, or fast.
•The process value (e.g., 1.0) allows timing calculation for different process corners.

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 Characterization and Operating Conditions
5. Library Characterization and Process:
•Characterizing for multiple process corners is time-consuming.
•Process derating adjusts delays for different corners but is rarely used due to its inaccuracy.

6. Summary of Process Derating:

•Process derating is a method to approximate timing for different process conditions.
•It introduces inaccuracies and is seldom employed. The main purpose of process values is to
allow such approximations when needed.

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 Characterization and Operating Conditions
Derating using K-factors

[Link] of K-factors:
•K-factors are used to adjust delays when operating conditions differ from those at which the
design was characterized.
•They provide an approximate method for calculating delays under varying process, voltage,
and temperature (PVT) conditions.

2. Example K-factors:
•Examples include factors for cell fall, cell rise, hold times, setup times, wire capacitance,
etc.
•K-factors for temperature (k_temp), voltage (k_volt), and process (k_process) conditions are
specified in a library.

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 Characterization and Operating Conditions
Derating using K-factors

3. Impact of Conditions:
•Voltage (k_volt): Negative k_volt factors indicate that delays decrease as voltage increases.
•Temperature (k_temp): Positive k_temp factors indicate that delays increase as temperature
rises (unless temperature inversion occurs).

4. Derating Formula:
•The derated delay is calculated as:
Result with derating = Original value * (1 + k_process * DELTA_Process
+ k_volt * Delta_Volt + k_temp * Delta_Temp)

⁃Where Delta_Process, Delta_Volt, and Delta_Temp represent deviations from nominal

conditions.
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 Characterization and Operating Conditions
Derating using K-factors

5. Example Calculation:
•If a library is characterized at 1.08V and 125°C, and you need to calculate the delay at
1.14V and 100°C:
⁃Derated_delay = Library_delay * ( 1 + k_volt_cell_rise * 0.06 - k_temp_cell_rise * 25)
⁃Derated delay = Library delay * (1 - 0.42 *0.06 - 0.0012 * 25)
•This results in a derated delay of approximately 94.48% of the original library delay.

6. Summary:
•K-factors allow adjustments to timing delays based on changes in process, voltage, and
temperature.
•The formula applies multiplicative corrections to account for environmental variations.

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 Characterization and Operating Conditions
Library Units

1. Definition of Library Units:

•All cell descriptions use standardized units declared in the library file.
•These units define measurements for voltage, time, capacitance, resistance, etc.

2. Liberty Command Set:

•Units are declared using the Liberty format, as shown in the example:
- Voltage: ‘voltage_unit : "1V";’
- Time: ‘time_unit : "1ns";’
- Capacitance: ‘capacitive_load_unit (1.000000, pf);’
- Current: ‘current_unit : 1mA;’
- Resistance: ‘pulling_resistance_unit : "1kohm";’

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 Characterization and Operating Conditions
Library Units

3. Assumed Units in Discussion:

•Time: Nanoseconds (ns).
•Voltage: Volts (V).
•Internal Power: Picojoules (pJ) per transition.
•Leakage Power: Nanowatts (nW).
•Capacitance: Picofarads (pF).
•Resistance: Kilo-ohms (KΩ).
•Area: Square microns (μm²).

4. Default Unit Assumptions:

•The mentioned units are assumed throughout unless specifically changed for a particular
explanation.
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