EC 304 - VLSI
Module VI
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Module IV
Adders-
Static adder,
Carry-By pass adder
Linear Carry Select adder
Square- root carry- select adder
Multipliers-Array multiplier
3 Static Adder
Full Adder
Accepts 3 inputs (A, B, Cin) and produces
outputs Sum and Cout
A B Cin Cout Sum BCin Sum
0 0 0 0 0 A 00 01 11
0 0 1 0 1 0 100 1 0 1
1 1 0 1 0
0 1 0 0 1
0 1 1 1 0 S = A’B’Cin + A’BCin’ + AB’ Cin’ +ABCin
1 0 0 0 1 = A B Cin
BCin Carry
1 0 1 1 0 A 00 01 11 10
1 1 0 1 0 0 0 0 1 0
1 1 1 1 1 1 0 1 1 1
Cout = A’BCin + AB’Cin + AB Cin’ +ABCin
4 = AB + BCin + ACin
Truth Table with carry status
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A=B=0
Cout = 0
A=1 OR B=1
THEN
Cout=Cin
A=B=1
Cout = 1
Three new variables are defined G, P D
Generate (G)
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Propagate(P)
Delete(D)
G=1 ensures that a carry bit will be generated independent of Ci
D=1 ensures that a carry bit will be deleted independent of C i
P=1 ensures that an incoming carry will be propagated to Co
S = A’B’Cin + A’BCin’ + AB’ Cin’ +ABCin
Cout = A’BCin + AB’Cin + AB Cin’ +ABCin
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After Applying the inverting property
=AB+
(A+B)Ci
The static CMOS Adder using the above expression is implemented
28 transistors are required for this implementation
Static CMOS implementation of Full-Adder
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=Co`
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RIPPLE CARRY ADDER
The basic circuit for realizing the adder arithmetic is the full
adder, a combinational circuit with 3 inputs and 2 outputs.
N bit adder can be constructed by cascading N full adder
circuit in series, connecting Co,k-1 to Ci,k for k=1 to N -1
This configuration is called ripple carry adder, since the carry
bit ripples from one stage to another i.e from LSB to MSB
Propagation delay of ripple carry adder is linearly
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proportional to N.
So when designing a full adder for a fast ripple carry
adder optimize tcarry and tsum
The linear dependency of Ripple carry Adder make it
impractical. Consider the worst case delay
Eg.
Cin=0
0 0 0 0 0 0 0 1+
1 1 1 1 1 1 1 1
10 0 0 0 0 0 0 0
1 1 1 1 Cout=1
1 1
The delay through the circuit depends upon the no: of logic
12 stage and applied input signals
Carry has to ripple from LSB to MSB
tadder = (N-1) tcarry +tsum
tcarry = propagation delay from Ci to Co
tsum = propagation delay from Ci to S
Eg. When tcarry = tsum=1 sec, N=16, Then adder has to wait
for 16 seconds to obtain output
Conclusion
Propagation delay of ripple carry adder is linearly
proportional to N.
So when designing a full adder for a fast ripple carry adder
optimize tcarry and tsum
13 Ripple Carry Adder
Longest delay (Worst case delay) example
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Cout =1
Cin=0
0 0 0 0 0 0 0 1+
1 1 1 1 1 1 1 1 P-> Propagate
1 0 0 0 0 0 0 0 0 A=1 OR B=1
P3=1 P0=0
P2=1 P1=1
P0=0, P1= P2= P3= 1,
BP =P0P1P2P3 ≠1 In this case carry is generated
Longest delay (Worst case delay) example
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Cin=1
Cout =1
0 0 0 0 0 0 0 1+
1 1 1 1 1 1 1 1 P-> Propagate
1 0 0 0 0 0 0 0 0 A=1 OR B=1
P3=1 P0=1
P2=1 P1=1
P0= P1= P2= P3= 1,
BP =P0P1P2P3 =1 , Then carry is bypassed
ie. Cin=Cout, No need to carry ripple, only carry bypass.
Carry-Bypass /Carry Skip Adder
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Carry Bypass Adder (N=16)
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N – No. of bits(16)
M- No. of bits in each bypass stage (4)
The worst case delay path is shaded in gray
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tcarry=the propagation delay through a single bit. The worst case
carry-propagation delay through a single stage of M bits is
approximately M times larger
tsetup= the fixed overhead time to create the generate and propagate
signals
tbypass=the propagation delay through the bypass multiplexer of a
single stage
tsum=the time to generate the sum of the final stage
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0000 0000 0000 0001 +
0111 1111 1111 1111
21 Problem
Determine an input pattern that triggers the worst case delay in a 16-bit
(4 x 4) carry bypass adder. Assume that tcarry=tsetup=tbypass=tsum=1,
determine
Delay
Compare the delay with ripple carry adder
Answer Click here
23 Delay Comparison
Linear Carry Select Adder
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Critical Path of Carry Select Adder
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Propagation delay
tadd=tsetup+Mtcarry+(N/M)tmux+tsum
Problem:
Determine the delay of a 16-bit linear carry select adder by
using unit delays for all cells
Drawback of carry select adder
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(5) (5) (5)
(5) (6) (7) (8)
Square root carry select adder
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2 bits 3 bits 4 bits 5 bits
(3) (4) (5) (6) (7)
(4) (5) (6) (7)
(8)
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M – No. of bits in first stage
N – Total number of bits
Delay Comparison
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Multiplication
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Multiplier
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Multiplication of two 4-bit numbers
Add these bits, Half
Add carry from previous adder is used
HA and 3 bits, Hence a FA
and HA is used (Add a2bo &
a1bo and Carry from HA
Check the
using FA)(Sum from FA
remaining
and a0b2 is added using HA)
combinations and
refer to the next
figure
Partial products
4 bits and cout of 2 adders(FA & HA of previous
stage..)hence to 2 FA and one HA are required
Array Multiplier
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