UNIT IV–

PROCESSOR
Instruction Execution – Building a Data Path – Designing a
Control Unit – Hardwired Control, Microprogrammed Control
– Pipelining.
 Instruction Execution

Basic Instruction Cycle Basic Instruction Cycle

with Interrupt
 A BASIC MIPS
IMPLEMENTATION
An Overview of the
Implementation
The memory-reference instructions load word (lw) and store
word (sw)
The arithmetic-logical instructions add, sub, AND, OR, and slt
The instructions branch equal (beq) and jump (j)
The basic implementation of
the MIPS subset, including
the necessary multiplexors
and control lines
Building Data path
Two state elements are needed to store and
access instructions, and an adder is needed
to compute the next instruction address
 path used for fetching
instruction and
incrementing the
A portion of the data path used for fetching instructions and incrementing the
program counterprogram counter
 Cont..
The two elements needed to implement R-format ALU operations are the register
file and the ALU
Data path elements for branches:
Branch taken
Branch not taken or (untaken branch)
 Designing Control Unit
ALU control:
ALU CONTROL
 ALU control inputs
based on the 2-bit
ALUOp control and the
6-bit function code

ALUOp indicates whether the operation to be performed:

 00- add for loads and stores,
 01- subtract for beq,
 10- determined by the operation encoded in the funct field.
 The output of the ALU control unit is a 4-bit signal that directly controls the
ALU by generating one of the 4-bit combination
DESIGNING THE MAIN
CONTROL UNIT
 DESIGN OF MAIN
CONTROL UNIT
3 Instruction classes formats are given below
Setting of the Control
lines
 Hardwired Control Unit
• An instruction is executed in a sequence of steps, each
requiring one clock cycle.
• Hence, a step counter may be used to keep track of the
progress of execution.
• Several actions are performed in each step, depending on the
instruction being executed. In some cases, such as for branch
instructions, the actions taken depend on tests applied to the
result of a computation or a comparison operation.
• External signals, such as interrupt requests, may also influence
the actions to be performed.
 Setting of the Control
Signals
It depends on:
• Contents of the step counter
• Contents of the instruction register
• The result of a computation or a comparison operation
• External input signals, such as interrupt requests
Generation of Control
Signals
 CONTROL SIGNALS:DATA PATH

• In each colck cycle, the results of actions in one stage are

stored in inter-stage registers.
- Available for use by the next stage in the next clock cycle.
• Since data are transferred from one stage to the next in every
clock cycle, inter stage registers are always enabled.
-This is the case for registers RA,RB,RZ,RY,andRM.
-The contents of the other registers PC,IR and register file
must not be changed in every clock cycle. New data are
loaded into these registers only when called for in a particular
processing step and they must be enabled only at those
times.
Datapath Control Signal
 Processor-to-Memory
Interface and IR Control
Signals
 Microprogrammed Control
• Control signals are generated for each execution step based on the
instruction in the IR.
• In hardwired control, these signals are generated by circuits that
interpret the contents of the IR as well as the timing signals derived
from a step counter.
• Instead of employing such circuits, it is possible to use a “software"
approach, in which the desired setting of the control signals in each
step is determined by a program stored in a special memory.
• The control program is called a microprogram to distinguish it from
the program being executed by the processor.
• The microprogram is stored on the processor chip in a small and
fast memory called the microprogram memory or the control store.
Microprogrammed control
unit organization
 Pipelining

Pipelining is an implementation technique in which multiple

instructions are overlapped in execution. Today, pipelining
is nearly universal.

(a) Laundry Analogy- Normal Method

 Pipeline in
processor
Single-cycle, non pipelined execution in top versus
pipelined execution in bottom.
Pipeline data path and
control
 Handling data hazards
and control
Pipeline Hazards:
hazards
Situations in pipelining when the next instruction cannot execute in
the following clock cycle.
These events are called hazards, and there are three different types.
Structural hazard
Data hazard
Control hazard
 Structural Hazard
 It means that the hardware cannot support the combination
of instructions that we want to execute in the same clock
cycle
 Data Hazard

There are some solutions to rectify data hazard. They are

Forwarding or Bypassing
Hazard detection unit
Reordering code to avoid pipeline stalls
Hazard detection by software
 Forwarding or Bypassing
Adding extra hardware to retrieve the missing item early from
the internal resources is called forwarding or bypassing
Forwarding works very well but cannot prevent all pipeline stalls,
however.

Even with forwarding, we would have to stall one stage for a load-
use data hazard

Pipeline stall, is often given the nickname bubble

 Data Hazards:
Forwarding versus
Stalling
 Data hazards arise when an instruction depends on the
results of an previous instruction in a way that is exposed
by the overlapping of instructions in the pipeline
Using the notation given
below , the two pairs of
hazard conditions are
given as
Conditions for detecting
hazards and the control
signals to resolve them:
Data Hazards and Stalls
if (ID/[Link] and
((ID/[Link] = IF/[Link]) or
(ID/[Link] = IF/[Link])))
Hazard Detection Unit
 Control hazard

Control hazard is also called branch hazard. When the proper

instruction cannot execute in the proper pipeline clock cycle
because the instruction that was fetched is not the one that is
needed; that is, the flow of instruction addresses is not what
the pipeline expected
 We use simpler
schemes
1. Assume Branch Not Taken
2. Assume Branch is taken
 Reducing the Delay of
Branches
 One way to improve branch performance is to reduce the cost
of the taken branch
 The MIPS architecture was designed to support fast single-
cycle branches that could be pipelined with a small branch
penalty
 Moving the branch decision up requires two actions to occur
earlier: computing the branch target address and
evaluating the branch decision
 Dynamic Branch
Prediction
 Assuming a branch is not taken is one simple form of branch
prediction
 One approach is to look up the address of the instruction to see if a
branch was taken the last time this instruction was executed and, if
so, to begin fetching new instructions from the same place as the
last time. This technique is called dynamic branch prediction
 One implementation of that approach is a branch prediction buffer
or branch history table
 Implementation of
branch prediction buffer
There are three schemes to dynamic branch prediction.
Simple 1-bit prediction scheme

2-bit prediction scheme

Tournament predictor