Registers and Counters

Part-1

Dr Jasdeep Kaur Dhanoa

Professor
Department of E & C Engineering
Contents

• Combinational and Sequential circuits

• Shift registers
• Ripple counter
• Design of Synchronous counters
• Sequence Detectors and Sequence Generators
• One flip-flop can store one-bit of information. In order to store multiple bits of information, we require
multiple flip-flops. The group of flip-flops, which are used to hold/ store the binary data is known as register.

• A register capable of shifting its binary information in one or both direction is called a shift register.
• All flip-flops receive common clock pulses, which activate the shift from one stage to the next.
• The simplest possible shift register is one that uses only flip-flops,

• If the register is capable of shifting bits either towards right hand side or towards left hand side is known
as shift register. An ‘N’ bit shift register contains ‘N’ flip-flops.

• The four types of shift registers based on applying inputs and accessing of outputs.
 Serial In − Serial Out shift register
 Serial In − Parallel Out shift register
 Parallel In − Serial Out shift register
 Parallel In − Parallel Out shift register
 Serial In − Serial Out SISO Shift Register

• The shift register, which allows serial input and produces serial output is known as Serial In – Serial
Out SISO shift register. The block diagram of 3-bit SISO shift register is shown in the following figure.

figure.

• This block diagram consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is
connected as the input of next D flip-flop. All these flip-flops are synchronous with each other since, the same
clock signal is applied to each one.
• In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also
called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the
next. So, we can receive the bits serially from the output of right most D flip-flop. Hence, this output is also
called as serial output.
Analysis:
Working of 3-bit SISO shift register by sending the binary information “011” from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000. We can understand the working
of 3-bit SISO shift register from the following table.
The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000Q2Q1Q0=000. Here, the serial
output is coming from Q0. So, the LSB 1 is received at 3 rd positive edge of clock and the MSB 0 is received at
5th positive edge of clock.
Therefore, the 3-bit SISO shift register requires five clock pulses in order to produce the valid output. Similarly, the N-
bit SISO shift register requires 2N-1 clock pulses in order to shift ‘N’ bit information.

No of positive edge of Serial Q2 Q1 Q0

Clock Input
0 - 0 0 0
1 1 LSB 1 0 0
2 1 1 1 0
3 0 MSB 0 1 1 LSB
4 - - 0 1
5 - - - 0 MSB
 Serial In - Parallel Out SIPO Shift Register
The shift register, which allows serial input and produces parallel output is known as Serial In – Parallel Out SIPOSIPO shift
register. The block diagram of 3-bit SIPO shift register is shown in the following figure.

figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the
input of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each
one.
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called
as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. In this case, we
can access the outputs of each D flip-flop in parallel. So, we will get parallel outputs from this shift register.
Analysis
Working of 3-bit SIPO shift register by sending the binary information “011” from LSB to MSB serially at the input.
Assume, initial status of the D flip-flops from leftmost to rightmost is Q2Q1Q0=000. Here, Q2 & Q0 are MSB & LSB
respectively. We can understand the working of 3-bit SIPO shift register from the following table.

No of positive edge of Serial Input Q2 MSB Q1 Q0 LSB

Clock

0 - 0 0 0

1 1 LSB 1 0 0

2 1 1 1 0

3 0 MSB 0 1 1

The initial status of the D flip-flops in the absence of clock signal is Q2Q1Q0=000. The binary information “011” is obtained in
parallel at the outputs of D flip-flops for third positive edge of clock.
So, the 3-bit SIPO shift register requires three clock pulses in order to produce the valid output. Similarly, the N-bit SIPO shift
register requires N clock pulses in order to shift ‘N’ bit information.
 Parallel In − Serial Out PISO Shift Register
The shift register, which allows parallel input and produces serial output is known as Parallel In − Serial Out PISOPISO shift
register. The block diagram of 3-bit PISO shift register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded. That means, output of one D flip-flop is connected as the input
of next D flip-flop. All these flip-flops are synchronous with each other since, the same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge
triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D
flip-flop.
Analysis
Working of 3-bit PISO shift register by applying the binary information “011” in parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops from leftmost to
rightmost will be Q2Q1Q0=011. We can understand the working of 3-bit PISO shift register from the following
table.

No of positive edge of Clock Q2 Q1 Q0

0 0 1 1 LSB
1 - 0 1
2 - - 0 LSB

Here, the serial output is coming from Q0. So, the LSB 1 is received before applying positive edge of clock and the MSB 0 is
received at 2nd positive edge of clock.
Therefore, the 3-bit PISO shift register requires two clock pulses in order to produce the valid output. Similarly, the N-bit PISO
shift register requires N-1 clock pulses in order to shift ‘N’ bit information.
Parallel In - Parallel Out PIPO Shift Register
The shift register, which allows parallel input and produces parallel output is known as Parallel In − Parallel Out PIPO shift
register. The block diagram of 3-bit PIPO shift register is shown in the following figure.

This circuit consists of three D flip-flops, which are cascaded.

That means, output of one D flip-flop is connected as the input
of next D flip-flop. All these flip-flops are synchronous with
each other since, the same clock signal is applied to each one.
In this shift register, we can apply the parallel inputs to each D
flip-flop by making Preset Enable to 1.

We can apply the parallel inputs through preset or clear. These

two are asynchronous inputs. That means, the flip-flops
produce the corresponding outputs, based on the values of
asynchronous inputs. In this case, the effect of outputs is
independent of clock transition. So, we will get the parallel
outputs from each D flip-flop.
 Analysis
Working of 3-bit PIPO shift register by applying the binary information “011” in parallel through preset inputs.
Since the preset inputs are applied before positive edge of Clock, the initial status of the D flip-flops from
leftmost to rightmost will be Q2Q1Q0=011. So, the binary information “011” is obtained in parallel at the
outputs of D flip-flops before applying positive edge of clock.
Therefore, the 3-bit PIPO shift register requires zero clock pulses in order to produce the valid output. Similarly,
the N-bit PIPO shift register doesn’t require any clock pulse in order to shift ‘N’ bit information.

Following are the applications of shift registers.

•Shift register is used as Parallel to serial converter, which converts the parallel data into serial data. It is
utilized at the transmitter section after Analog to Digital Converter ADC block.
•Shift register is used as Serial to parallel converter, which converts the serial data into parallel data. It is
utilized at the receiver section before Digital to Analog Converter DAC block.
•Shift register along with some additional gates generate the sequence of zeros and ones. Hence, it is used
as sequence generator.
•Shift registers are also used as counters. There are two types of counters based on the type of output from
right most D flip-flop is connected to the serial input. Those are Ring counter and Johnson Ring counter.
 Counters

• A register that goes through a prescribed sequence of states upon the application of input pulse is called a counter.
• A counter that follows the binary number sequence is called a binary counter.
• Counters are available in two categories
 Ripple counters
 Synchronous counters
A ring counter is a circular shift register with only one flip-flop being set at any particular time, all
others are cleared.
The single bit is shifted from one flip-flop to the next to produce the sequence of timing signals.
The decoder shown in decodes the four states of the counter and generates the required
sequence of timing signals.