CMOS IC FABRICATON
CMOS
Step 1: First we choose a substrate as a base for fabrication.
For N- well, a P-type silicon substrate is selected.
Step 2 - Oxidation: The selective diffusion of n-type
impurities is accomplished using SiO2 as a barrier which
protects portions of the wafer against contamination of the
substrate. SiO2 is laid out by oxidation process done exposing
the substrate to high-quality oxygen and hydrogen in an
oxidation chamber at approximately 10000c
Step 3 - Growing of Photo resist: At this stage to permit the
selective etching, the SiO2 layer is subjected to the
photolithography process. In this process, the wafer is coated
with a uniform film of a photosensitive emulsion.
Step 4 – Masking: This step is the continuation of the
photolithography process. In this step, a desired pattern of
openness is made using a stencil. This stencil is used as a mask
over the photo resist. The substrate is now exposed to UV
rays the photo resist present under the exposed regions of
mask gets polymerized
Step 5 – Removal of Unexposed Photo resist: The mask is
removed and the unexposed region of photo resist is dissolved
by developing wafer using a chemical such as
Trichloroethylene.
Step 6 – Etching: The wafer is immersed in an etching
solution of hydrofluoric acid, which removes the oxide from
the areas through which dopants are to be diffused.
Step 7 – Removal of Whole Photoresist Layer: During
the etching process, those portions of SiO2 which are protected
by the photoresist layer are not affected. The photoresist mask is
now stripped off with a chemical solvent (hot H2SO4).
Step 8 – Formation of N-well: The n-type impurities are
diffused into the p-type substrate through the exposed region
thus forming an N- well.
Step 9 – Removal of SiO2: The layer of SiO2 is now
removed by using hydrofluoric acid.
Step 10 – Deposition of Polysilicon: The misalignment of the
gate of a CMOS transistor would lead to the unwanted
capacitance which could harm circuit. So to prevent this “Self-
aligned gate process” is preferred where gate regions are
formed before the formation of source and drain using ion
implantation.
Polysilicon is used for formation of the gate because it can
withstand the high temperature greater than 80000c when a wafer
is subjected to annealing methods for formation of source and
drain.
Polysilicon is deposited by using Chemical Deposition
Process over a thin layer of gate oxide.
This thin gate oxide under the Polysilicon layer prevents further
doping under the gate region.
Step 11 – Formation of Gate Region: Except the two regions
required for formation of the gate for NMOS and PMOS
transistors the remaining portion of Polysilicon is stripped
off.
Step 12 – Oxidation Process: An oxidation layer is
deposited over the wafer which acts as a shield for
further diffusion and metallization processes.
Step 13 – Masking and Diffusion: For making regions for
diffusion of n-type impurities using masking process small
gaps are made.
Using diffusion process three n+ regions are developed
for the formation of terminals of NMOS.
Step 14 – Removal of Oxide: The oxide layer is stripped off.
Step 15 – P-type Diffusion: Similar to the n-type diffusion
for forming the terminals of PMOS p-type diffusion are
carried out.
Step 16 – Laying of Thick Field oxide: Before forming the
metal terminals a thick field oxide is laid out to form a
protective layer for the regions of the wafer where no terminals
are required.
Step 17 – Metallization: This step is used for the formation
of metal terminals which can provide interconnections.
Aluminum is spread on the whole wafer.
Step 18 – Removal of Excess Metal: The excess metal is
removed from the wafer.
Step 19 – Formation of Terminals: In the gaps formed after
removal of excess metal terminals are formed for the
interconnections.
Step 20 – Assigning the Terminal Names: Names are
assigned to the terminals of NMOS and PMOS transistors.
Twin tub-CMOS Fabrication Process
In this process, separate optimization of the n-type and p-type
transistors will be provided. The independent optimization of Vt,
body effect and gain of the P-devices, N-devices can be made
possible with this process.
STEPS:
Lightly doped n+ or p+ substrate is taken and, to
protect the latch up(low impedance path between vdd
to ground), epitaxial layer is used.
The high-purity controlled thickness of the layers of
silicon are grown with exact dopant concentrations.
The dopant and its concentration in Silicon are used to
determine electrical properties.
Formation of the tub
Thin oxide construction
Implantation of the source and drain
Cuts for making contacts
Metallization
UNIT-III