Computer Architecture
and Organization
Module 1.3 – Computer Performance
The Second Generation -
Transistors
• The transistor is smaller, cheaper, and dissipates less heat than a
vacuum tube but can be used in the same way as a vacuum tube to
construct computers.
• Unlike the vacuum tube, which requires wires, metal plates, a glass
capsule, and a vacuum, the transistor is a solid-state device, made
from silicon.
• The transistor was invented at Bell Labs in 1947 and by the 1950s had
launched an electronic revolution.
• It was not until the late 1950s, however, that fully transistorized
computers were commercially available.
What are solid state devices?
• They are electronic devices in which electricity flows through solid
semiconductor crystals (silicon, gallium arsenide, germanium) rather
than through vacuum tubes.
The Third Generation –
Integrated Circuits
• A single, self-contained transistor is called a discrete component.
• Throughout the 1950s and early 1960s, electronic equipment was composed
largely of discrete components—transistors, resistors, capacitors, and so on.
• Discrete components were manufactured separately, packaged in their own
containers, and soldered or wired together onto masonite-like circuit boards,
which were then installed in computers, oscilloscopes, and other electronic
equipment.
• Whenever an electronic device called for a transistor, a little tube of metal
containing a pinhead-sized piece of silicon had to be soldered to a circuit
board. The entire manufacturing process, from transistor to circuit board,
was expensive and cumbersome.
Later Generations
• SSI – Small Scale Integration
• LSI – Large Scale Integration – more than 1,000 components
• VLSI – Very Large Scale Integration – more than 10,000 components
• ULSI – Ultra Large Scale Integration – more than 1,000,000 components
• Monolithic IC – built on a single stone or crystal
• Thin and Thick Film IC – larger than monolithic but smaller than discrete IC.
Used with higher power requirements. Passive components are integrated
but discrete components are connected to form circuits.
• Hybrid IC – an interconnections of several individual chips
Later Generations
• SEMICONDUCTOR MEMORY. Although the first application of IC’s in
computers was construction of the processor (the control unit and
the arithmetic and logic unit), it was also found that it could be used
to construct memories.
• MICROPROCESSORS. A breakthrough was achieved in 1971, when
Intel developed its [Link] 4004 was the first chip to contain all of
the components of a CPU on a single chip
Designing for Performance
1. Microprocessor Speed
• Branch prediction: The processor looks ahead in the instruction code fetched from
memory and predicts which branches, or groups of instructions, are likely to be
processed next. If the processor guesses right most of the time, it can prefetch the
correct instructions and buffer them so that the processor is kept busy.
• Data flow analysis: The processor analyzes which instructions are dependent on each
other’s results, or data, to create an optimized schedule of instructions. In fact,
instructions are scheduled to be executed when ready, independent of the original
program order. This prevents unnecessary delay.
• Speculative execution: Using branch prediction and data flow analysis, some
processors speculatively execute instructions ahead of their actual appearance in the
program execution, holding the results in temporary locations. This enables the
processor to keep its execution engines as busy as possible by executing instructions
that are likely to be needed.
Designing for Performance
• Performance Balance - adjusting of the organization and architecture to
compensate for the mismatch among the capabilities of the various
components.
• Increase the number of bits that are retrieved at one time by making DRAMs “wider”
rather than “deeper” and by using wide bus data paths.
• Change the DRAM interface to make it more efficient by including a cache or other
buffering scheme on the DRAM chip.
• Reduce the frequency of memory access by incorporating increasingly complex and
efficient cache structures between the processor and main memory. This includes the
incorporation of one or more caches on the processor chip as well as on an off-chip
cache close to the processor chip.
• Increase the interconnect bandwidth between processors and memory by using
higher-speed buses and by using a hierarchy of buses to buffer and structure data flow.
Types of DRAM
• Synchronous DRAM (SDRAM) syncs memory speeds with CPU clock speeds,
letting the memory controller know the CPU clock cycle. This enables the CPU to
perform more instructions at a time.
• Rambus DRAM was more widely used in the early 2000s for graphics cards.
• Double Data Rate SDRAM (DDR SDRAM) almost doubles the bandwidth in data
rate of SDRAM by using double pinning. This process allows for data to transfer on
rising and falling edges of a clock signal. It has been available in different iterations
over time, including DDR2 SDRAM, DDR3 SDRAM and DDR4 SDRAM.
• Fast Page Mode DRAM gives higher performance than other DRAM types through
focusing on fast page access.
• Extended Data Out DRAM improves the time to read from memory on
microprocessors, such as Intel Pentium.
Designing for Performance
3. Improvements in Chip Organization and Architecture
• Increase the hardware speed of the processor. This increase is fundamentally due to
shrinking the size of the logic gates on the processor chip, so that more gates can be
packed together more tightly and to increasing the clock rate. With gates closer
together, the propagation time for signals is significantly reduced, enabling a speeding
up of the processor. An increase in clock rate means that individual operations are
executed more rapidly.
• Increase the size and speed of caches that are interposed between the processor
and main memory. In particular, by dedicating a portion of the processor chip itself to
the cache, cache access times drop significantly.
• Make changes to the processor organization and architecture that increase the
effective speed of instruction execution. Typically, this involves using parallelism in
one form or another.
Obstacles faced when improving
chip performance
• Power: As the density of logic and the clock speed on a chip increase, so
does the power density (Watts/cm2 ). The difficulty of dissipating the heat
generated on high-density, high-speed chips is becoming a serious design
issue.
• RC delay: The speed at which electrons can flow on a chip between
transistors is limited by the resistance and capacitance of the metal wires
connecting them; specifically, delay increases as the RC product increases. As
components on the chip decrease in size, the wire interconnects become
thinner, increasing resistance. Also, the wires are closer together, increasing
capacitance.
• Memory latency: Memory speeds lag processor speeds, as previously
discussed.
Activity
• Reporting Assignment
• The Evolution of the x86 architecture
• Embedded Systems
• ARM Architecture
Performance Assessment
• Clock Speed and Instructions per Second
• The System Clock
• Instruction Execution Rate
Clock Speed and Instructions
per Second
• THE SYSTEM CLOCK. Operations performed by a processor, such as
fetching an instruction, decoding the instruction, performing an
arithmetic operation, and so on, are governed by a system clock.
Typically, all operations begin with the pulse of the clock. Thus, at the
most fundamental level, the speed of a processor is dictated by the
pulse frequency produced by the clock, measured in cycles per
second, or Hertz (Hz).
• The rate of pulses is known as the clock rate, or clock speed. One
increment, or pulse, of the clock is referred to as a clock cycle, or a
clock tick. The time between pulses is the cycle time.
Clock Speed and Instructions
per Second
• INSTRUCTION EXECUTION RATE
1. Average cycles per instruction (CPI) for a program
Let CPIi be the number of cycles required for instruction type i. and Ii be
the number of executed instructions of type i for a given program. Ic is the
instruction count.
Clock Speed and Instructions
per Second
2. Processor time (T) is the time needed to execute a given
program.
= 1/f is the constant cycle time
In the more refined equation, p is the number of processor cycles needed to
decode and execute the instruction, m is the number of memory references
needed, and k is the ratio between memory cycle time and processor cycle
time.
• Ic, p, m, k are influenced by four system attributes: the design of the instruction
set (known as instruction set architecture), compiler technology (how effective
the compiler is in producing an efficient machine language program from a high-
level language program), processor implementation, and cache and memory
hierarchy.
• Above is a matrix in which one dimension shows the five performance factors
and the other dimension shows the four system attributes.
• An X in a cell indicates a system attribute that affects a performance factor
Clock Speed and Instructions
per Second
3. MIPS rate is the rate at which instructions are executed, expressed as
millions of instructions per second (MIPS)
4. Floating point performance is expressed as millions of floating-point
operations per second (MFLOPS)
SPEC Benchmark
• Benchmark suite is a collection of programs, defined in a high-level language, that
together attempt to provide a representative test of a computer in a particular
application or system programming area.
• The best known such collection of benchmark suites is defined and maintained by
the System Performance Evaluation Corporation (SPEC), an industry consortium.
SPEC performance measurements are widely used for comparison and research
purposes.
• The best known of the SPEC benchmark suites is SPEC [Link] is the industry
standard suite for processor-intensive applications. That is, SPEC CPU2006 is
appropriate for measuring performance for applications that spend most of their
time doing computation rather than I/O. The CPU2006 suite is based on existing
applications that have already been ported to a wide variety of platforms by SPEC
industry members.
Averaging Results
• For m, a different benchmark program, a simple arithmetic mean can
be calculated as follows:
where Ri is the high-level language instruction execution rate for
the ith benchmark program.
• An alternative is to take the harmonic mean:
Speed Metric
• The speed metric measures the ability of a computer to complete a
single task. SPEC defines a base runtime for each benchmark program
using a reference machine. Results for a system under test are
reported as the ratio of the reference run time to the system run
time. The ratio is calculated as follows:
• where Trefi is the execution time of benchmark program i on the
reference system and Tsuti is the execution time of benchmark
program i on the system under test.
Assignment #2
Solve the required information on a separate sheet of paper.
Show your solutions and draw a box around the final answer.
Upload pictures of your answer sheets in Canvas.
Thank you!
B