8255 PROGRAMMABLE PERIPHERAL INTERFACE

(PPI)
 INTRODUCTION

 In reality, we are not supposed to connect I/O devices directly

with the processor’s data bus. Instead, there should be some
device to which I/O ports should connect I/O devices.
 8255 is a Programmable Peripheral Interface, which means it is a
programmable device used to interface I/O devices with the
processor.
 It has three 8-bit ports (PA, PB, and PC), and all ports are
bidirectional (can be used as input or output ports ).
 8255 WORKING

1. Assuming the connected device to

be an input device. Initially, the
Input device seeks for permission
from PPI so that it can send data.

2. PPI permits Input devices to send

data, only when there is no left data
in 8255 which should be sent to the
8086 processor. If there is some
previous data left in 8255, which is
still not sent to 8086, then it doesn’t
permit Input device.
 8255 WORKING

3. Once 8255 permits input device, data

is received and stored in temporary
registers in 8255. 8255 holds that
data, which should be sent to 8086,
and then it sends a signal to 8086.

4. Whenever 8086 is free to receive the data, then 8086 sends back a signal , after that data
transmission happens between 8255 and 8086. If 8086 do not becomes free up to long time,
which means 8255 has some value in it which is still not sent to 8086, so 8255 does not
permit the Input device to send any data because the existing data will be overwritten.
All the signal in these diagrams
represented using red curved arrow are
known as handshake signals. This
process of data transmission is known
as handshaking.
 BASIC FEATURES OF 8255
 The 8255 microprocessor is a PPI (programmable peripheral interface) device.

 It includes three I/O ports which are programmed within different modes.

 This microprocessor simply provides several facilities to connect different devices. Thus it is used in
different applications frequently.
 It operates in three modes like Mode 0 (Simple I/O), Mode 1 (Strobed I/O), and Mode 2 (Strobed bi-
directional I/O).
 It is compatible totally with the families of Intel microprocessors.

 It is TTL compatible.

 For port-C of this microprocessor, direct bit SET/RESET capacity is available.

 It includes 24/40 programmable input/output pins which are placed as 2 to 8-bit ports & 2 to 4-bit ports.

 It includes three 8-bit ports; Port-A, Port-B & Port-C.

 The three I/O ports include a control register that defines each I/O port’s function & in which mode they
must operate.
8255 PIN CONFIGURATION

 It includes 40-pins like PA7-PA0,

PC7-PC4, PC3-PC0, PB0-PB7, , , , A1
& A0,D0-D7 and RESET.
 8255 PIN CONFIGURATION
PA7 to The PA7 to PA0 are Port A data lines pins (1 to 4 & 37 to 40) which are distributed equally
PA0 (PortA on two sides of the top of the pin. These eight port A pins work as either buffered input
Pins) lines or latched output based on the loaded control word into the control word
register.
PB0 to The PB0 to PB7 from 18 to 25 are the data line pins that carry the port B data.
PB7 (Port
B Pins)
PC0 to PC0 to PC7 pins are port C pins which include pin10 to pin17 which carry the port C data
PC7 (Port bits. From there, pins 10 – pin13 are known as Port C upper pins & pin14 to pin17 are
C Pins) known as lower pins. The pins from these two sections can be used individually to
transmit 4 data bits using two separate port C parts.
D0 to D7 These D0 to D7 pins are data I/O lines which include 27-pin to 34-pin. These pins are
(Data bus used to carry the 8-bit binary code and it is utilized to train the entire IC work. These pins
pins) are jointly known as the control register/control word which carries the data of the control
word.
A0 & A1 A0 and A1 pins at pin8 & pin9 simply make a decision about which port will be preferred
for transmitting the data.
 8255 PIN CONFIGURATION

The pin6 like is a chip select input pin which is responsible for selecting a chip. A low
signal at pin simply allows the communication between the 8255 & the processor which
means at this pin, the operation of data transfer gets allowed by an active low signal.
The pin5 like is a read input pin that puts the chip within the reading mode. A low signal
at this pin provides data to the CPU by a data buffer.
The pin36 like pin is a write input pin that puts the chip within writing mode. So, a low
signal at pin simply allows the CPU to execute the write operation above the ports
otherwise microprocessor’s control register through the data bus buffer.
RESET The pin35 like the RESET pin resets the whole data available in all the keys to their
default values when it is in set mode. It is an active high signal where the high signal at
the RESET pin clears the control registers & the ports are placed within the input mode.
GND The pin7 is a GND pin of IC.
VCC The pin26 like VCC is the +5V input pin of IC.
ARCHITECTURE OF 8255
ARCHITECTURE OF 8255

A1 A0 Selection of 8255
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control Word
8255 chip not
1 x x
selected
 1. DATA BUS BUFFER

 The data bus buffer is mainly used for connecting the inside bus
of the 8255 with the system bus so that proper interfacing can be
established between these two.
 This buffer simply permits the read or write operation to be
executed from or to the CPU.
 This buffer permits the data supplied from the control register or
ports to the CPU in case of write operation & from the CPU to the
status register or ports in case of the read operation.
 2. READ/WRITE CONTROL LOGIC

 Read or write control logic unit controls the inside system

operations.
 This unit holds the capability to manage both the data transfer &
status or control words internally & externally.
 Once there needs data to fetch then it allows the provided
address by the 8255 by the bus & generates a command
immediately to the two control groups for the specific operation.
 3. GROUP A & GROUP B CONTROL

 Both these groups are managed by the

CPU and work based on the generated
command by the CPU.
 This CPU transmits control words
toward these two groups and they
consecutively transmit the suitable
command to their particular port.
 Group A controls port A with higher
order port C bits whereas group B
controls port B with lower order port C
bits.
 4. PORT A & PORT B 5. PORT C

 Port A & Port B includes an 8-bit  Port C includes an 8-bit data input buffer and
input latch and 8-bit buffered or 8-bit bidirectional data o/p latch or buffer.
latched output.  This port is divided mainly into two sections –
port C upper PCU & port C lower PCL.
 The main function of these  So these two sections are mainly programmed
ports is also independent of the & separately used as a 4-bit I/O port.
mode of operation.  This port is used for handshake signals,
Simple I/O & status signal inputs. This port is
 Port A can be programmed in 3
used in combination with port A & Port B for
modes like modes 0, 1, and 2 both the status and handshaking signals.
whereas Port B can be  This port provides only direct bit sets or
programmed in modes 0 & resets capacity.

mode 1
 OPERATIONS FOR 8255

Input/Output
A1 A0
Operation
0 0 0 1 0 Port A to Data Bus
0 1 0 1 0 Port B to Data Bus
1 0 0 1 0 Port C to Data Bus
0 0 1 0 0 Data Bus to Port A
0 1 1 0 0 Data Bus to Port B
1 0 1 0 0 Data Bus to Port C
1 1 1 0 0 Data Bus to Control
register

Read operation is not available for CWR

 MODES OF OPERATION
Mode of
Operatio
 8255 has two modes of operation. ns
BSR Parallel
Mode I/O
(Port C) Mode

Mode 0 Mode 1 Mode 2

Port A,B,
Port A, B Port A
and C
 1. PARALLEL I/O MODE

If the D7 = 1, then it is I/O

command or else it BSR command.
D6 and D5 are for mode selection
of port A
D4 is to determine whether port A is
input port or output port.
D3 is used for determine whether
port C – upper is input port or output
port.
D2 is used to select mode of Port B
D1 is to determine whether port B is
input port or output port.
D0 is to determine Port C lower as
the Input or Output Port.
1. PARALLEL I/O MODE
 1. PARALLEL I/O MODE: EXAMPLE

 Example 1: Initialize 8255 PPI to

define:
1. Port A output in mode 1.
2. Port B input in mode 0.
3. Port C low as output.
8 bit address of CWR is 06h.
 1. PARALLEL I/O MODE: EXAMPLE

 Example 1: Initialize 8255 PPI to

define:
1. Port A output in mode 1.
2. Port B input in mode 0.
3. Port Clow as output.
8 bit address of CWR is 06h.
 1. PARALLEL I/O MODE: EXAMPLE
 Example 2: Write an initialization
sequence to define Port A in mode 2,
Port B as output in mode 1. The 16 bit
address of CWR is 2006h.
 1. PARALLEL I/O MODE: EXAMPLE
 Example 3: Define the 8255 PPI Port
A as input in mode 0, Port B as input
in mode 1. The address of control
word register is 81507.
 1. PARALLEL I/O MODE: EXAMPLE
 Example 4: Write a set of Instructions to perform the
following:
1. Initialize Port A as input in mode 0.
2. Initialize Port B as output in mode 1.
3. Initialize Port C upper as output and Port C lower as input
 1. PARALLEL I/O MODE: EXAMPLE
 Example 5: Write an ALP that will input the contents of Port B
and Port C, and then perform ANDing and output the result to Port
A. Port A is connected with address 10600H.
 2. BIT SET-RESET (BSR) MODE

 In the process of handshaking, 6 lines out of 8 lines of PC are

utilized in handshaking, remaining two lines can be used for
attaching bit addressable I/O devices. Such as an Air
Conditioner can be attached to one of these lines. BSR stands
for Bit Set Reset command.
 When port C is utilized for control or status operation, then by
sending an OUT instruction, each individual bit of port C can be
set or reset.
 1. BIT SET-RESET (BSR) MODE

Here,
D7 = 0 for BSR
command.
D6, D5, D4 do
not care pins.
D3 , D2, D1 are
used to select pins
on the PC.
D0 is for set or
reset, for the
selected pin.
 2. BIT SET-RESET (BSR) MODE :EXAMPLE

Example 1: Write a set of instructions to set PC7 pin of 8255 PPI

having ctrl word register at 47h.
 2. BIT SET-RESET (BSR) MODE :EXAMPLE

Example 2: Write a set of instructions to set bit 4 of Port C.

Assume the address of Port A is 10H.
 2. BIT SET-RESET (BSR) MODE :EXAMPLE

Example 2: Write a set of instructions to set bit 4 of Port C.

Assume the address of Port A is 10H.
 2. BIT SET-RESET (BSR) MODE :EXAMPLE

Example 3: Write an assembly language program to set PC6,PC2

and PC4 bits of Port C, and reset them after 50 ms.
 2. BIT SET-RESET (BSR) MODE :EXAMPLE

Example 3: Write an assembly

language program to set
PC6,PC2 and PC4 bits of Port C,
and reset them after 50 ms.

Here the address of CWR is not given,

so assume add. of Port A is 00h, so the
address of CWR is 06h.