COMPUTER ORGANIZATION
AND ARCHITECTURE
UNIT 3: CONTROL UNIT
INSTRUCTION FORMAT:
In general, based on the number of operands
or reference made in the instruction.
Instructions can be classified into three
categories:-
1. Three Address Instruction
2. Two address instruction
3. One address Instruction
4. Zero address instruction.
TIMING CIRCUIT:
In order to perform an instruction, we need to
perform a number of micro-operations, and
these micro-operations must be timed.
AC ← PC
IR ← M[AR], PC ← PC + 1
MICRO-OPERATIONS:
A computer executes a program
Fetch/execute cycle
Each cycle has a number of steps
(see pipelining) Called micro-operations
Each step does very little
Atomic operation of CPU
MICRO OPERATIONS:
Can be performed during one clock period.
Examples: shift, move, count, add, load etc.
Can be classified into 4 categories:
1. Register transfer micro-operations
2. Arithmetic micro-operations
3. Logic micro-operations
4. Shift micro-operations
INSTRUCTION CYCLE:
A program is a sequence of instructions. It is
executed by going through a cycle of each
instruction. Each instruction cycle is
subdivided into a sequence of sub cycles or
phases. Each instruction cycle consists of
these phases:
1. Fetch inst. from the memory
2. Decode
3. Read the effective address
4. Execute
5. Fetch and decode
Example: int i = 5 ;
FETCH - 4 REGISTERS:
Memory Address Register
(MAR)
Connected to address bus
Specifies address for read or
write op
Memory Buffer Register
(MBR)
Connected to data bus
Holds data to write or last data
read
Program Counter (PC)
Holds address of next
instruction to be fetched
Instruction Register (IR)
Holds last instruction fetched
FETCH SEQUENCE
Address of next instruction is in PC
Address (MAR) is placed on address bus
Control unit issues READ command
Result (data from memory) appears on data
bus
Data from data bus copied into MBR
PC incremented by 1 (in parallel with data
fetch from memory)
Data (instruction) moved from MBR to IR
MBR is now free for further data fetches
FETCH SEQUENCE (SYMBOLIC)
t1: MAR <- (PC)
t2: MBR <- (memory)
PC <- (PC) +1
t3: IR <- (MBR)
(tx = time unit/clock cycle)
or
t1: MAR <- (PC)
t2: MBR <- (memory)
PC <- (PC) +1
t3: IR <- (MBR)
RULES FOR CLOCK CYCLE GROUPING
Proper sequence must be followed
MAR <- (PC) must precede MBR <- (memory)
Conflicts must be avoided
Must not read & write same register at same
time
MBR <- (memory) & IR <- (MBR) must not be in
same cycle
Also: PC <- (PC) +1 involves addition
UseALU
May need additional micro-operations
EXAMPLE OF TIMING:
Memory reference and register reference instructions
RISC (REDUCED INSTRUCTION SET
COMPUTER):
RISC processors typically have a limited set of
instructions, often performing basic operations like
arithmetic, logic, and data movement.
RISC processors aim to execute most instructions in a
single clock cycle, resulting in faster instruction
throughput.
Few instructions and addressing modes.
Hardwired rather than microprogrammed control.
RISC processors typically have a larger number of
registers, This reduces the need for memory accesses,
improving performance.
RISC computer has a small set of simple and general
instructions, rather than large set of a complex and
specialized ones.
Example: SUMMIT (2020), 200 petaFLOPS operations per
second
CISC (COMPLEX INSTRUCTION SET
COMPUTER):
CISC processors support a wide range of complex instructions
that can perform multiple operations in a single instruction.
CISC architectures often include memory-to-memory
operations, where data can be transferred directly between
memory locations without involving the CPU registers.
Instructions in CISC architectures can vary in length,
depending on the complexity of the operation being
performed.
CISC processors have specialized hardware to execute
complex instructions efficiently. This hardware includes
microcode, which translates complex instructions into a series
of simpler micro-operations that can be executed by the CPU.
Compared to RISC architectures, CISC architectures typically
have a smaller number of general-purpose registers.
# of instructions 100-250
# of Addressing modes 5-20
Variable length instruction format.
DESIGNING OF CONTROL UNIT:
The control signal can be generated either by
hardware (hardware CU) or by micro-program
control unit (m/y + hardware).
In Hardware control unit design, each control
signal expressed as SOP expression and
realized by digital hardware.
Fixed logic circuits that correspond directly to
the Boolean expression are used to generate
control signal.
EXAMPLE OF TIMING:
Uses three 8-bit register’s A,
B, and C. Supports two
instructions I1 and I2.
DIFFERENCE BETWEEN HARDWIRED
AND MICRO-PROGRAMMED
Characteristics Hardwired Micro-
programmed
control
Speed Fast Slow
Implementation Hardware Software
Complex Difficult Easier
instruction
Design Process Difficult for more Easy
operation
Memory Not used Control Memory
used
Used in RISC CISC
MICRO PROGRAMMED CONTROL
UNIT:
Introduced by Maurice Wilkies (1951).
Advantage is the simplicity of its structure
Microprograms were organized as a sequence
of microinstructions and stored in a special
control memory
In this the binary patterns of control signals
are stored in control m/y. After accessing word
from the control memory, hardware is used to
generate the control signals.
Design is flexible and it is used in CISC System
Types-
1. Horizontal microprogram
2. Vertical microprogram
HORIZONTAL MICROPROGRAM (EXAMPLE)
Provides higher degree of parallelism, suitable in multi-processor system
Requires more bits for control word (1 bit for every control signal)
VERTICAL MICROPROGRAM (EXAMPLE)
Reduces the size of control words by encoding.
Maximum degree of parallelism is 1 (due to decoder)
Horizontal Vertical
Long Format Short Format
Ability to express high degree Limited ability to express
of multi-programming Parallelism
Little encoding of control Considerable encoding
information
Useful when higher operating Slower operating speed
speed is desired
Note: The Combination of both controlled unit is preferred in most
applications
CONTROL WORD SEQUENCING:
In order to implement micro-program, control
words are to be sequentially from control
memory. One address instruction is used for
performing the control word sequencing.