COMPUTER ORGANIZATION &
ASSEMBLY
CS-530
WEEK 2
Mr. Shoaib Nazir / Mr. KAMRAN Ali
CS & IT Department, GIMS
Copyright © 2012 Cengage Learning. All rights reserved. 2
Lecture Overview
1. Architecture of Registers &Flip-flops
2. Register with Parallel Load
3. Shift Registers
4. Bidirectional Shift Registers with Parallel
Load
5. Binary Counters
6. Binary Counter with Parallel Load
Intro To Registers
Registers in digital electronics are the group of binary storage
cells capable of holding binary information. A group of flip-flop
constitutes a register since each flip-flop can work as a binary
cell.
An ‘n’ bit register has ‘n’ flip-flops and is capable of holding
‘n’ bit of information.
In addition to flip-flop, a register can have a combinational part
that performs data processing task.
Various types of registers are available commercially. The
simplest register is one that consists only of flip-flops, with
no external gates.
Simple register constructed with four D flip-flops
• The common clock input triggers all flip-flops inputs.
• The four outputs can be sampled at any time to obtain the
binary information stored in the register.
• The clear input goes to a special terminal in each flip-flop.
When this input goes to 0, all flip-flops are reset
asynchronously.
• clear signal enables the D input but independent of clock.
Register with Parallel Load
• The transfer of new information into a register is referred
to as loading the register.
• If all the bits of the register are loaded simultaneously with
a common clock pulse transition, loading is parallel.
• Most digital systems have a master clock generator that
supplies a continuous train of clock pulses.
Register with Parallel Load
• The clock pulses are applied to all flip-flops and registers
in the system.
• The master clock acts like a pump that supplies a
constant beat to all parts of the system.
• A separate control signal must be used to decide which
specific clock pulse will have an effect on a particular
register.
Shift Registers
A register capable of shifting its binary information in one or
both directions is called a shift register.
All flip-flops receive common clock pulses that initiate the
shift from one stage to the next.
The simplest possible shift register is one that uses only
flip-flops, as shown in Fig. 2-8.
The output of a given flip-flop is connected to the D input of
the flip-flop at its right.
Shift Registers
With the help of common clock pulse, serially leftmost register’s information
transferred to rightmost register.
Bidirectional Shift Register with Parallel Load
A register capable of shifting in one direction only is called
a unidirectional shift register.
A register that can shift in both directions is called a
bidirectional shift register.
The most general shift register has all the capabilities listed
below.
1. An input for clock pulses to synchronize all operations.
2. A shift-right operation and a serial input line associated
with the shift right.
Bidirectional Shift Register with Parallel Load
3. A shift-left operation and a serial input line associated with
the shift-left.
4. A parallel load operation and n input lines associated with
the parallel transfer.
5. n parallel output lines.
6. A control state that leaves the information in the register
unchanged even though clock pulses are applied continuously.
Bidirectional Shift Register with Parallel Load
Types of Shift Registers
i. Serial in serial out
ii. Serial in parallel out
iii. Parallel in parallel out
iv. Parallel in serial out
Cont…
Serial-in-Serial-out (SISO): This type of registers accept data
serially i.e. 1 bit at a time, at the single input line. The output is also
obtained on a single output line in a serial manner. The data within
the register may be shifted from left to right using shift left to
register or may be shifted from right to left using shift right register.
Block Diagram:
Cont…
Serial-in-Parallel-out (SIPO): In this type of registers, the data is
shifted in serially but shifted out in a parallel manner. To obtain the
output data in parallel, it is required that all the output bits are
available at the same time. This can be obtained by connecting the
output of each flip-flop to an output pin. The bits are available
simultaneously, once the data is stored in the flip-flop.
Block Diagram:
Cont… (BSCS 3rd B)
Parallel-in-Serial-out (PISO): In this type of register, the parallel data is
loaded into the register simultaneously and is shifted out of the register
serially one bit at a time under clock control. The block diagram of this type
of register is given below:
Block Diagram:
Cont..
Parallel-in-Parallel-out (PIPO): These types of registers are designed such
that data can be shifted into or out of the register in a parallel manner. The
parallel input of data has no interconnection between the flip-flops since no
serial shifting is required. Hence the moment the parallel entry of data is
accomplished, the data will be available at the parallel outputs of the register.
Block Diagram:
Applications of Registers
Some main applications of registers are given below:
The shift registers are used for temporary data storage.
The shift registers are also used for data transfer and data manipulation.
The serial-in serial-out and parallel-in parallel-out shift registers are used to
produce time delay to digital circuits.
A Parallel-in-Serial-out shift register is used to convert parallel data to serial
data.
Counters
A register that goes through a predetermined sequence of
states upon the application of input pulses is called a
counter.
The input pulses may be clock pulses or may originate from
an external source.
They may occur at uniform intervals of time or at random.
These are useful for generating timing signals to control the
sequence of operations in digital computers.
Binary Counters
• A counter that follows the binary number sequence is
called a binary counter.
• An n-bit binary counter is a register of n flip-flops and
associated gates that follows a sequence of states
according to the binary count of n bits, from 0 to 2" - 1.
• The design of binary counters can be carried out by the
procedure outlined in Sec. 1-7 for sequential circuits.