COA-MODULE V- Basic Processing Unit

(HARDWIRED CONTROL AND MICROPROGRAMMED

CONTROL)

COA- Module 5
1
 COA- MODULE V
BASIC PROCESSING
UNIT

COA- Module 5
4
Machine Cycle

COA- Module 5
Model of Control Unit

COA- Module 5
 Functions of Control Unit using Control Signals
 Sequencing
 CU causes the CPU to step through a series of micro-
operations in proper sequence based on the program being
executed.
E.g. In order to carry out a task such as ADD, the control unit
must generate a set of control signals in a predefined
sequence governed by the HW structure of the processing
section.
 Execution
 CU causes each micro-operation to be performed

 Control Signals
 External: inputs indicating the state of the system
 Internal: logic required to perform the sequencing and
execution functions

COA- Module 5
 Fundamental Concepts contd..
 Inputs to control unit are:
 Master clock
 Status info from processing section
 Command signals from external agent
 Outputs produced by control unit
 Signals that drive the processing section and responses to an external
envent (operation complete or abort) due to exceptions (overflow and
underflow)
 Control unit undertakes the following responsibilities
 Instruction interpretation:

Read instr. , Recognize, Get operands and Route to appropriate

functional
units, necessary control signals issued
 Instruction sequencing:

Control unit determines the address of next instruction to be executed

and loads to PC
 Processor fetches one instruction at a time and perform the operation
specified.
 Instructions are fetched from successive memory locations until a
branch or a jump instruction COA- Module 5
is encountered
Connection between CPU and Memory

COA- Module 5
 Fetch/execute cycle
 Step I:
 Fetch the contents of the memory location pointed
to by Program Counter (PC).
 PC points to the memory location which has the
instruction to be executed.
 Load the contents of the memory location into
Instruction Register (IR).
 Step II:
 Increment the contents of the PC by 4 (assuming the
memory is byte addressable and the word length is 32
bits).
 Step III:
 Carry out the operation specified by the instructions in the
IR.
 Steps I and II constitute the fetch phase, and are repeated
as many times as necessary to fetch the complete
instruction.
 COA- Modulephase.
Step III constitutes the execution 5 10
 Internal organization of a processor

 Recall that a processor has several

registers/building blocks:
 Memory address register (MAR)
 Memory data register (MDR)
 Program Counter (PC)
 Instruction Register (IR)
 General purpose registers R0 - R(n-1)
 Arithmetic and logic unit (ALU)
 Control unit.
 How are these units organized and how do they
communicate with each other?

COA- Module 5 11
 Organization

PC
Decoder
contr
MAR ol
IR
memory
bus MDR Register
file
R0
Y
R1

R2
AL
U Rn-1
Z

CPU
bus 5
COA- Module 12
 Register
Const Y_in
gating Ri_in
4
Y x
x

Select MUX Ri

ALU x

Z_in x Ri_out
Z

Z_out
C
P
COA- Module
U 5 13
 Input & Output Gating for one Register Bit

 A 2-input multiplexer is used to select the data applied to the input

of an edge-triggered D flip-flop.
 When Riin =1, mux selects data on bus. This data will be
loaded into flip-flop at rising-edge of clock.
When Riin =0, mux feeds back the value currently
stored in flip-flop.
 Q output of flip-flop is connected to bus via a tri-state gate.

When Riout = 0, gate's output is in the high-impedance

state. (This corresponds to the open- circuit state of a
switch).

When Riout =1, the gate drives the bus to 0 or 1, depending

on the
value of Q.

COA- Module 5 1
4
 Registers and the
bus
bus line 0
bus line 1

bus line m-1 (e.g., 31)

bit 0

register

bit m-1 clock

COA- Module 5 15
 Internal organization of a
processor Control
signals
PC

Instruction
Addres
decoder
s line
s MAR and control
logic
Memor
y bus
MDR HAS
TWO INPUTS MDR
AND TWO Dat
a IR
OUTPUTS line
s
Y
Constant R0
4

Selec MUX

processor
t

Internal
Ad

Bus
d A B
ALU Sub R n - 1
contr ALU
ol
lines Carry-
XOR in TEMP
 Single bus organization

 Single bus organization:

 ALU, control unit and all the registers are connected
via a single common bus (Called Internal Bus)
 Bus is internal to the processor and should not be
confused with the external bus that connects the
processor to the memory and I/O devices.
 Data lines of the external memory bus are connected
to the internal processor bus via MDR.
 Register MDR has two inputs and two outputs.
 Data may be loaded to (from) MDR from (to) internal
processor bus or external memory bus.
 Address lines of the external memory bus are
connected to the internal processor bus via MAR.
 MAR receives input from the internal processor bus.
 MAR provides output to external memory bus.

COA- Module 5
 Single bus organization (contd..)
 Instruction decoder and control logic block, or control
unit issues signals to control the operation of all units
inside the processor and for interacting with the
memory bus.
 Control signals depend on the instruction loaded in the
Instruction Register (IR)
 Outputs from the control logic block are connected to:
 Control lines of the memory bus.
 ALU, to determine which operation is to be performed.
 Select input of the multiplexer MUX to select between
Register Y and constant 4.
 Control lines of the registers, to select the registers.

COA- Module 5
 Single bus organization (contd..)

 Registers Y, Z, and TEMP:

 Used by the processor for temporary storage during
execution of some instructions.
 Note that Registers R0 to R(n-1) are used to store
data generated by one instruction for later use by
another instruction.
 Data is stored in R0 through R(n-1) after the execution
of an instruction.
 Multiplexer MUX selects either the output of register Y
or
a constant 4, depending upon the control input
Select.
 Constant 4 is used to increment the value of the PC.
 B input of ALU is obtained directly from processor-bus.
As instruction execution progresses, data are transferred from
one register to another, often passing through ALU to perform
arithmetic or logic operation.
COA- Module 5
 Registers and the bus (contd..)

 A bus may be viewed as a collection of parallel wires.

 Buses have no memory:
 They are just a collection of wires.
 When data is on the bus, all registers can “see” that
data at their inputs.
 A register may place its contents onto the bus.

COA- Module 5
 Registers and the bus (contd..)

 At any one time, only one register may output its

contents to the bus:
 Which register outputs its content to the bus is
determined by the control signal issued by the control
logic.
 Control signal depends on the instruction loaded in the
instruction register.
 Registers can load data from the bus:
 Which registers load data from the bus is determined by
the control signal issued by the control logic.
 Registers are clocked (sequential) entities (unlike ALU
which
is purely combinatorial).

COA- Module 5
 The Processing Unit

1. Basic Processing
Cycle
1. Register Transfer
2. Types of Operations 2. Fetch from Memory
3. Control Mechanisms 3. Store to Memory
4. Arithmetic/Logic Ops.
5. Execution of Complete
Instruction
6. Branching Ops.

COA- Module 5
 2. Types of Operations

 Operation cycle includes:

 Transfer data from register to register or to ALU
 Fetch contents of memory location and put in
one of the CPU registers
 Store contents of CPU register in memory
location
 Perform arithmetic or logic operation

COA- Module 5
 2.1. Register Transfers

CPU bus R_out

Copy contents of R1 to
R3
1. Address_out=R R0
1 Y
2. R_out R1
3. Address_in=R3
R2
4. R_in ALU
R3

1.R1_ou Z register file

t
2.R3_in
When Riin =1, data on bus is loaded into Ri Address_out
R_in
 when Riout =1, content of Ri is placed on Address_in
bus

COA- Module 5
 Registers and the bus (contd..)

Bu
s

D Q
1
Q Riout
Cloc
Ri in k

All operations and data transfers are controlled by the processor

clock
• Each bit in a register may be implemented by an edge-triggered D
flip flop.
• Two input multiplexer is used to select the data applied to the input
of an
edge triggered flip-flop.
• Q output of the flip-flop is connected
COA- Moduleto
5 the bus via a tri-state gate.
 Registers and the bus (contd..)

Bu
s

D Q
1
Q Riout
Cloc
Ri in k

Riin = 1:
Multiplexer selects the data on the bus.
Data is loaded into the flip-flop at the rising edge of the
clock.
Riin = 0:
Multiplexer feeds back the value currently stored in the flip-
flop. Q output represents the value currently stored in the
COA- Module 5
flip-flop. 26
 Registers and the bus (contd..)

Bu
s

D Q
1
Q Riout
Cloc
Ri in k

Riout = 1:
Tri-state gate loads the value of the flip-flop onto the
bus. Data is loaded onto the bus at the rising edge of
the clock.
Riout = 0:
Gate’s output is in high-impedance (electrically disconnected)
state. Corresponds to open-circuit state.
COA- Module 5 27
 Registers and the bus (contd..)

Operation of a tri-state gate

• A tri-state gate can enter one of three output states.
- its output can be in a logic low state (L).
- its output can be in a logic high state (H).
- its output can be effectively an open-circuit (high impedance)
• When a tri-state gate is connected to a bus in high-impedance state, its
outputs are effectively disconnected from the bus.
Riout = 1, output is: Riout = 0:
Logic low, if Q = 0 High impedance
Logic high, if Q = Open circuit condition
1 Bus
Bus

0 0
D D
1 Q 1 Q
Cloc
Q Cloc
Q
Riin k Riin k

COA- Module 5 28
 Registers and the bus (contd..)

Operation of a tri-state gate

• A tri-state gate can enter one of three output states.
- its output can be in a logic low state (L).
- its output can be in a logic high state (H).
- its output can be effectively an open-circuit (high impedance)
• When a tri-state gate is connected to a bus in high-impedance state, its
outputs are effectively disconnected from the bus.
Riout = 1, output is: Riout = 0:
Logic low, if Q = 0 High impedance
Logic high, if Q = Open circuit condition
1 Bus
Bus

0 0
D D
1 Q 1 Q
Cloc
Q Cloc
Q
Riin k Riin k

COA- Module 5
 Registers and the bus (contd..)

Operation of an edge-triggered
flip-flop

single processor clock period

Low-to-High transition

• Data is loaded from the register to the bus (or to the register from the
bus) at the rising edge of the clock.
• Data is loaded at the L-H transition of the clock.

COA- Module 5
 Simple register transfer example

Transfer the contents of register R3 to

register R4

Clock period

1 3
2

[Link] signals R3out and R4in become 1. They stay valid until the
end of the clock cycle.
[Link] a small delay, the contents of R3 are placed onto the bus. The
contents of R3 stay onto the bus until the end of the clock cycle.
3. At the end of the clock cycle, the data onto the bus is loaded into R4.
R3out
and R4in become 0.

COA- Module 5
 The Processing Unit

1. Basic Processing
Cycle
1. Register Transfer
2. Types of Operations 2. Fetch from Memory
3. Control Mechanisms 3. Store to Memory
4. Arithmetic/Logic Ops.
5. Execution of Complete
Instruction
6. Branching Ops.

COA- Module 5
 2.2. Fetch from Memory (1)

Memory bus Internal

Data lines processor
(External bus
MDR_out MDR_ou
Bus) E t

x x

MDR

x x

MDR_in MDR_i
E n

COA- Module 5
 2.2. Fetch from memory (2)
e.g., Move (Ri),Rj
Control Step
1 MAR 
1 . [Ri]
Start read on memory
Control Step 2 bus Wait for MFC Memory
2 . response Load MDR from Function
Control Step 3 memory bus Rj  Complete
3 . [MDR]
4
Addres
. MAR s
5 Dat
. MDR a CPU
Rea
Memor
Memory d
y MF
C

COA- Module 5
 Fetch from memory (3)
Signal Activation Sequence Internal
processor
Control Step Ri_out, MAR_in, Read bus
1. MDR_inE,
Ri_in
Control Step WMFC
2. MDR_out, Rj_in
Control Step x
3.
MDR_out MDR_ou
Ri
E t

Memory x x
bus Data MD x
lines R
x x Ri_out

MDR_in MDR_i
E n

COA- Module 5
 2.2. Fetch from Memory
Timing
(4) 1 of the Operation2
3 1. Ri_out, MAR_in,
CLK Read
2. MDR_inE,
WMFC
3. MDR_out, Rj_in
MAR_i
n
New MAR to
addres Address [Link]

s Read
MR [Link]
Cmd.
MDR_in
E
Valu [Link] to
Dat e MDR
[Link]
a ete
MDR_ou
MFC
t

COA- Module 5
 The Processing Unit

1. Basic Processing
Cycle
1. Register Transfer
2. Types of Operations 2. Fetch from Memory
3. Control Mechanisms 3. Store to Memory
4. Arithmetic/Logic Ops.
5. Execution of Complete
Instruction
6. Branching Ops.

COA- Module 5
 2.3. Store into Memory

e.g., Move Rj,(Ri)

1 Ri_out, MAR_in
. Rj_out, MDR_in, Write
2 MDR_outE, WMFC
.
3
. Address

Dat
Memor a CPU
y
Writ
e
MF
C

COA- Module 5
 The Processing Unit

1. Basic Processing
Cycle
1. Register Transfer
2. Types of Operations 2. Fetch from Memory
3. Control Mechanisms 3. Store to Memory
4. Arithmetic/Logic Ops.
5. Execution of Complete
Instruction
6. Branching Ops.

COA- Module 5
 2.4. Arithmetic Operation

ADD R3,R2,R1

Step Action
1. Address out _
R1
Y_in
R_out
2
. Address out
_R2 R_out
F_alu

“ADD”
Address in _
Z_in
R3 Z_out
R_in

COA- Module 5
CO-Unit VI-Basic Processor
 Register Transfers
1. Address_out  R1 R_out
CPU bus
Y_in
R_ou
t
R0
Y_in Y
R1

R2
ALU
R3
Z register file

Address_out

COA- Module 5
 Register Transfers
2. Address_out 
R2 R_out CPU bus R_out
F_alu  “ADD”
Z_in
R0
Y_in Y
R1

R2
F_alu
ALU
R3
Z_in Z register file

Address_out

COA- Module 5
 Register Transfers

Address_in  CPU bus

R3 Z_out
R_in
R0
Y
R1

R2
ALU
R3
Z register file

Z_out R_in
Address_in

COA- Module 5
 Steps in
time CPU bus

Ste 1 2 3
Y_in
p Y
Y_in

Z_i ALU
n
Z_in Z
Z_ou
t

R_in
Z_out

COA- Module 5
 The Processing Unit

1. Basic Processing
Cycle 1. Register Transfer
2. Types of Operations 2. Fetch from Memory
3. Control Mechanisms 3. Store to Memory
4. Arithmetic/Logic Ops.
5. Execution of Complete
Instruction
6. Branching Ops.

COA- Module 5 46
 2.5. Execution of a Complete Instruction

1 Fetch instruction
. Fetch the
2 operand Perform
. operation Store
3 result
.
 Exampl ADD (R3),R1
e 4
[R1]
.  M([R3]) +
[R1]

COA- Module 5 47
Execution fetch (1)

[R1]  M([R3]) +
Step Action
[R1]
1 PC_out, MAR_in,
Read Set carry-in Step 1-3:
ALU Instruction fetch and
F_alu = PC update
“ADD” Z_in
 Z_out,
PC_in Wait
for MFC [PC]  [PC ]
3 MDR_out, +1
IR_in

[IR]  M([PC ])

Note: for architectures having PC:=PC+4

a different scheme must be used

COA- Module 5
 Fetch [R1]  M([R3]) +
[R1] 1.. PC_out, MAR_in,
instruction
MAR_in
MAR Read Set carry-in
ALU
PC_out F_alu = “ADD”
Z_in
PC IR

ADD ALU MDR

carry
Z_in Z

Read

WFMC Q) Why Set carry-in

ALU?
Q) Why MAR_in?
COA- Module 5
Execution fetch [R1]  M([R3]) +
(2) [R1]
Step 1-3:
Step Action instruction
1 PC_out, MAR_in, fetch
Read Set carry-in and PC
ALU update
F_alu =
“ADD” Z_in [PC]  [PC ]
 Z_out, +1
PC_in Wait
for MFC [IR] 
3 MDR_out, M([PC ])
IR_in

COA- Module 5
 Fetch
[R1]  M([R3]) +
instruction [R1]
MAR_in
MAR

PC_in IR
PC

 Z_out,
PC_in Wait
for MFC ALU MDR
MDR_in
Z

Read

WFMC Z_out Q What is read into

MDR?

COA- Module 5
Execution fetch [R1]  M([R3]) +
(3) [R1]

Step 1-3:
Step Action instruction
1 PC_out, MAR_in, fetch
Read Set carry-in and PC
ALU update
F_alu =
“ADD” Z_in
 Z_out,
PC_in Wait
for MFC
[IR] 
3 MDR_out,
M([PC ])
IR_in

COA- Module 5
 Fetch [R1]  M([R3]) +
instruction [R1]
3. MDR_out, IR_in Q What is loaded into
MAR IR?

PC IR
IR_in

ALU MDR

Read
MDR_out
WFMC

COA- Module 5
Execute
Step Action
4 Address_out=R3, Step 4 and 5:
R_out MAR_in operand fetch
Read

 Address_out=R1,
Perform
R_out Y_in, Wait for
addition
MFC
6 MDR_out,
Z_in F_alu =
Store
“ADD”
Result
7 Address_in=R1,
R_in Z_out, End

COA- Module 5
 Execute
Read
PC Decoder
control
MAR
IR
memory bus
MDR register file
4. R0
R3_out Y
MAR_i R1
n Read
R2
ALU
R3
Z

CPU bus Q) Role of

Decoder?
COA- Module 5
CO-Unit VI-Basic Processor
Execute

Step Action
4 Address_out=R3, Step 4 and 5:
R_out MAR_in operand fetch
Read

 Address_out=R1,
R_out Y_in, Wait for Perform
MFC addition
6 MDR_out,
Z_in
F_alu =
7 “ADD”
Address_in=R1, Store
R_in Z_out, End Result

COA- Module 5 56
 Execute
WFMC Decoder
PC

control
MAR
IR
memory bus

CPU bus
MDR

R0
Y
R1
 R1_out
Y_in, Wait for MFC R2
ALU
R3
Z register file

Q Where does MDR read

CO-Unit VI-Basic Processor from?
COA- Module 5
Unit
Execute

Step Action
4 Address_out=R3,
R_out MAR_in Step 4 and 5:
Read operand fetch

 Address_out=R1,
R_out Y_in, Wait for Perform
MFC addition
6 MDR_out,
Z_in F_alu =
Store Result
“ADD”
7 Address_in=R1,
R_in Z_out, End

COA- Module 5
 Execut [R1]  M([R3]) +
[R1]
e
6. MDR_out, Decoder
Z_in F_alu = PC
“ADD” control
MAR
IR
memory bus
MDR register file
R0
Y
R1

R2
Q Why ALU
Z_in? R3
Z
Q) Who sets F_alu to
CPU bus ADD?
COA- Module 5
 [R1]  M([R3]) +
Execut [R1]
e
Step Action
4 Address_out=R3,
Step 4 and 5:
R_out MAR_in
operand fetch
Read

 Address_out=R1,
Perform
R_out Y_in, Wait for
addition
MFC
6 MDR_out,
Z_in Store
F_alu = Result
7 “ADD”
Address_in=R1,
R_in Z_out, End

COA- Module 5
 Execute
Decoder
7. R1_in PC
Z_out,
End control
MAR
IR
memory bus
MDR register file
R0
Y
R1

R2
ALU
R3
Z

CPU bus Q) Role of

End?
COA- Module 5 61
 The Processing Unit

1. Basic Processing
Cycle
1. Register Transfer
2. Types of 2. Fetch from Memory
Operations
3. Store to Memory
3. Control Mechanisms 4. Arithmetic/Logic Ops.
5. Execution of Complete
Instruction
6. Branching Ops.

6
2

COA- Module 5 62
2.6. Branching

Jump: PC+Offset

Step Action
1-3 <instruction fetch
as in previous
example>
 PC_out,
Y_in
5 Offset-field-
IR_out F_alu =
“ADD” Z_in

6 PC_in
Z_out,
End

COA- Module 5 63
 Branching
Decoder
 PC_out, Y_in PC

control
MAR
IR
memory bus
MDR register file
R0
Y
R1

R2
ALU
R3
Z

CPU bus
CO-Unit VI-Basic Processor COA- Module 5 64
Unit
Branching

Step Action
1-3 <instruction fetch
as in previous
example>
 PC_out,
Y_in
5 Offset-field-
IR_out F_alu =
“ADD” Z_in

6 PC_in
Z_out,
End

COA- Module 5 65
 Branching
5. Offset-field- PC Decoder
IR_out F_alu =
“ADD” Z_in control
MAR
IR
memory bus
MDR
register file
R0
Y
R1

R2
ALU
R3
Z

CPU bus
CO-Unit VI-Basic Processor COA- Module 5 66
Unit
 Branching

Step Action
1-3 <instruction fetch
as in previous
example>
 PC_out,
Y_in
5 Offset-field-
IR_out F_alu =
“ADD” Z_in

6 PC_in
Z_out,
End

COA- Module 5
CO-Unit VI-Basic Processor
 Branching
Decoder
6. PC_in PC
Z_out, control
End
MAR
IR
memory bus
MDR

R0
Y
R1

R2
ALU
R3
Z register file

CPU bus
COA- Module 5
Conditional branching

JN : PC+Offset

Step Action
1-3 <instruction fetch
as in previous
example>
 PC_out, Y_in If not
If N=0 then Negative
End
5 Offset-field-
IR_out F_alu =
“ADD” Z_in

6 PC_in
Z_out,
End

COA- Module 5 69
 2. Performing an Arithmetic or Logic
Operation2.
Ex. R3 R1+ Internal
bu
processor
R2
 What is the sequence of Riin
s

operations ?
Ri
Step 1: Output of the register R1 and input
of the register Y are enabled, causing Riout
the contents of R1 to be transferred to Yin
Y.
Step 2: The multiplexer’s select signal is set Y
to select Y causing the multiplexer to gate Constant
the contents of register Y to input A of the 4
ALU.
 R1out, Yin
Selec MUX
t
Step 3: The contents of Z are transferred A B
 R2out, SelectY, Add,
to the destination register R3. ALU
Zin
 Zin
Zout, R3in
Z

Zout

COA- Module 5 70
Ex. Move (R1),R2.
The sequence of steps
is:
1)R1out, MARin, Read ;desired address
Read is loaded into MAR &
command is issued
2) MDRinE, WMFC ;load MDR from memory bus & Wait for
MFC response from memory
3)MDRout R2in
,
;load R2 from MDR
where WMFC=control signal that
causes
processor's control circuitry to wait for
arrival of MFC signal

Note: we have not considered Instruction fetch

operation.

COA- Module 5
 Control sequence for the
instruction
EX. Move (Rs),Rd

The control-sequence is written as follows

1)PCout, MARin, Read, Select4, Add, Zin
2)Zout, PCin, Yin, WMFC
3)MDRout, IRin

4)Rsin, MARin, Read

5)MDRinE, WMFC

6)MDRout, Rdin, End

COA- Module 5
 Execution of a complete instruction
Consider the instruction Add
(R3),R1 Which adds he contents of
a memory- Location
pointed by R3 to register
R1.
Executing this instruction
requires the following
actions:
1)Fetch the instruction.
2)Fetch the first operand.
3)Perform the addition.
4)Load the result into R1.

COA- Module 5
 Instruction
Execution
Instruction execution proceeds as follows: R1← R1 + [R3]
Step1:The instruction-fetch operation is initiated by loading contents
of PC into MAR & sending a Read request to memory. The Select
signal is set to Select4, which causes the Mux to select constant 4.
This value is added to
operand at input B (PC‟s content), and the result is stored in Z
Step2: Updated value in Z is moved to PC.
Step3: Fetched instruction is moved into MDR and then to IR.
Step4: Contents of R3 are loaded into MAR & a
memory read signal is issued.
Step5: Contents of R1 are transferred to Y
Step6: When Read operation is to
completed,memory-operand is available in MDR,
Prepare for addition.
addition
and the is performed.
Step7: Sum is stored in Z, then transferred to R1.
The End signal causes a new instruction fetch
cycle to begin by returning to step1.
COA- Module 5
Single Bus organization of the data path within a
CPU

COA- Module 5
 Internal organization of a
Internal processor
processor bus

Control signals

PC

Instruction
Addres
decoder
s line
s MAR and control
logic
Memor
y bus

MDR
Dat
a IR
line
s
Y

Constant R0
4

Selec MUX
t

Ad
d A B
ALU Sub R n - 1
contr ALU
ol
lines Carry-
XOR in TEMP

Z
COA- Module 5
 Execution of a Complete Instruction

Add (R3), R1← R1 +

R1 [R3])

COA- Module 5
 Execution of a Complete Instruction

Add R2,
R1

R2out

COA- Module 5 78
 Execution of Branch Instructions
 A branch instruction replaces the contents of PC with
the branch target address, which is usually obtained
by adding an offset X given in the branch instruction.
 The offset X is usually the difference between the
branch target address and the address immediately
following the branch instruction.
 Unconditional branch

COA- Module 5
79
 Execution of Branch Instructions
The processing starts, as usual, the fetch phase ends in step3.
In step 4, the offset-value is extracted from IR by instruction-decoding circuit.
Since the updated value of PC is already available in register Y, the offset X is
gated
onto the bus, and an addition operation is performed.
In step 5, the result, which is the branch-address, is loaded into the PC.

The offset X used in a branch instruction is usually the difference between

the branch target-address and the address immediately following the
branch instruction. (For example, if the branch instruction is at location 1000
and branch target-address is 1200, then the value of X must be 196,
since the PC will be containing the address 1004 after fetching the
instruction at location 1000).
In case of conditional branch, we need to check the status of
the condition-codes before loading a new value into
the PC.
e.g. Offset-field-of-IRout, Add, Zin, If N=0 then END

If N=0, processor returns to step 1

immediately after step 4.
If N=1, step 5 is performed to load COA-aModule 5
new value into PC 8
0
 Execution of Branch Instructions

Step Action

1 PCout , MAR in , Read, Select4, Add,

2 Zin

3 Zout, PCin , Yin, WMF

4 C MDRout , IRin

5 Offset-field-of-IRout,

Add, Zin
Zout, PCin for
Fig. Control sequence , End
an unconditional branch
instruction.

CO-Unit VI-Basic Processor COA- Module 5

81
Unit
Multiple-Bus Organization
•Allow the contents of
two different registers to
be accessed
simultaneously and have
their contents placed on
buses A and B.
•Allow the data on bus C
to be loaded into a third
register during the same
clock cycle.
• Incrementer unit.
•ALU simply passes
one of its two input
operands unmodified to
bus C
 control signal: R=A or
R=B
COA- Module 5
 General purpose registers are combined into a single block called
registers.
 3 ports,2 output ports –access two different registers and have
their contents on buses A and B
 Third port allows data on bus c during same clock cycle.
 Bus A & B are used to transfer the source operands to A & B inputs
of the ALU.
 ALU operation is performed.
 The result is transferred to the destination over the bus C.
 ALU may simply pass one of its 2 input operands unmodified to
bus C.
 The ALU control signals for such an operation R=A or R=B.
 Incrementer unit is used to increment the PC by 4.
 Using the incrementer eliminates the need to add the constant
value 4 to the PC using the main ALU.
 The source for the constant 4 at the ALU input multiplexer can be
used to increment other address such as loadmultiple &
storemultiple
COA- Module 5
 Multiple-Bus Organization

 Add R4, R5, for the three-bus

R6 organization

Step Action

1 PCout, R=B, MARin , Read,

2 IncPC
WMFC
3 MDRoutB, R=B,
IRin
4 R4outA, R5outB, SelectA, Add, R6in ,
End

Fig. Control sequence for the

instruction
.
COA- Module 5
Instruction execution proceeds as follows in Multiple-
Bus Organization
Step 1:The contents of PC are passed
through the ALU using R=B control signal & loaded into MAR to
start a memory read operation
At the same time PC is incrementer
by 4 Step 2:The processor waits
for MFC
Step 3: Loads the data ,received into
MDR ,then transfers them to IR.
Step 4: The execution phase of the instruction requires only one
control step to complete.

COA- Module 5
 Exercise

 What is the control

sequence for
execution of the
instruction
Add R1,
(R2)
including the
instruction fetch
phase? (Assume
single bus
architecture)

COA- Module 5 86
 The Processing Unit

1. Basic Processing
Cycle
2. Types of Operations
3. Control
Mechanisms 1. Hardwired
Q Who sets F_alu to
ADD? 2. Micro-
Programmed

8
7

COA- Module 5 87
Hardwired
Control

COA- Module 5
88
 3 Control Mechanism- Overview

 To execute instructions, the processor must have some

means of generating the control signals needed in the
proper sequence.
 Two categories: hardwired control and micro
programmed
control
 Hardwired system can operate at high speed; but with
little flexibility.

COA- Module 5 89
 Hardwired vs Microprogrammed
 Hardwired
 Use gates to generate signals
 Squeeze out the juice for performance(not flexible)
 Different logic styles possible
 Economical initially
 Small changeredesign
 Microprogrammed
 Store the control signals in the sequence
 Just read from the memory every clock cycle
 Expensive initially
 Additions done by simply changing the
microprogram in
control memory
 Diagnostics routine can be made available in
memory
COA- Module 5
 3.1 HARDWIRED APPROACH

 Final circuit is obtained by physically connecting

gates and flip flops
 Cost of control logic increases with system complexity

CO-Unit VI-Basic Processor COA- Module 5

Unit
Control Unit Organization

CLK Control
Clock step
counter

Extern
al
inputs
Decode
IR
r/
encode Conditio
r n
codes

Control signals

[Link] unit
organization.
COA- Module 5
92
 Hardwired Control -Separating
decoding/encoding
Clock Control
Rese
CLK
step
t
counter

Step decoder
Only one set
to 1 T_1
Ins_ T_n
1 Statu
s
IR Instruction Encoder Flag
decoder s
Conditio
Ins_
n
n
Codes
Ru
Z_in End
n
Q) Role of
COA- Module 5 Run ? 93
Decoder/encoder block is a combinational-circuit that
generates required control-outputs depending on state of
Step-decoder provides a separate signal line all
for its inputs.
each step
in the control sequence.
Similarly, output of instruction-decoder consists of a
separate line
for each machine instruction.
For any instruction loaded in IR, one of the output-lines INS1
through INSm is set to 1, And all other lines are set to
The input signals to encoder-block are combined to
generate the individual control- signals Yin, PCout, Add,
End and so on.

COA- Module 5 9
4
 3.1. Hardwired Control -Generation of control
signals
AD BRanch
Z_in = T_1 + T_6 . ADD + T_4 . D T_6 T_4
BR
time
slot

T_1

Z_i
n

COA- Module 5 95
This signal is asserted during time-slot T1 for all

instructions, during T6 for an Add instruction

The control H/W shown can be viewed as a state m/c that changes from one
during T4another
state to for unconditional branch
in every clock instruction
cycle, depending on the content of IR,the

conditional codes and the external inputs

When RUN=1, counter is incremented by 1 at the
end of every clock cycle.
When RUN=0, counter stops counting.
Sequence of operations carried out by this machine is
determined by wiring of logic elements, hence the name
“hardwired”.

COA- Module 5 9
6
Generation End control
signal
End = T_7 . ADD + T_5 . BR +(T_5 . N + T_4 . /N) .BRN+ . .
..

COA- Module 5 97
 3.1. Hardwired Control-Performance

 Performance is dependent on:

 Power of instructions
 Cycle time
 Number of cycles per instruction
 Performance improvement by:
 Multiple datapaths
 Instruction prefetching and
pipelining
 Caches

COA- Module 5
Complete CPU

Instruction Intege
Intege Floating-
Floating-
Intege Floating-
r point
unit r r point
point
unit
unit unit
unit
unit unit

Instructio Data
n Cach
Cache e

Bus
Interfac Processor/
e CPU

System
Main Bus Input/
Memor Outpu
y t
COA- Module 5
 A Complete Processor
 This has separate processing-units to deal with integer data and
 floating-point data.
 A data-cache is inserted between these processing-units & main-
memory.
 Instruction-unit fetches instructions
→ from an instruction-cache or
→ from main-memory when desired instructions are not already in
cache
 Processor is connected to system-bus & hence to the rest of
the computer by means of a bus interface
 Using separate caches for instructions & data is common
practice in
many processors today.
 A processor may include several units of each type to
increase the potential for concurrent operations

COA- Module 5 10
1
Micro programmed
Control

COA- Module 5
 3.2. Micro-programmed control

 All control bits are organized as memory

 Each memory location represents a control setting/word
 Control word (CW) consists of individual bits represent various control-
signals

(like Add, End, Zin).

 The control word represents unique combination of (0s and

1s)
 Memory words in micro routine are called micro-instructions.
 Micro-routines are sequences of micro-instructions
 Control stores for all micro-routines of the instruction set .
 Micro-program counter (µ PC) to read control words
sequentially Every time a new instruction is loaded into IR,
output of "starting address generator" is loaded into µPC.
Then, µPC is automatically incremented by clock, causing
COA- Module
successive microinstructions 5 read from CS.
to be
3.2. Micro-Programmed
Control Examples of Micro-
Instructions

Micro PC_in MAR_i Z_i

- .. n n
.
instructio
n
1 0 1 1
..
2 . 1 0 0
..
3 . 0 0 0
. .
.

COA- Module 5
 Microprogrammed Control

 Control signals are generated by a program similar to

machine language programs.
 Control Word (CW); microroutine; microinstruction

CO-Unit VI-Basic Processor COA- Module 5 105

Unit
Microinstructions for
Add (R3),R1

COA- Module 5 106

 Microroutine for the instruction Branch<0

 The previous organization cannot handle the situation when the

control unit is required to check the status of the condition codes
or external inputs to choose between alternative courses of
action.
 Use conditional branch microinstruction.

Address Microinstruction
0 PCout , MAR in , Read, Select4,Add,
1 Zin Zout , PCin , Yin , WMFC
2
MDRout , IRin
3 Branch to starting address of appropriate
microroutine
2. . . . . . . . If
. . N=0,
. . . . .then
. . . . branch
. . . . . .to
....................
.....................
5 microinstruction 0 Offset-field-of-
2
IRout , SelectY, Add, Zin Zout , PCin ,
6
End
2
Fig. Microroutine for the instruction
7
Branch<0.
COA- Module 5
107
 Micro programme Unit for Conditional
Branching
Extern
al
inputs
Starting
branch Conditio
IR and n
generat
address codes
or

Clock  PC

Contr
ol CW
store
Fig. Organization of the control unit to allow
conditional branching in the micro
program.
COA- Module 5
108
 Conditional
Branching
In case of conditional branching, microinstructions specify
which of the external inputs, condition-codes should be
checked as a condition for branching to take place.
The starting and branch address generator block loads a
new
address into µPC when a microinstruction instructs it to do
so .
To allow implementation of a conditional branch, inputs
to this block consist of
→ external inputs and condition-codes
→ contents of IR
µPC is incremented every time a new microinstruction is
fetched from
microprogram memory except in following
situations
i) When a new instruction is loaded into IR, µPC is loaded
with starting-address of microroutine for that
instruction.
ii) When a Branch microinstruction
COA- Module 5is encountered and 10
9
 Microinstructions

 A straightforward way to structure microinstructions is to

assign one bit position to each control signal.
 However, this is very inefficient.
 The length can be reduced: most signals are not
needed simultaneously, and many signals are
mutually exclusive.
 All mutually exclusive signals are placed in the same group in
binary coding.

COA- Module 5 110

 Some Drawbacks of microprogrammed
control
1) Assigning individual bits to each control-signal results in long
microinstructions because the number of required
signals is usually large.
2) Available bit-space is poorly used because
only a few bits are set to 1 in any given
microinstruction. Solution: Signals can be grouped
because
- Most signals are not needed simultaneously.
- Many signals are mutually exclusive.
Grouping control-signals into fields requires a little more hardware
because decoding-circuits must be used to decode bit patterns of
each field into individual control signals.
Advantage: This method results in a smaller control-store
(only 20 bits are needed to store the patterns for the
42 signals).
3) Having a separate microroutine for each machine instruction results
in a large total number of microinstructions and a large control-
store.
4) Execution time is longer because it takes more time to carry
out the required [Link]- Module 5 11
1
 Microprogrammed control
(contd..)
Microinstruction format
• Simple approach is to allocate one bit for each control signal
- Results in long microinstructions, since the number of control
signals
is usually very large.
- Few bits are set to 1 in any microinstruction, resulting in a
poor use of bit space.
• Reduce the length of the microinstruction by taking advantage of
the fact that most signals are not needed simultaneously, and many
signals are mutually exclusive. For example:
- Only one ALU function is active at a time.
- Source for a data transfer must be unique.
- Read and Write memory signals cannot be active
simultaneously.
• Group mutually exclusive signals in the same group.
• At most one microperation can be specified per group.
• Use binary coding scheme to represent signals within a group.

COA- Module 5
 Microprogrammed control (contd..)
Microinstruction format

Examples:

• If ALU has 16 operations, then 4 bits can be sufficient.

• Group register output signals into the same group, since only
one of these signals will be active at any given time (Why?)
If the CPU has 4 general purpose registers, then PCout, MDRout,
Zout,
Offsetout, R0out, R1out, R2out, R3out and Tempout can be placed
in a single group, and 4 bits will be needed to represent these.

COA- Module 5
 3.2. Micro-Programmed
Control Structure micro-
 instructions
Most simple organization: 1 bit per control signal
 However,
 Many bits needed (e.g., 80-120 bits)
 For many signals, only one is needed per cycle; hence they can be
grouped
 Coding is possible: e.g., an address instead of a single control bit
per
register
 Alternative approach to reduce the length of the microinstruction:
• Enumerate the patterns of the required signals in all microinstructions.
• Assign each meaningful combination of active control signals a unique
code.
• Code represents the microinstruction .
• Grouping control signals into fields requires a little more hardware:
 Decoding circuits are needed to decode patterns to individual control
signals.
 Cost of the additional hardware is offset by reduced number of bits
 in each microinstruction:
theReduces COA- Module 5
decoderthe size of the control 114
 store.
 3.2. Micro-Programmed
Control Forms of
organization
 Little coding: horizontal
organization
 Large words
 Little decoding logic
 Fast
 Much coding: vertical organization
 Small control store
 Much decoding logic
 Slower
 Mixed organization

COA- Module 5
3.2. Micro-Programmed Control
Horizontal/Vertical

F0 F1 F2 F3
Horizont
al
R0 R1 R2
R3

F0 F1

Decoder
Vertic
al
R0 R1 R2
R3

COA- Module 5
 3.2. Micro-Programmed
Control Sequencing

 Thus far only branch after fetch

 No sharing of micro-code between micro-routines
 Micro-subroutines lead to more efficient control
store

COA- Module 5
 3.2. Micro-Programmed
Control Multi-way branching

 Number of two-way branches

 disadvantage: slows down
 More than one branch address in micro-
instruction
 disadvantage: more bits required
 bit-ORing if specified branch address

COA- Module 5
3.2. Micro-Programmed
Control Example
branch
addres
s
xxx000 micro-
instruction
O
R
wyz part of
IR

xxxwyz

actual
branch
addres
s

COA- Module 5
 Mapping of Instruction

 Example
 Mapping 3-bit operation code to 7-bit
address

ADD of 0000
OP-codes Instructions
AND 0001
LDA 0010 Control
memory
Mapping bits 0 xxx 00 Address
0 000 00 ADD Routine

0 001 00 AND Routine

0 010 00 LDA Routine

COA- Module 5
 3.2. Micro-Programmed
Control
Example microroutine (1)
ADD (Rsrc)+, Rdst

Mod
e
IR OP code 010 Rsrc Rdst

11 8 4 3 0
10 7
Instruction bit 8: direct/indirect
Format bit 9,10: indexed (11)
autodecrement(
10)
autoincrement(0
1) register(00)

COA- Module 5
 3.2. Micro-Programmed Control
Example microroutine (2)
Address Micro-instruction

0 PC_out, MAR_in, Read, Set carry-in ALU, F_alu =

“ADD”, Z_in
Z_out, PC_in, Wait for use bits from IR
2 MFC
MDR_out, FETCH
foraddressing
3 μBranch{μPC101
IR_in (from PLA); mode
μPC_3{[not.IR_10].[not.IR_9].[IR_8]}
μPC_5,4[IR_10,9];
........................................................................................................
12
... Rsrc_out, MAR_in, Set carry-in ALU,Read, F_alu =
1 “ADD”, Z_in Z_out, Rscr_in
12 μBranch{μPC 170; μPC_0[not.IR_8]}, WMFC
2
12
17 MDR_out, MAR_in, Read,
3
0 WMFC MDR_out, Y_in
17 Rdst_out, F_alu = “ADD”, autoincreme
1
2 Z_in Z_out, Rdst_in, End nt
direc 17 indire
t 3
ct
COA- Module 5
3.2. Micro-Programmed
Control Micro branch
address
Mod
e
IR OP code 010 Rsrc Rdst

11 9 8 4 3
10 7 0

/IR10./
IR9.IR8

10
PL
A
1
0 0 1 0 1 0 0 0
1
12
1

COA- Module 5
3.2. Micro-Programmed
Control Micro branch
address
Mod
e
IR OP code 010 Rsrc Rdst

11 8 4 3
10 7 0

IR
8

17
0
PL
A
0 0 1 1 1 10 0
1
17
1
COA- Module 5
 Microprogram sequencing-

Simple microprogram sequencing:

• Load the starting address into PC when a new instruction is
loaded
into IR.
• Introduce some branching capability within the
microprogram through special branch microinstructions,
which specify the branch address.
Disadvantages of the simple approach:
• Large total number of microinstructions and large control
store.
• Most machines have several addressing modes, and many
combinations of instructions and addressing modes.
• Separate microroutine for each of these combinations produces a
lot of
• duplication of common parts.
• Share as much common code as possible.
• Sharing common code requires many branch instructions to
transfer COA- Module 5
 Microprogrammed control (contd..)
Microprogram sequencing

Consider the following instruction which adds the source

operand to the contents of register Rdst, and places the
results in register Rdst.
ADD src, Rdst

Assume that the source operand can be specified in the

following addressing modes:
- Register.
- Autoincrement
- Autodecrement
- Indexed.
- Indirect forms of the above methods.

COA- Module 5
 Start of instruction fetch.

ADD Rsrc, Rdst

Microroutines for all the instructions

COA- Module 5
Microprogrammed control (contd..)
Start of instruction fetch.
ADD Rsrc, Rdst

Microroutines for all the instructions

Microinstruction at address 170 is performed in

the register indirect mode.
Microinstruction at address 171 is performed in
the register direct mode.
Microinstruction 170 is bypassed if register
direct
mode is used.
One way to bypass microinstruction 170 is to
have the previous microinstruction specify
address 170, and then use an OR gate to
change the LSB of the address to 1.
This technique is called bit-ORing.

COA- Module 5
 Branch Address Modification Using Bit-ORing

The micro program in Figure 20 shows that branches are not

always made to a single branch address. This is a direct
consequence of combining simple micro routines by sharing
common parts. Consider the point labeled ∞ in the figure. At this
point, it is
necessary to choose between actions required by direct and
indirect addressing modes.
If the indirect mode is specified in the instruction, then the
microinstruction in location 170 is performed to fetch the
operand from the memory. If the direct mode is specified, this
fetch must be bypassed by branching immediately to location
171.
The most efficient way to bypass microinstruction 170 is to
have the preceding branch microinstructions specify the address
170 and then use an OR gate to change the least significant it
of this address to 1 if the direct addressing mode is involved.
This is known as the bit-ORing technique for modifying branch
addresses.
CO-Unit VI-Basic Processor COA- Module 5
 Alternative Approaches to the bit-
ORing
An alternative to the bit-ORing approach is to use two conditional
branch
microinstructions allocations 123,143, and 166.
Another possibility is to include two next address fields within a
branch microinstruction, one for the direct and one for the
indirect address modes. Both of these alternatives are inferior to
the bit-Oring technique.

COA- Module 5
 Microprogrammed control (contd..)
Microinstructions with the next-address field.

• Several branch microinstructions are required to enable sharing of

common code.
• The branch microinstructions do not perform any useful operation
related to data.
• They are required to determine the address of the next
microinstruction.
• They slow down the execution of the instruction.
• Ideally we need to assign consecutive addresses to all
microinstructions that are generally executed one after the other.
• Recall that the next microinstruction is determined by
incrementing the
microprogram counter.
• But due to the goal of sharing as much common code as
possible, this is not always possible.
• This leads to a significant increase in the branch instructions.

COA- Module 5
 Microprogrammed control (contd..)
Microinstructions with the next-address field.

• Powerful alternative is to include an address field as a part

of every microinstruction.
• The address field indicates the location of the next
microinstruction to be fetched.
• In effect, every microinstruction becomes a branch
microinstruction in
addition to its other function.
Disadvantages:
• Additional bits are required to specify the address field in every
instruction.
• Approximately one-sixth of the control store is devoted to
specifying the address.
Advantages:
• Separate branch instructions are virtually eliminated.
• Flexible scheme, very few restrictions in assigning
addresses to microinstructions.
COA- Module 5
 3.2. Micro-Programmed Control
Next-address field (1)

 Micro-instruction contains address next micro-

instruction
 Larger store needed
 Branch micro-instructions no longer needed

COA- Module 5
Next-address field
(2)
Status IR Conditio
flags n
codes

Decoding
circuits

micro-AR

Control

Next store micro-

address IR

Microinstruction
decoder

COA- Module 5
 Next-address field
 The microprogram discussed earlier requires several
branch microinstructions, which perform no useful
operation in the datapath.
 A powerful alternative approach is to include an
address field as a part of every microinstruction to
indicate the location of the next microinstruction to
be fetched.
 Pros: separate branch microinstructions are
virtually eliminated; few limitations in assigning
addresses to microinstructions.
 Cons: additional bits for the address field
(around 1/6)

COA- Module 5 13
5
3.2. Micro-Programmed
Control Example

F0 F1 F2 F3 F4 F5 F6 F7 F8

Field 0(8 Next address

bits): Register
Field 1(4 address_in
bits): Register
Field 2(4 address_out Other
bits): registers_in
Field 3(4 Function ALU
bits): : Read/Write/
Field 4(4 Nop Carry-in ALU
bits): WMFC
PLA/ORing
Field 5(2 bit) End
etc
Field 6(1
bit) : Field
7(1 bit) :
Field 8(1 bit)
: COA- Module 5 136
 Partial Format for the field encoded
Microinstructions
Microinstructi
on
F1 F2 F3 F4 F5 What is the price paid
for this scheme?
F1 (4 F2 (3 F3 (3 F4 (4 F5 (2
bits) bits) bits) bits) bits)
0000: No 000: No 000: No 0000: Add 00: No
transfer transfer transfer action
0001: PCo u t 001: PCin 001: MARin 0001: Sub 01: Read
• Each group
0010: MDRout 010: IRin 010: MDRin 10: Write
0011: Zout 011: Zin 011: TEMPin occupies a large
0100:
0101: R0
R1out 100:
101: R0in 100: Yin 1111: XOR enough field to
out
R1in
16 ALU
function
represent all the
0110: R2out
110: s signals.
0111: R3out
R2in • Most fields
1010:
TEMPout
111: must include one
R3in
1011: inactive code, which
OffseoF6
tut F7 F8 specifies no action.
•All fields do not have
F6 (1 F7 (1 F8 (1 to
bit) bit) bit) include inactive code.
0: 0: No 0: Require a little more
SelectY action Continue hardware
1: 1: WMFC 1: End
Select4
COA- Module 5 137
 3.2. Micro-Programmed
Control Organization
 Micro-program is often placed in ROM on CPU chip
 Some machines had writable control store, i.e. user
could change instruction set

COA- Module 5 138

 Further Discussions

 Prefetchin
g
 Emulation

COA- Module 5 13
9
 Prefetching
 Microprogrammed control leads to slower operating
speed because of the time it takes to fetch
microinstructions from the control store.
 To achieve faster operation, the next microinstruction
can
be prefetched while the current one is being executed.
 Execution time can be overlapped with the fetch time.
 the next microinstruction is pre-fetched while the
current one is being executed.
 Prefetching microinstructions presents some
difficulties:
 Status flags and the results of the current microinstruction
that is being executed are necessary to determine the
address of the next microinstruction.
 Straightforward prefetching may occassionally fetch a
wrong
instruction.
increased operation COA- Module 5 140
 Fetch must be repeated.
speed.
 Emulation
 The main function of microprogrammed control is to provide a
means for simple, flexible and relatively inexpensive
execution of machine instruction.
 Control offers the flexibility to add new instructions to the
instruction set of a processor.
 New microroutines need to be added to implement
the new instructions.
 Add to the instruction set of a given computer M1 an entirely new set
of instructions that is in fact the instruction set of a different
computer M2.
 Programs written in the machine language of M2 can be run on
M1 .
 M1 emulates M2.
 Emulation allows transition to new computer systems with
 minimal
E m udisruption.
l a t io n is easiest when the machines involved
ar ch i t e c t u re .
have similar
 Emulation allows us to replace obsolete equipment with
COA- Module 5
more up-to-date
Implementation of the Microroutine

Addres Microinstructi
s on

(octal)

00 PC , MAR in
, Read, 4 , Add, in
out
0 Select Z
00
1 Z , PC , IR, Y , WMFC
00 MDR
out
out
in
in
in
2
00  Branch PC  101 (from Instruction

3 { decoder);
 PC ];  PC  [IR  [IR 9 ]  [IR

5,4 10,
8 ]} 10 ]
[IR 9
, Read, 3
Select4,
12 Rsrc out , MAR in
1 Add, Z
in
12 Z , Rsrc
out in
2
12  Branch {   [IR 8 ]},
170;  PC 0

3 PC WMFC
17 MDR out , MAR , Read,
0 WMFC
in
17 MDR ,Y
out in
1
17 Rds out , , Add, in
2 t SelectY Z
17 Z , ,
3 Rdst End
out in

COA- Module 5
bit-ORing

COA- Module 5