William Stallings
Computer Organization
and Architecture
10th Edition
Chapter 5
Internal Memory & Chip Logic
Semiconductor Memory Types
Memory Category Volatility
Type
Volatile – must be
Random-Access Read-write
provided with a constant
Memory (RAM) memory
power supply
Read-only
Memory (ROM)
Read-only memory
Programmable
ROM (PROM)
Erasable PROM
Nonvolatile
(EPROM)
Electrically Read-mostly
Erasable PROM memory
PROM – small, written only once, special equipment is required for programming
(EEPROM)
In read-mostly-memory, the Read op are far more frequent than write op
EPROMFlash Memory
– all storage cells must be erased to same initial state by an ultraviolet light, it takes
20 min to perform, can be used multiple times
EEPROM – that can be written into at any time without erasing prior contents; only byte or
bytes addressed are updated. Write op takes longer time than read op, 100 microsec/byte
Semiconductor Memory
• RAM
—Misnamed as all semiconductor memory is
random access (as all of the types listed in the
previous table)
—Read/Write
—Volatile
—Temporary storage
RAM technology is dived into two technologies:
—Dynamic and Static
Memory Cell Operation
Select terminal – selects a memory cell for read/write operation
Control terminal – indicated read or write
For writing – data terminal provides an electrical signal that sets state of cell to 1 or 0
For reading – that terminal is used for output of cell’s state
Dynamic RAM
• DRAM is made with cells that stores data as charge
on capacitors, presence or absence of charge on a
capacitor is interpreted as a binary 1 or 0
• DRAM require periodic charge refreshing to
maintain data storage i.e. Charges leak
• Need refreshing even with power continuously
applied
• Simpler construction
• Smaller per bit
• Less expensive
• Need refresh circuits
• Slower
• Main memory
• Essentially analogue
—Level of charge determines value
Dynamic RAM Structure
- Here is an individual DRAM cell that
stores one bit
- Address line is activated when bit
value from this cell is to be read or
written
- Transistor acts as a switch (allows
current to flow) if a voltage is applied
to address line and (no current flows) if
no voltage is present on address line
- For write op, a voltage signal is
applied to bit line, (high for 1 and low
for 0), a signal on address line allowing
a charge to be transferred to capacitor
- For read op, when address line is
selected transistor turns on and charge
stored on capacitor is fed out onto a bit
line and to a sense amplifier, which
compares capacitor voltage to a
reference value, for 1 or 0
DRAM Operation
• Address line active when bit read or written
—Transistor switch closed (current flows)
• Write
—Voltage to bit line
– High for 1 low for 0
—Then signal address line
– Transfers charge to capacitor
• Read
—Address line selected
– transistor turns on
—Charge from capacitor fed via bit line to sense
amplifier
– Compares with reference value to determine 0 or 1
—Capacitor charge must be restored
Static RAM
Static RAM
• Bits stored as on/off switches
• No charges to leak
• It holds its data as long as power is
supplied to it
• More complex construction
• Larger per bit
• More expensive
• Does not need refresh circuits
• Faster
• Cache
• Digital
—Uses flip-flops logic-gate
Static RAM Structure
• Transistor arrangement
gives stable logic state
1,0
• State 1 (logical 1 store)
— point C1 is high &
point C2 is low
— T1 T4 off, T2 T3 on
• State 0 (logical 0 store)
— C2 high, C1 low
— T2 T3 off, T1 T4 on
• Address line controls
two transistors T5, T6,
when signal is applied to
this line, T5 T6 are
switch on, allowing
read/write op
• Write – apply value to B
& its compliment to B*
• Read – bit value is read
from line B
SRAM v DRAM
• Both volatile
—Power needed to preserve data
• Dynamic cell
—Simpler to build, smaller
—More dense (i.e., smaller cell = more cells per unit
area)
—Less expensive
—Needs refresh
—Larger memory units (used for main memory)
• Static cell
—Faster than DRAMs
—Used for Cache memory (both on & off chip)
Read Only Memory (ROM)
• Permanent storage
—Nonvolatile
• Microprogramming (see later)
• Library subroutines
• Systems programs (BIOS)
• Function tables
Types of ROM
• Written during manufacture
—Very expensive for small runs
• Programmable (once)
—PROM
—Needs special equipment to program
• Read “mostly”
—Erasable Programmable (EPROM)
– Erased by UV
—Electrically Erasable (EEPROM)
– Takes much longer to write than read
—Flash memory
– Erase whole memory electrically
Organisation in detail (Chip Logic)
• A 16Mbit chip can be organised as a 2048
x 2048 x 4bit array , (i.e., 4 M x 4)
—Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin devoted to addressing doubles
the number of rows and columns, so size of chip
memory grows by a factor of 4
(4) Additional 11
Fig: Typical 16-Mbit DRAM address lines select one
(4M x 4) of 2048 columns of 4-
bits, Four data lines are
WE and OE pins determine whether used for input/output of
a write/read op is performed 4-bits to and from data
buffer.
i.e. 22 required address
lines are passed through
select logic external to
chip & multiplexed onto
11 address lines
(1) 4-bits are read/written at a time, A 16Mbit chip can be organised as a 2048 x 2048 x 4bit
array, (2) Elements of array are connected by both horizontal-row (select terminal) and
vertical-column (data-in/sense terminal) lines, (3) Address lines supply address of word to be
selected, here 11 address lines are needed to select one of 2048 rows. These 11 lines are fed
into a row decoder, which has 11 lines of input & 2048 lines for output, decoder activates a
single one of 2048 outputs depending on bit pattern on 11 input lines (211 = 2048)
Chip Refreshing (DRAM)
• All DRAMs require a refresh operation
• Disable DRAM chip while all data cells are
refreshed
• Refresh Counter steps through all of rows values
• For each row, output lines from refresh counter
are supplied to row decoder & RAS line is
activated
• The data are Read-out & Written-back into same
location
• This causes each cell in the row to be refreshed
• Takes time
• Slows down apparent performance
Chip Packaging
For a 16-Mbit chip
organized as (4M x 4), different
from ROM chip, because a
RAM can be updated, the data
pins are input/output.
WE & OE pins indicate
whether this is a write or read
op. Because DRAM is accessed
by row and column, and address
is multiplexed only 11 address
pins are needed to specify 4M
row/column combinations (211 x
211 = 4M)
No Connect (NC) pin is
provided, so that there are an
even no. of pins
Example: Chip Logic
• An 8-Mbit chip can be organised as a
(1Mx 8bit) array , (i.e., 1 M x 8)
— Dedicated - number of address pins
– Generate row address only
– 20 pins to address (220= 1M)
–A
Fig: Typical 8-Mbit DRAM
(1M x 8)
WE and OE pins
determine
whether a
write/read op is
performed, CE,
Chip Enable
(1) 4-bits are read/written at a time, A 16Mbit chip can be organised as a 2048 x 2048 x 4bit
array, (2) Elements of array are connected by both horizontal-row (select terminal) and
vertical-column (data-in/sense terminal) lines, (3) Address lines supply address of word to be
selected, here 11 address lines are needed to select one of 2048 rows. These 11 lines are fed
into a row decoder, which has 11 lines of input & 2048 lines for output, decoder activates a
single one of 2048 outputs depending on bit pattern on 11 input lines (211 = 2048)
Chip Packaging
For an 8-Mbit EPROM chip organized as
(1M x 8), the package includes 32-pins, which
support following signal lines:
address of the word being accessed. For 1M
words, a total of 20 (220 = 1M) pins are needed
(A0 – A19).
data to be read out, consisting of 8 lines
(D0 – D7).
Power supply to chip (Vcc).
A ground pin (Vss).
A chip enable (CE) pin, to connect to more
than one memory chip over same address bus.
A program voltage (Vpp) that is supplied
during programming (write operations).
Error Correction
• Hard Failure
—Permanent defect
• Soft Error
—is a Random, non-destructive event alters
contents of one or more memory cells without
damaging memory, caused by power supply, or
alpha particles in materials
• Detected using Hamming error correcting
code
- When data are to be read into memory, a calculation is performed on data to
produce a code. Both code and data are stored, thus, if an M-bit word of data
is to be stored, and the code is of length K bits, then actual size of stored
word is (M + K) bits
- When previously stored word is read out, code is used to detect error & then
correct the errors
Error detection & correction using Hamming code
-Hamming Code on 4-bit
words (M = 4), with three
A B A B intersecting circle, & seven
compartments, 4 data bits are
1 1 1 0 placed at inner comp Fig(a), &
(a) 1 (b)
1 1 other are filled with parity bits
0 1 0
0 -Each parity bit is chosen so
that total no. of 1s in its circle
C C is even Fig(b), As circle A
includes three data 1s, parity
A B A B bit in that circle is set to 1
-If an error changes one of
1 1 0 1 1
(c) 0 data bits Fig(c), it is easily
1 (d) 1
0 0 0 0 found, By checking parity bits,
0 discrepancies are found in
0
circle A & C but not in B, i.e.
C C only one comp is in A&C but
not B, correcting error by
changing that bit
e.g., Hamming Code for 8-bit words
- For Hamming Code how long the code must be. An error could occur on any of
M data bits or K check bits, we must have (2k – 1) > = (M + K)
- E.g., for a word of 8 data bits (M = 8), we have
• K = 3: 23 -1 < 8+3
• K = 4: 24 -1 > 8+4 , (thus 8-data bits require 4-check bits, total of 12-bits word)
Check
C1 = D1 * D2 * D4 * D5 * D7 bits are
C2 = D1 * D3 * D4 * D6 * D7 calculated
as
C4 = D2 * D3 * D4 * D8
C8 = D5 * D6 * D7 * D8
Bit
positio 12 11 10 9 8 7 6 5 4 3 2 1
n
Positio
n no 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
Data
bit D8 D7 D6 D5 D4 D3 D2 D1
Check
bit C8 C4 C2 C1
e.g. C1 = D1 (0011) * D2 (0101) etc select all where first binary digit is 1 out of 4-bits
e.g., Hamming Code for 8-bit words
C1 = D1 , D2 , D4 , D5 , D7 (3, 5, 7, 9, 11 bit positions check with parity bit C1)
C2 = D1 , D3 , D4 , D6 , D7 (3, 6, 7, 10, 11 check with parity bit C2)
C4 = D2 , D3 , D4 , D8 (5, 6, 7, 8 with C4) D8 D7 D6 D5 D4 D3 D2 D1
C8 = D5 , D6 , D7 , D8 ; we have an 8-bit word is 0 0 1 1 1 0 0 1
Originally Sent Received As
C1 = 1*0*1*1*0 =1 C1 = 1*0*1*1*0 =1
C2 = 1*0*1*1*0 =1 C2 = 1*1*1*1*0 =0
C4 = 0*0*1*0 =1 C4 = 0*1*1*0 =0
C8 = 1*1*0*0 =0 C8 = 1*1*0*0 =0
Suppose data bit 3 sustain an error, changed from 0 to 1, when check bits are recalculated,
When new check bits are compared with old check bits,
Resultant word is formed: C8 C4 C2 C1
i.e. result is 0 1 1 0 indicating that bit position 6, 0 1 1 1
which contains data bit 3, is in error 0 0 0 1 *
-------------------------------
0 1 1 0
e.g., Hamming Code for 8-bit words
Bit
position 12 11 10 9 8 7 6 5 4 3 2 1
Position 110 101
number 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
0 1
Data bit D8 D7 D6 D5 D4 D3 D2 D1
Check bit C8 C4 C2 C1
Word
stored as 0 0 1 1 0 1 0 0 1 1 1 1
Word
fetched 0 0 1 1 0 1 1 0 1 1 1 1
as
Position 110 101
number 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001
0 1
Check bit 0 0 0 1
Table : Single-error-correcting (SEC) & Check Bit Calculation
Hamming (DED) Code
0 0 0 1 1 0 1
(a) 1 (b) (c)
1 1 0
0 1 0 1 0
0 0
1 0 1 1 0 1 0
(d) 1 1
0 (e) 0 (f) 0
1 0 1 1 1 1
0 0 0
Increase in Word length with Error Correction
Single-Error
Single-Error
Correction/ Double-
Correction
Error Detection
Data Check % Increase % Increase
(Overhead) Check Bits (Overhead)
Bits Bits
8 4 50 5 62.5
16 5 31.25 6 37.5
32 6 18.75 7 21.875
64 7 10.94 8 12.5
128 8 6.25 9 7.03
256 9 3.52 10 3.91
Increase in Word length with Error Correction
How is the syndrome for the Hamming Code interpreted? Suppose a 12-bit data word
stored in memory is 101000101101. Using the Hamming algorithm, determine what check
bits would be stored in memory with the data word. Show how you got your answer.
• Assume a stack-oriented processor that includes the stack operations
PUSH and POP. Arithmetic operations automatically involve the top one
or two stack elements. Begin with an empty stack. What stack elements
remain after the following instructions are executed?
• PUSH 4
• PUSH 7
• PUSH 8
• ADD
• PUSH 10
• SUB
• MUL
• PUSH 9
• ADD
Question…
Assume a stack-oriented processor that includes the stack operations
PUSH and POP. Arithmetic operations automatically involve the top
one or two stack elements. Begin with an empty stack. What stack
elements remain after the following instructions are executed?
•PUSH 4
•PUSH 7
•PUSH 8
•ADD
•PUSH 10
•SUB
•MUL
•PUSH 9
•ADD
Synchronous DRAM (SDRAM)
• Access is synchronized with an external
clock
• Address is presented to RAM
• RAM finds data (CPU waits in conventional
DRAM)
• Since SDRAM moves data in time with
system clock, CPU knows when data will
be ready
• CPU does not have to wait, it can do
something else
• Burst mode allows SDRAM to set up
stream of data and fire it out in block
IBM 64Mb SDRAM