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Optimizing Placement in Physical Design

The document outlines the placement stage in physical design, detailing the flow and techniques involved, such as initial placement, legalization, and timing optimization. It emphasizes the use of ICC2 commands for various processes, including high fanout net synthesis and scan chain reordering, to enhance performance and reduce congestion. Overall, the document highlights the importance of optimizing placement for improved power, performance, and area (PPA).

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R K
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23 views14 pages

Optimizing Placement in Physical Design

The document outlines the placement stage in physical design, detailing the flow and techniques involved, such as initial placement, legalization, and timing optimization. It emphasizes the use of ICC2 commands for various processes, including high fanout net synthesis and scan chain reordering, to enhance performance and reduce congestion. Overall, the document highlights the importance of optimizing placement for improved power, performance, and area (PPA).

Uploaded by

R K
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Placement Stage in Physical

Design
Detailed Flow with ICC2
Implementation and Optimization
Techniques
Placement Flow - Overview
• - Initial Placement
• - Legalization
• - Timing & Congestion Runs
• - HFNS (High Fanout Net Synthesis)
• - Multi-bit Flop Conversion
• - Scan Chain Reordering
• - Tie Cell Insertion
• - Final Timing & Congestion Optimization
Initial Placement
• - Cells placed based on logical connectivity
• - Focus on reducing wirelength and congestion
• - ICC2 Command: initial_place
Legalization
• - Align cells to legal rows, remove overlaps
• - Ensure standard cell rows are respected
• - ICC2 Command: place_opt -legalize_only
Timing & Congestion Optimization
• - Perform multiple runs for timing and
congestion
• - Spread congested regions and fix critical
paths
• - ICC2 Command: place_opt -congestion -
timing
High Fanout Net Synthesis (HFNS)
• - Buffer trees for high fanout nets (e.g. reset,
clock enable)
• - Reduce skew and improve transition
• - ICC2 Command: set_hfn_strategy, apply_hfn
Multi-bit Flop Conversion
• - Converts multiple single-bit flops to multi-bit
• - Saves area and clock power
• - ICC2 Command: create_multibit_flops
Scan Chain Reordering
• - Optimize scan chains for routability and
minimal path length
• - ICC2 Command: optimize_scan_chain
Tie Cell Insertion
• - Tie unused inputs to known voltage levels
• - Prevents floating inputs and reduces leakage
• - ICC2 Command: insert_tie_cells
Global Route Congestion Analysis
• - Estimate routing congestion after placement
• - Guide optimization efforts
• - ICC2 Command: report_congestion
Path Grouping & Bounds
• Basically they were classified into 2 types there are:
1. Move Bound
2. Group Bound
1. Move Bounds: Bounds which are used group the cells together
to reduce the wire length and achieve better timing of your design
.Here we can decide the area to allocated to bound and where to
place them also we can decide .

2. Hard Bound
3. Soft Bound
4. Exclusive Bound

2. Group Bound: Bounds that tool it self decides the area of the
bound but here tool itself decides its location where to keep
Hard Bound
Diamond Bound
Dimensionless Bound
- ICC2: create_bounds tu
Path Grouping
Path Grouping: It is process of Organizing the timing paths
into logical sets.
It helps us to analyze the critical paths in the design.
By clearing the WNS we will achieve the better TNS in the
circuit
Command : group_path –from <start_point> -to <end_point> -
name <path_name> -weight <value>
Summary
• - Placement involves multiple critical sub-
stages
• - Tools like ICC2 enable detailed control at
each stage
• - Optimizing placement leads to better PPA
and routability

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