Integrated circuits
ELC 412 Level 4
Digital Introduction
Digital IC building transfer Voltage
block characteristics
NMOS, PMOS and Noise Margin
CMOS Fall time, rise time
Digital Integrated and Propagation
Circuits building block time delay
Fan in and Fan out
Power and Energy
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EE141 Integrated Circuits 2nd Introduction
CMOS configuration
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EE141 Integrated Circuits 2nd Introduction
DC Operation
Voltage Transfer Characteristic
V(y)
VOH = f(VOL)
V f
OH
V(y)=V(x)
VOL = f(VOH)
VM = f(VM)
VM Switching Threshold
V OL
V OL V V(x)
OH
Nominal Voltage Levels
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Mapping between analog and digital signals
V
V
out
“ 1” OH
V Slope = -1
V OH
IH
Undefined
Region
V
IL
Slope = -1
V
“ 0” V OL
OL
V V V
IL IH in
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EE141 Integrated Circuits 2nd Introduction
Definition of Noise Margins
"1"
V
OH
NM H Noise margin high
V
IH
Undefined
Region
NM L V
V
OL
IL Noise margin low
"0"
Gate Output Gate Input
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EE141 Integrated Circuits 2nd Introduction
Fan-in and Fan-out
M
N
Fan-out N Fan-in M
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EE141 Integrated Circuits 2nd Introduction
Input Characteristics of the 8086/8088
Logic Voltage Current
0 V ILmax = 0.8 V I ILmax = 10 uA
Fan-Out of a device is the maximum
1 V IHmin = 2.0 V I IHmax = 10 uA
number of similar devices that can be
connected on the output of that device
without any problems.
Output Characteristics of the 8086/8088
The Fan-Out is limited by the current
Logic Voltage Current
sink of the device (Fan-Out = IOLmax 0 V OLmax = 0.45 V I OLmax = 2.0 mA
Device/IILmax Load)
1 V OHmin = 2.4 V I OHmax = -400 uA
For example the IOLmax of the 8088
is 2 mA and the IILmax of the 74LS Recommended Fan-Out of the 8086/8088
Family I SINK I SOURCE Fan-Out
family is 0.4 mA. Thus the fan out
TTL (74) -1.6 mA 40 uA 1
is 2.0/0.4 = 5. TTL (74LS) -0.4 mA 20 uA 5
The noise immunity (VILmax- VOLmax) . TTL (74ALS) -0.1 mA 20 uA 10
The noise immunity of the 8088 is TTL (74F) -0.5 mA 25 uA 10
CMOS (74HC) -10 uA 10 uA 10
0.8-0.45=0.35V.
CMOS (CD4) -10 uA 10 uA 10
NMOS -10 uA 10 uA 10
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EE141 Integrated Circuits 2nd Introduction
The Ideal Gate
V out
Ri =
Ro = 0
Fan out =
g=
g=
V in
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EE141 Integrated Circuits 2nd Introduction
An Old-time Inverter
5.0
4.0 NM L
3.0
(V)2.0
out VM
V
NM H
1.0
0.0 1.0 2.0 3.0 4.0 5.0
Vin (V)
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EE141 Integrated Circuits 2nd Introduction
Rise time-Fall time
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Delay Definitions
V in
50%
tpHL tpLH
V out
90%
50%
10% t
tf tr
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Regenerative Property
v0 v1 v2 v3 v4 v5 v6
A chain of inverters
v0
V (Volt)
1 v1
v2
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Simulated response 0 2 4 6 8 10
t (nsec)
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EE141 Integrated Circuits 2nd Introduction
Ring Oscillator
v0 v1 v2 v3 v4 v5
v0 v1 v5
T = 2 tp N
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EE141 Integrated Circuits 2nd Introduction
A First-Order RC Network
R
vout
vin C
tp = ln (2) = 0.69 RC
Important model – matches delay of inverter
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Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
1 t T Vsupply t T
Pave p (t )dt isupply t dt
T t T t
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Energy and Energy-Delay
Power-Delay Product (PDP) is the average energy
consumed by the gate per switching event;
E = Energy per operation = Pav tp
Energy-Delay Product (EDP) =
quality metric of gate = E tp
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A First-Order RC Network Vdd
E0->1 = C LVdd2
R PMOS i
vout supply
A1 NETWORK
vAinN CVLout CL
NMOS
NETWORK
T T Vdd
E = P t dt = V i t dt = V C dV = C V 2
0 1 dd sup ply dd L out L dd
0 0 0
T T Vdd
t dt = V t dt = C V 1 2
E = P i dV = --- C V
ca p cap out ca p L out out 2 L dd
0 0 0
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