ARCHITECTURE
OF 8086
Architecture
■ 2 Parts
– Bus Interface Unit(BIU)
– Execution Unit(EU)
BIU - Functions
■ Fetches instruction of data from memory
■ Write data to memory
■ Read data from I/O ports
■ Write data to I/O ports
■ Generate 20 - bit physical address for memory access
BIU – Functional Parts
1. Segment Register
2. Instruction Pointer(IP)
3. Instruction Queue
4. Address Generation Unit
1. Segment Register
– 16 – bit register
– Stores base address of segments
– CSR, DSR, SSR, ESR
2. Instruction Pointer
IP
– 16 –bit register
– Stores the address of next instruction to be executed
– Its content is automatically incremented as the execution of next instruction takes
place
3. Instruction Queue
– 6 byte long
– FIFO
– When EU is executing an instruction at the same time BIU fetches machine code of
next instruction to be executed
– Pre decoded instruction byte queue
4. Address Generation Unit
– Generates 20 – bit physical address from 16 – bit segment register & 16 – bit offset
register
EU - Functions
■ Fetches instructions of data from BIU
■ Decodes instruction
■ Execute instruction
■ EU contains control circuitry to perform various internal operations
EU– Functional Parts
1. GPRs (General Purpose Registers)
2. Pointers & Index Registers
3. ALU
4. Flag Register
5. Timing & Control Unit
6. Decoding Unit
■ General Purpose Registers
– AX, BX, CX, DX
– 16 – bit registers
– Hold temporary value of intermediate result
■ Pointers & Index Registers
– Pointer Reg SP, BP
– Index Reg SI, DI
■ Flag Register
– 16 – bit register behave like flipflop
– Divided into 2 parts
■ Condition code/status flag
■ Machine control flags
■ ALU
– 16 – bit ALU
– Perform arithmetic & logic operations
– 8 – bit & 16 – bit ALU operation
■ Timing & Control Unit
– Direct all internal operations
– Responsible for generation of control signal
■ Decoding Unit
– Decodes the opcode byte fetched from the instruction byte and
send to control circuit for execution
EU - General Purpose Registers
■ Accumulator Register (AX)
– Consists of two 8 – bit registers AH, AL
– Combined together as AX for 16 – bit operation
– AL Low order byte of the word
– AH High order byte
EU - General Purpose Registers
■ Base Register (BX)
– Consists of two 8 – bit registers BH, BL
– Combined together as BX for 16 – bit operation
– BL Low order byte of the word
– BH High order byte
EU - General Purpose Registers
■ Counter Register (CX)
– Consists of two 8 – bit registers CH, CL
– Combined together as CX for 16 – bit operation
– CL Low order byte of the word
– CH High order byte
– Instruction such as SHIFT, ROTATE and LOOP use the content of CX
as a counter
EU - General Purpose Registers
■ Data Register (DX)
– Consists of two 8 – bit registers DH, DL
– Combined together as DX for 16 – bit operation
– DL Low order byte of the word
– DH High order byte
Flag Register
■ 16 – bit
■ Indicates some conditions produced by the execution of an
instruction
■ 9 of the 16 are active flags and remaining 7 are
undefined
■ 6 flags indicates some conditions – status flags
■ 3 flags – control flags
Flag Register
Overflow Carry
Direction Parity
Interrupt Flag Auxiliary Carry
Trap Zero
6 are status flags
Sign
3 are control flag
16
■ Overflow Flag (OF)
– Set if an overflow occurs
– This flag will be set (1) if the result of a signed operation is too large to fit in the
number of bits available to represent it, otherwise reset (0).
– Eg: Addition of two signed numbers, if the result overflows into the sign bit
■ Direction Flag (DF)
– Used by string manipulation instructions
– If flag bit is ‘0’ string is processed beginning from lowest to the highest address
(autoincrementing mode)
– Otherwise, string is processed from highest address to lowest address
(autodecrementing order)
■ Interrupt Flag (IF)
– Used to enable the interrupt
– 1 microprocessor is capable of handling the interrupt
– 0 any interrupt raised while execution of instruction will not be handled by
microprocessor
■ Trap Flag (TF)
– 1 Processor enters in a single step execution mode
– Trap interrupt is generated after execution of each instruction
■ Carry Flag (CF)
– 1 -> when there is carry out of MSB in case of addition or a
borrow in case of subtraction
■ Sign Flag (SF)
– 1 –> when result is negative
– MSB of result represents sign
■ Zero Flag (ZF)
– 1 –> when result is zero
■ Auxiliary Carry (AC)
– 1 -> if there is a carry from lowest nibble
■ Parity Flag (PF)
– 1 -> if lower byte of result contains even number of 1’s
– 0 -> odd number of 1’s
1. 4 2H 1. 3 7H
+2 3 H +2 9 H
6 5H 6 0H
0100 0010 0011 0111
0010 0011 0010 1001
0110 0101 0110 0000
OF SF ZF AC PF CF OF SF ZF AC PF CF
0 0 0 0 1 0 0 0 0 1 1 0
1. 4 2H
+4 3 H
8 5H
0100 0010
0100 0011
1000 0101
OF SF ZF AC PF CF
1 1 0 0 0 0