Introduction to Microcontrollers

• Computers have only been with us for a few decades but

their impact (direct or indirect) on our lives is profound.
• Usually these are supposed to be just data processors
performing exhaustive numeric operations. But there
presence is unnoticed at most of the places; like
– At supermarkets in Cash Registers, Weighing
Scales, etc.
– At home in Ovens, Washing Machines, Alarm
Clocks, etc.
– At play in Toys, VCRs, Stereo Equipment, etc.
– At office in Typewriters, Photocopiers, Elevators,
etc.
– In industry in Industrial Automation, safety
systems, etc.
– On roads in Cars, Traffic Signals, etc.

[Link] ; 1
 Microcontrollers
• Computers can be divided into following two
main types depending on their function
– General purpose (Not Transparent)
– Special purpose (Transparent)
• Microcontrollers are more suitable for special
purpose devices.
• Microcontroller is a device similar to
microprocessor but includes more circuitry in the
same chip.

[Link] ; 2
 Terminology
• A computer is defined by two main qualities
– The ability to be programmed to operate on data
without human intervention
– The ability to store and retrieve data.

• Computers also have peripheral devices to

communicate with outside world.

[Link] ; 3
[Link] ; 4
[Link] ; 5
 Central Processing Unit (CPU)
• Brain of the computer system, administers
all activity in the system and performs all
operations on data.
• Continuously performs two operations:
fetching and executing instructions.
• Understand and execute instructions
based on a set of binary codes called the
instruction set.
[Link] ; 6
 Machine Cycle
To execute an instruction -the processor must:
1) Fetch the instruction from memory 2) Decode
the instruction 3) Execute the instruction 4) Store
the result back in the memory. These four steps
refer to Machine Cycle.
Generally one machine cycle = X clock cycles
("X" depends on the particular instruction being
executed). Shorter the clock cycle, lesser the
time it takes to complete one machine cycle, so
instructions are executed faster. Hence, faster
the processor.
[Link] ; 7
 Fetching & Executing An Instruction
• Fetching involves the following steps:
– Contents of PC are placed on address bus
– READ signal is activated
– Data (instruction opcode) are read from RAM and placed on
data bus
– Opcode is latched into the CPU’s internal instruction register
– PC is incremented to prepare for the next fetch from memory
• Execution involves decoding the opcode and
generating control signals to gate internal registers in
and out of the ALU and to signal the ALU to perform
the specified operation.
[Link] ; 8
 The Buses: Address, Data, &
Control
• A bus is a collection of wires carrying information with a
common purpose.
• For each read or write operation, the CPU specifies the
location of the data or instruction by placing an address
on the address bus, then activates a signal on the
control bus indicating whether the operation is read or
write.
• Read operations retrieve a byte of data from memory at
the location specified and place it on the data bus. CPU
reads the data and places it in one of its internal
registers.
• Write operations put data from CPU on the data bus
and store it in the location specified.

[Link] ; 9
 The Buses (contd.)
• Address bus carries the address of a specified location.
For n address lines, 2nlocations can be accessed. E.g.,
A 16-bit address bus can access 216 = 65,536 locations
or 64K locations (210 = 1024 = 1K, 26 = 64).
• Data bus carries information between the CPU and
memory or between the CPU and I/O devices.
Computers spend up to two-thirds of their time simply
moving data, so the number of lines of the data bus is
important for overall performance. This limitation by
width of data bus is a bottleneck even with a vast
amount of memory on the system and a high speed
CPU. 16-bit computer means…?
• Control bus carries control signals supplied by the CPU
to synchronize the movement of information on the
address and data bus.
[Link] ; 10
 Input/Output Devices
• I/O devices or computer peripherals provide the path for
communication between the computer system and the real world.
Three main types:
– Mass Storage Devices (Hard disk, magnetic tape, CD-ROM,
etc.)
– Human Interface (Keyboard, mouse, joystick, CRT, printer,
speaker, etc.)
– Control/Monitor devices (Phototransistors, sensors,
thermostats, switches, motors, relays, etc.)
• Control devices are outputs, or actuators, that can affect the world
around them when supplied with a voltage or current.
• Monitoring devices are inputs, or sensors, that are stimulated by
temperature, pressure, light, motion, etc. and convert this to voltage
or current read by the computer.
The interface circuitry converts the voltage or current to binary
data, or vice versa.

[Link] ; 11
 Microprocessors Vs.
Microcontrollers
• Microprocessor is a single chip CPU, microcontroller contains, a CPU and
much of the remaining circuitry of a complete microcomputer system in a
single chip.
• Microcontroller includes RAM, ROM, serial and parallel interface, timer,
interrupt schedule circuitry (in addition to CPU) in a single chip.
– RAM is smaller than that of even an ordinary microcomputer, but
enough for its applications.
– Interrupt system is an important feature, as microcontrollers have to
respond to control oriented devices in real time. E.g., opening of
microwave oven’s door cause an interrupt to stop the operation.
(Most microprocessors can also implement powerful interrupt schemes, but
external components are usually needed.)
• Microprocessors are most commonly used as the CPU in microcomputer
systems. Microcontrollers are used in small, minimum component designs
performing control-oriented activities.
• Microprocessor instruction sets are “processing intensive”, implying
powerful addressing modes with instructions catering to large volumes of
data. Their instructions operate on nibbles, bytes, etc. Microcontrollers have
instruction sets catering to the control of inputs and outputs. Their
instructions operate also on a single bit. E.g., a motor may be turned ON
and OFF by a 1-bit output port. [Link] ; 12
 Gains and Losses
• Gains: Reduced component count in a
circuit, high degree of integration, shorter
development time, lower manufacturing
cost, lower power consumption, higher
reliability, etc.
• Losses: Some situations (very few)
require extremely fast response to events
are poorly handled by the microcontrollers.

[Link] ; 13
 Architecture(Hardware)Summary
The 8051
•A Microcontroller derivative family based on the
8051 core.
•A Microcontroller because a one-chip system can
be made with the one chip containing:
– Program & Data Memory
–I/O Ports
–Serial Communication
–Counters/Timers
–Interrupt Control logic
–A-to-D and D-to-A converters

[Link] ; 14
 MCS-51 Family Overview
• Term 8051 refers to MCS-51 family of microcontroller
ICs by Intel Corp. (From 8031-8752)
• Features are summarized below:
– 8 Bit data path and ALU.
– Easy interfacing.
– 12 to 30 MHz versions available. (1 µsec to 400 ns
for single cycle instructions).
– Full instruction set including:
Multiply and Divide.
Bit set, reset, and test (Boolean instructions).
– Variety of addressing modes.

[Link] ; 15
Hardware Features of the 8051
-0K (8031), ROM 4K (8051), EPROM 4K (8751) –RAM
128 bytes (8XY1), 256 bytes (8XY2) (where X= 0 or 7
&Y=3 or 5)
–Four 8-bit I/O Ports (P0-P3)
–Two 16-bit Timers/Counters (T0 &T1)
–Serial I/O Port
–Boolean Processor (Operates on Single Bits)
–210 bit-addressable locations
–Oscillator & Clock Circuit

[Link] ; 16
[Link] ; 17
[Link] ; 18
8051 has 4 Bus Control Signals
• PSEN (pin 29): (Program Store Enable) enables external
program (code) memory. Usually connected to EPROM’s
output enable (OE). It pulses low during fetch stage of an
instruction. It remains high while executing a program
from internal ROM.
• ALE (pin 30): (Address Latch Enable) used for
demultiplexing the address and data bus when port 0 is
used as the data bus and low-byte of address bus.
• EA (pin 31): (External Access) high to execute programs
from internal ROM and low to execute from external
memory only.
• RST (pin 9): (RESET) master reset of 8051.

[Link] ; 19
 Reset
• External reset is asynchronous to the internal clock.
• RST pin must be high for at least two machine cycles while the
oscillator is running.
• Internal RAM is not affected by reset.
• Reset sets PC to 0000H.
• Typical circuits:

[Link] ; 20
 8051 Oscillator & Power Pins
• Pins 18 and 19 are the oscillator pins to connect
the crystal of nominal frequency 12 MHz.
• Pin 40 is for +5V and pin 20 is for GND.

[Link] ; 21
 I/O Ports
-Four 8-bit I/O ports.
-Most have alternate functions.
-Bi-directional.

[Link] ; 22
 Port 0 (pin 32-39)
- Dual purpose I/O port.
-In min. component design, it is used as a
general purpose I/O port.
-In larger designs with external memory, it
becomes a multiplexed data bus:
– Low byte of address bus, strobed by ALE.
– 8-bit instruction bus, strobed by PSEN.
– 8-bit data bus, strobed by WR and RD.
[Link] ; 23
 Port 1 (pin 1-8)
-As an I/O port: Standard bi-directional port
for interfacing to external devices as
required for I/O.
-Alternate functions: Only on some
derivatives.

[Link] ; 24
 Port 2 (pin 21-28)
-Dual purpose I/O port.
-As an I/O port: Standard bi-directional
general purpose I/O port.
-Alternate functions: High byte of address
bus for external program and data memory
accesses.

[Link] ; 25
 Port 3 (pin 10-17)
-Dual purpose I/O port.
-As an I/O port: Standard bi-directional general purpose I/O port.
-Alternate functions:

Serial I/O -TXD, RXD

Timer clocks -T0, T1
Interrupts -INT0, INT1
Data memory -RD, WR

[Link] ; 26
 Addressing Space
-64K x 8 ROM -External Program Memory.
(Enabled via PSEN)
-64K x 8 RAM -External Data Memory.
(Enabled via RD and WR)
-256 x 8 RAM -Internal Data Memory.
-128 x 8 Special Function Registers (SFRs).
-Bit addressing of 16 RAM locations and 16
SFRs.
[Link] ; 27
[Link] ; 28
 Internal Data Memory
-Four register banks (Register Bank 0-3):00
to 1F hexadecimal.
-Bit addressable RAM (128 bits): 20 to 2F
hexadecimal.
-General purpose RAM (directly addressable
range): 30 to 7F hexadecimal.
-Special function registers (indirectly
addressable range): 80 to FF
hexadecimal.
[Link] ; 29
[Link] ; 30
• Any location on general purpose RAM can be accessed freely using
direct or indirect addressing modes.
• E.g., MOV A, 5FH ;contents of 5FH location will be
loaded in A
• E.g., MOV R0, #5FH ; value 5FH will be loaded in register R0
• MOV A, @R0 ; data will be loaded in A which is pointed
• ; at by R0
• Powerful feature that bits can be set, cleared, ANDed, ORed, etc.
with a single instruction
• E.g., SETB 67H ; to set bit 67H
Most microprocessors will do like
MOV A, 2CH ; read entire byte
• ORL A, #10000000B ; set MSB
• MOV 2CH, A ; write back entire byte

[Link] ; 31
[Link] ; 32
[Link] ; 33
[Link] ; 34
Special Function Register Space
-128 byte address space, directly
addressable as 80 to FF hex.
-16 addresses are bit addressable: Set,
Clear, AND, OR, MOV (those ending with
0 or 8).
-This space contains:
– Special purpose CPU registers.
– I/O control registers.
– I/O ports.
[Link] ; 35
[Link] ; 36
• CPU registers:
-ACC : Accumulator.
-B : B register.
-PSW : Program Status Word.
-SP : Stack Pointer.
-DPTR : Data Pointer (DPH, DPL).
• Interrupt control:
-IE : Interrupt Enable.
-IP : Interrupt Priority.

• I/O Ports:
-P0 : Port 0.
-P1 : Port 1.
-P2 : Port 2.
-P3 : Port 3.

[Link] ; 37
Timers:
– TMOD : Timer mode.
– TCON : Timer control.
– TH0 : Timer 0 high byte.
– TL0 : Timer 0 low byte.
– TH1 : Timer 1 high byte.
– TL1 : Timer 1 low byte.
Serial I/O:
– SCON : Serial port control.
– SBUF : Serial data registers.
Other:
– PCON : Power control

[Link] ; 38
- CY : Carry Flag.
- AC : Auxiliary Carry Flag.
- F0 : Flag 0 (available for user).
- RS1 : Register Select 1.
- RS0 : Register Select 0.
- OV : Arithmetic Overflow Flag.
- P : Accumulator Parity Flag.
• Flags are 1-bit registers provided to store the results of
certain program instructions. In order to conveniently
address the flags, they are grouped inside the PSW
register.

[Link] ; 39
• CY: (Carry Flag) is dual purpose: (1) As traditional CY for arithmetic operations e.g.,
If A contains FFH then the instruction
• ADD A, #1
• leaves A equal to 00H and sets the CY in PSW. (A=00H & CY=1)
• (2) As Boolean accumulator e.g., ANL C, 25H ; ANDs bit 25H with the carry flag and
places the result back in the CY.
• AC: (Auxiliary Carry Flag) used in addition of BCD numbers, is set if a carry was
generated out of bit 3 into bit 4. If the values are added are BCD, then the add
instruction must be followed by DAA (decimal adjust accumulator) to bring results
greater than 9 back into range.
• F0: (Flag 0) is a general-purpose flag bit available for user applications.
• OV: (Overflow flag) is set after an addition or subtraction operation if there was an
arithmetic overflow. Results greater than +127 or less than –128 will set OV bit.
• P: (Parity Bit) automatically set or cleared each machine cycle to establish even parity
with the accumulator. Parity bit is most commonly used in conjunction with serial port
routines to include a parity bit before or after the transmission.
• RS1 & RS0 are used to select different register banks.
• RS1 RSO Register Bank Address
• 0 0 0 00h - 07h
• 0 1 1 08h - 0Fh
• 1 0 2 10h - 17h
• 1 1 3 18h - 1Fh
Fig PSW (Program Status Word) [Link] ; 40
 SFRs (Special Function registers)
•B Register: (at F0H) also bit addressable and used along with the
accumulator for multiply & divide operations. E.g., MUL A B
instruction multiplies the 8-bit unsigned values in A & B and leaves
the 16-bit result in A (low-byte) & B (high-byte) E.g., DIVA B
instruction divides A by B leaving the integer result in A and
remainder in B.
•SP: (Stack Pointer) (at 81H) is an 8-bit register contains the address
of the data item currently on the top of stack. Its operations include
“Pushing” & “Popping” data from the stack.
•DPTR: (Data Pointer) is 16-bit register at 82H (DPL, low-byte) and
83H (DPH, high-byte) used to access external code or data
memory. It can be specified by its 16-bit name, DPTR, or by each
individual byte name, DPH and DPL.

[Link] ; 41
 Instruction Set Summary
8051 Addressing Modes
There are basically 5 ways of specifying source/destination operand addresses:
1. Particular On-chip Resources:
This includes the Accumulator (A), the Stack Pointer (SP), the Data Pointer (DP), the
Program Counter (PC), and the Carry (C). Other On-chip Registers are Memory-
mapped while these have special Op-codes.
2. Immediate operands:
The # sign is the designator. These are 8-bits except for DPTR contents (16-bits).
3. Register operands:
Designated as Rn, where n is 0..7. One of the four Register Banks is used
(selected by RS0 and RS1 in PSW).
4. Direct Operands:
From 00 to FF Hex, specifies one of the internal data addresses.
5. Indirect Address:
Designated as @Ri, where i is 0 or 1, uses the contents of R0 or R1 in the selected
Register Bank to specify the address. Other form is @A, using Accumulator contents.

[Link] ; 42
 8051 Addressing Modes
• Addressing modes are an integral part of each
computers instruction set. They allow different ways of
specifying source/destination operand addresses
depending on the programming situation. There are 8
modes of addressing:
• 1. Immediate
• 2. Register
• 3. Direct
• 4. Indirect
• 5. Relative
• 6. Absolute
• 7. Long
• 8. Indexed
[Link] ; 43
 IMMEDIATE ADDRESSING
• For example, the instruction:

MOV A, #99d

This instruction uses Immediate Addressing because the Accumulator will be

loaded with the value that immediately follows; in this case 99 (decimal).

[Link] ; 44
 DIRECT ADDRESSING
• Example:
• MOV A, direct; copy data from direct address ‘direct’ to register A
• MOV Rn, direct; copy data from direct address ‘direct’ to register Rn
• For example:
• MOV A, 47h

[Link] ; 45
 REGISTER ADDRESSING
For example:
MOV A, R5

[Link] ; 46
 INDIRECT ADDRESSING
For example:
MOV A, @ R0

[Link] ; 47
RELATIVE ADDRESSING

[Link] ; 48
General Format of Instruction:
Label: OpCode Destination, source ; Comments

[Link] ; 49
Instruction Set : Arithmetic

[Link] ; 50
Instruction Set : Logical

[Link] ; 51
[Link] ; 52
[Link] ; 53
Instruction Set : Data Transfer

[Link] ; 54
[Link] ; 55
Instruction Set : Branching

[Link] ; 56
[Link] ; 57
 Timer Operation
Counter / Timers (T0 & T1)
•Timer is a series of divide-by-two flip-flops that receive
an input signal as a clocking source.
•Clock is applied to the first flip-flop, which gives output
divided by 2.
•That output of first flip-flop clocks the second flip-
flop,which also divides it by 2 and so on.
•The output of the last stage clocks a timer overflow flip-
flop, or flag, which is tested by the software.
•It is like a counter. A 16-bit timer would count from
0000H to FFFFH. The overflow flag is set on the FFFFH-
to-0000H count.
• There are two timers in 8051 i.e., T0 and T1.
•Four modes of timer operations.

[Link] ; 58
• TMOD is not bit addressable. It is loaded, generally, by the software
at the beginning of a program to initialize the timer mode.
- GATE : Permits INTx pin to enable/disable the counter.
- C/T : Set for counter operation, reset for timer operation.
- M1, M0 : To Select the Mode
0 0 : Mode 0 - 13-bit timer mode (Emulates 8048).
0 1 : Mode 1 - 16-bit timer mode.
1 0 : Mode 2 - 8-bit auto-reload mode.
1 1 : Mode 3 - Split timer mode (Timer 0 = two 8-bit timers).

[Link] ; 59
- TF1, TF0 : Overflow flags for Timer 1 and Timer 0.
- TR1, TR0 : Run control bits for Timer 1 and Timer 0.
Set to run, reset to hold.
- IE1, IE0 : Edge flag for external interrupts 1 and 0. *
Set by interrupt edge, cleared when interrupt is processed.
- IT1, IT0 : Type bit for external interrupts. *
Set for falling edge interrupts, reset for 0 level interrupts.
*= not related to counter/timer operation but used to detect
and initiate external interrupts.
[Link] ; 60
 Timer Modes
• Timer Mode 0 (13-bit Timer):
– Timer high-byte (THx) is cascaded with the 5 least significant bits of
the timer low-byte (TLx) to form a 13-bit timer, where x = 0 or 1.
– Upper 3-bits of TLx are not used.
– Overflow occurs on the 1FFFH-to-0000H and sets the timer overflow
flag.
– MSB is THx bit 7, and LSB is TLx bit 0.
MOV TMOD, #00H ; setting both timers to mode 0

[Link] ; 61
 • Timer Mode 1 (16-bit Timer):
– Same as mode 0 except that it is 16-bit. Timer high-byte (THx) is cascaded
the timer low-byte (TLx) to form a 16-bit timer, where x = 0 or 1.
– Clock is applied to the combined high and low-byte timer registers.
– Overflow occurs on the FFFFH-to-0000H and sets the timer overflow flag.
– MSB is THx bit 7, and LSB is TLx bit 0.
– LSB toggles at clock frequency/21 and MSB at clock frequency/216

[Link] ; 62
Timer 1 Operating in 16-bit (Mode 1)

[Link] ; 63
 Timer Mode 2 (Auto-Reload):
– Timer low -byte (TLx) operates as an 8-bit timer while the timer high -
byte (THx) holds a reload value.
– When the count overflows from FFH-to-00H, not only the timer flag
set, but also the value in THx is loaded into TLx, and counting
continues from this value up to next FFH-to-00H, so on.

[Link] ; 64
 • Timer Mode 3:
– Timer 0 Splits into two 8-bit counter/timers. TL0 and TH0 act as two
separate timers with overflows setting the TF0 and TF1 respectively.
– Timer 1 (when timer 0 is in mode 3 ):
Counter stopped if in mode 3
Can be used in mode 0, 1, or 2
Has gate (INT1) and external input (T1), but no flag or interrupt.
May be used as a baud rate generator.

[Link] ; 65
 Clocking Sources
1. Interval Timing 2. Event Counting
[Link] Timing:

• If C/T = 0 (in TMOD), timer operation is selected and timer is clocked from
on-chip oscillator. A divide-by-12 clock frequency is applied.
• Timer registers (TLx/THx) increment at a rate of 1/12th the frequency of on-
chip oscillator.
• 12 MHz crystal would yield a clock rate of 1 MHz.
• Timer overflows occur after a fixed number of clocks, depending on the
initial value loaded into the timer registers.
[Link] Counting:
• If C/T = 1 (in TMOD), counter operation is selected and timer is clocked
fromexternal source. Usually, external source supplies the timer with a pulse
upon the occurrence of an event. Timer counts those events.
• External clock source comes through P3.4 (for Timer 0) and P3.5 (for Timer
1).
• Timer registers are incremented in response to a 1-to-0 transition at the
external input.
• Number of external events is determined in software by reading the timer
registers TLx/THx. [Link] ; 66
Start, Stop, and Control of Timers
•TRx bit in bit addressable register TCON is
responsible for starting and stopping the
counters
– –TRx = 0 stops/disables the timers (e.g., CLR
TR1)
– –TRx = 1 starts/enables the timers (e.g.,
SETB TR0)
•System reset clears TRx, so timers are
disabled by default.
[Link] ; 67
 Initializing and Accessing Timer Registers
•Timers are usually initialized once at the beginning of the program to set the correct
operating mode.
•Then, within the body of a program, the timers are started, stopped, flag bits are tested
and cleared, timer registers read or updated, and so on, as required in the
application.
•First register to be initialized is TMOD to set the mode of operation e.g.,
MOV TMOD, #00010000B ; sets Timer 1 in mode 1,leave C/T = 0 and GATE = 0 for
;internal clocking, and clears the Timer 0 bits.

•Secondly, registers to be initialized are TLx/THx. E.g., For 100µs interval, the following
instruction will do the job
MOV TL1, #9CH ; (-100)10 = FF9CH
MOV TH1, #FFH ; load Timer 1 registers by FF9CH
•The timer is then started by setting the run control bit i.e.,
SETB TR1
•Overflow flag is automatically set 100µs later. Following instruction will check that
WAIT: JNB TF1, WAIT ; wait until overflow flag is set.
•When the timer overflows, it is necessary to stop the timer and clear the overflow flag in
software by the following instructions:
CLR TR1; stop Timer 1
CLR TF1; clear overflow flag of Timer 1
[Link] ; 68
 Short and Long Intervals
•Shortest possible interval is one machine cycle i.e., 1µs (using 12 MHz
crystal frequency).
•An 8-bit counter can give maximum delay of 256µs because 28=256.
•A 13-bit counter can give maximum delay of 8192µs because
213=8192.
•A 16-bit counter can give maximum delay of 65536µs because
216=65536.
65536µs = 0.065536 sec = 0.066 sec (approx.)
•For more than 0.066 sec delay, there are two methods:
[Link] Timer 0 and Timer 1 but in this way both timers will be tied
up.
[Link] one timer in 16-bit mode with a software loop counting overflows.

[Link] ; 69
 THE 8051 UART
The 8051 includes Full duplex UART (Universal
Asynchronous Receiver /Transmitter), known as
a serial port .(Full duplex UART is a device that
receives and transmits serial data with each data
character preceded by a start bit “0” and
followed by a stop bit “1”). Essential function of
serial port is to perform parallel-to-serial
conversion for output data, and serial-to-parallel
conversion for input data. The UART block
diagram is shown in next slide.
[Link] ; 70
[Link] ; 71
 Serial Port Operation

• Essential function of serial port is to perform parallel-to-serial

conversion for output data, and serial-to-parallel conversion for input
data.
• Transmission bit is P3.1 on pin 11 (TXD) and reception bit is P3.0
on pin 10 (RXD).
• Features full duplex (simultaneous reception and transmission).
• Two SFRs (SBUF & SCON) provide software access to serial port.
– Writing to SBUF loads data to be transmitted and reading SBUF
accesses received data.
– SCON is a bit addressable register containing status bits and control
bits. Control bits set the operating mode and status bits indicate the
end of a character transmission or reception. The status bits are
tested in software or programmed to cause an interrupt.
•Serial port frequency of operation (baud rate) can be fixed or variable.
– Fixed is derived from on-chip oscillator and variable is supplied by
Timer 1 which must be programmed accordingly.

[Link] ; 72
- SM0, SM1 : Serial Port Mode bits
Mode Baud Rate
00 = Mode 0 : Shift register I/O Fixed (oscillator frequency/12)
01 = Mode 1 : 8-bit UART Variable (set by timer)
10 = Mode 2 : 9-bit UART Fixed (osc frq/32 or osc frq/64 )
11 = Mode 3 : 9-bit UART Variable (set by timer
Mode 0 : Not used.
Mode 1 : If SM2 = 0 : Normal Operation.
If SM2 = 1 : Ignore bytes with no stop bit.
Modes 2 & 3 : If SM2 = 0 : Set RI (receive interrupt) on all bytes.
If SM2 = 1 : Set RI only on bytes where 9th bit is 1.
-REN: Receiver enable. Must be set to receive characters.
-TB8: Transmit bit 8. Ninth bit transmitted (in modes 2 and 3); set/cleared by software.
-RB8: Receive bit 8. Ninth bit received (in modes 2 and 3):
Mode 0 : Not used.
Mode 1 : Stop bit.
Mode 2, 3 : Ninth data bit.
-TI: Transmit interrupt flag. Set at end of character transmission; cleared by software.
-RI: Receive interrupt flag. Set at end of character reception; cleared by software.
[Link] ; 73
 Serial Interface
-Full duplex UART (Universal Asynchronous Receiver
/Transmitter is a device that receives and transmits serial
data with each data character preceded by a start bit “0”
and followed by a stop bit “1”). Sometimes a parity bit is
inserted between the last data bit and the stop bit.
-The essential operation of a UART is to perform parallel-
to-serial conversion for output data, and serial-to-
parallel conversion for input data.
-10 or 11 bit frames. -Interrupt driven. -Registers:
SCON - Serial port control register.
SBUF - Read received data.
- Write data to be transmitted.
[Link] ; 74
Serial Interface Modes of Operation
(Mode 0)
Mode 0: 8-Bit Shift Register Mode. Terms RXD & TXD are
misleading in this mode. RXD line is used for both input and
output. TXD line serves as the clock.
• Eight bits are transmitted and received with the LSB first.
Baud Rate is fixed at 1/12 of on-chip oscillator frequency.
• Transmission is initiated by any instruction that writes data to
SBUF. Data are shifted out on RXD line with clock pulses sent
out by the TXD line. Each transmitted bit is valid on the RXD
pin for one machine cycle. E.g., MOV SBUF, A
• Reception is initiated when the REN is 1 and the RI is 0. REN
is set at the beginning of the program, and then clear RI to
begin a data input operation. The clocking of data
into serial port occurs on the positive edge of TXD.

[Link] ; 75
Serial Interface Modes of Operation
(Mode 1)
Mode 1: Serial port operates as an 8-bit UART with a
variable baud rate.10-bits are transmitted on TXD or
received on RXD. Start bit (always 0), 8 data bits (LSB
first), and a stop bit (always 1). For a receive operation,
the stop bit goes into RB8 in SCON. Baud Rate Clock is
variable using Timer 1 overflow or external count input.
• Transmission is initiated by writing data to SBUF. Shifted
data are outputted on the TXD line beginning with the
start bit. The transmit interrupt flag (TI) is set as soon as
the stop bit appears on TXD.
• Reception is initiated by a 1-to-0 transition on RXD.

[Link] ; 76
Serial Interface Modes of Operation
(Mode 2)
Mode 2: Serial port operates as a 9-bit UART with
a fixed baud rate. 11-bits are transmitted or
received. Start bit (always 0), 8 data bits (LSB
first), a programmable 9th bit, and a stop bit
(always 1).
• On transmission, the 9th bit whatever has been
put in TB8 in SCON (may be a parity bit).
• On reception, the 9th bit is placed in RB8 in
SCON.
• Baud Rate is programmable to either 1/32 or
1/64 of the on-chip oscillator frequency.

[Link] ; 77
Serial Interface Modes of Operation
(Mode 3)
Mode 3: Serial port operates as a 9-bit
UART with a variable baud rate. 11-bits
are transmitted or received. Baud Rate is
programmable and provided by the Timer
1 overflow or external input.
Summary:
Baud rate: Fixed in modes 0 & 2, variable in modes 1 & 3
Data Bits: Eight in mode 1, nine in modes 2 & 3

[Link] ; 78
 UART Initialization
• Receiver Enable Bit (REN): must be set by software to enable the reception of characters at
the beginning of a program when the serial port, timers, etc. are initialized. The instructions are
SETB REN or MOV SCON, #xxx1xxxxB
• The 9th Bit: transmitted must be loaded into TB8 by software and received is placed in RB8.
• Adding a Parity Bit: is a common use of 9th bit. E.g., if communication requires 8 data bits
plus even parity
MOV C, P ; Put even parity bit in C flag
MOV TB8, C ; This becomes the 9th data bit in TB8
MOV SBUF, A ; Move 8 bits from ACC to SBUF
• E.g., if communication requires 8 data bits plus odd parity
MOV C, P ; Put even parity bit in C flag
CPL C ; Convert to odd parity
MOV TB8, C ; This becomes the 9th data bit in TB8
MOV SBUF, A ; Move 8 bits from ACC to SBUF
• Parity can be used in mode 1 also if the 7 data bits are used. E.g., 7-bit ASCII code with even
parity can be transmitted as follows:
CLR ACC.7 ; Ensure MSB is clear
MOV C, P ; Put even parity bit in C flag
MOV ACC.7, C ; Copy even parity bit into MSB
MOV SBUF, A ; Send character

[Link] ; 79
 Interrupt Flags (RI &TI)
•RI & TI in SCON play an important role in serial communications. Both bits
are set by hardware but must be cleared by software.
– RI is set at the end of character reception and indicates “receive buffer full”.
– This condition is tested in software or programmed to cause an interrupt.
– If software wishes to input a character from the device connected to the
serial port, it must wait until RI is set, then clear RI and read the character
from SBUF.
WAIT: JNB RI, WAIT ; Check RI until set
CLR RI ; Clear the flag
MOV A, SBUF ; Read character
– TI is set at the end of character transmission and indicates “transmit buffer
empty”.
– If software wishes to send a character to the device connected to the serial
port, it must wait until TI is set (means previous character was sent, wait
until transmission is finished before sending the next character), then clear
TI and send the character.
WAIT: JNB TI, WAIT ; Check TI until set
CLR TI ; Clear the flag
MOV SBUF, A ; Send character
[Link] ; 80
 Baud Rates
•Baud rate is also affected by a bit in the PCON register.
PCON.7 is SMOD bit. If SMOD = 1, baud rate will be
doubled in modes 1, 2 and 3.
•Mode 2 baud rate is the 1/64th the oscillator frequency
(SMOD = 0) and can be doubled to 1/32nd the oscillator
frequency (SMOD = 1).
•PCON is not bit-addressable, setting SMOD without
altering the other bits requires a “read-modify-write”
operation as follows:
MOV A, PCON ; Get current value of PCON
SETB ACC.7 ; Set SMOD
MOV PCON, A ; Write value back to PCON
[Link] ; 81
 Using Timer 1 as Baud Rate Clock
•Usually the timer is used in auto-reload mode and TH1 is loaded
with a proper reload value.
•Formula for the baud rate in modes 1 and 3 is
Baud Rate = Timer 1 Overflow Rate / 32
e.g., For 1200 baud
1200 = Timer 1 Overflow Rate / 32
Timer 1 Overflow Rate = 1200 * 32 = 38400 Hz
•Timer must overflow at a rate of 38.4 kHz and the timer is
clocked at a rate of 1 MHz (1000 kHz), overflow required every
1000/38.4 = 26.04 clocks, so
MOV TH1, # -26
•Due to rounding, there is a slight error in the resulting baud rate.
Up to 5% is tolerable using asynchronous communications.
Exact baud rates are possible using an 11.059 MHz crystal .
[Link] ; 82
 Interrupts
An interrupt is the occurrence of an event that causes
temporary suspension of a program while the condition
is serviced by another program. It is like a sub-routine.
CPU cannot execute more than one instruction at a time;
but it can temporarily suspend execution of one program,
execute another, then return to the first program.
Difference in interrupt and subroutine is that in an
interrupt-driven system, the interruption occur
asynchronously with the main program, and it is not
known when the main program will be interrupted.
Program that deals with the interrupt is called as ISR
(Interrupt Service Routine).

[Link] ; 83
 Interrupt System
-Five interrupt sources in order of polling (priority) sequence are:
External Interrupt 0
Timer 0
External Interrupt 1
Timer 1
Serial Port
-The polling sequence is fixed but each interrupt type can be
programmed to one of two priority levels.
-If two interrupts of same priority occur simultaneously then polling
sequence will determine which is serviced first.
-External interrupts can be programmed for edge or level sensitivity.
-Each interrupt type has a separate vector address.
-All interrupts are disabled after a system reset and enabled
individually by software.

[Link] ; 84
 Processing Interrupts
When an interrupt occurs and is accepted by
CPU, the following actions occur:
– Current instruction’s complete execution
– PC is saved on the stack
– PC is loaded with the vector address of the ISR
– ISR executes and takes action in response to
interrupt
– ISR finishes with a RETI instruction
– PC is loaded with its old value from the stack
– Execution of main program continues where it left off
[Link] ; 85
 Interrupt Vector
• When an interrupt is accepted, the value loaded
into the PC is called the interrupt vector. It is the
address of the start of the ISR for the
interrupting source.
• When an interrupt is vectored, the flag that
caused the interrupt is automatically cleared by
hardware.
• Timer interrupts occur when the timer registers
(TLx/THx) overflow and set the overflow flag
(TFx).

[Link] ; 86
[Link] ; 87
- EA : Global interrupt enable/ disable.
- ES : Serial port interrupt enable/ disable.
- ET1 : Timer 1 interrupt enable/ disable.
- EX1: External interrupt 1 enable/ disable.
- ET0 : Timer 0 interrupt enable/ disable.
- EX0: External interrupt 0 enable/ disable.
e.g., Timer 1 interrupt can be enabled as follows:
SETB EA ; Enable global interrupt bit
SETB ET1 ; Enable Timer 1 interrupt
Or MOV IE, #10001000B

[Link] ; 88
(1 = High priority, 0 = Low priority)
- PS : Priority for Serial port interrupt.
- PT1: Priority for Timer 1 interrupt.
- PX1 : Priority for External interrupt 1.
- PT0 : Priority for Timer 0 interrupt.
- PX0 : Priority for External interrupt 0.
IP is cleared after a system reset to place all interrupts at the lower
priority level by default.

[Link] ; 89
• TI: Transmit interrupt flag. Set at the end of
character transmission; cleared by software.
• RI: Receive interrupt flag. Set at the end of
character reception; cleared by software.

[Link] ; 90
 External Interrupts

• External interrupt occurs as a result of a low-

level or negative-edge on the INT0 or INT1 pin
of 8051.
• Flags that generate these interrupts are bits IE0
and IE1 in TCON. These are automatically
cleared when the CPU vectors to the interrupt.
• Low-level or negative-edge activated interrupts
can be programmed through IT0 and IT1
bits in TCON, i.e., ITx = 0 means low-level and
ITx = 1 means negative-edge triggered.

[Link] ; 91
- TF1, TF0 : Overflow flags for Timer 1 and Timer 0. *
- TR1, TR0 : Run control bits for Timer 1 and Timer 0. *
Set to run, reset to hold.
- IE1, IE0 : Edge flag for external interrupts 1 and 0.
Set by interrupt edge, cleared when interrupt is
processed.
- IT1, IT0 : Type bit for external interrupts.
Set for falling edge interrupts, reset for 0 level interrupts.
* = related to counter/timer operation
[Link] ; 92