Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić

Timing Issues
January 2003

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EE141 Integrated Circuits 2nd Timing Issues
 Synchronous Timing

CLK

In Combinational
R1 R2
Cin Logic Cout Out

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EE141 Integrated Circuits 2nd Timing Issues
 Timing
Definitions

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EE141 Integrated Circuits 2nd Timing Issues
 Latch Parameters

D Q
tc-q-rise ≠ tc-q-fall
Clk

T
Clk PWm
tsu
D
thold

tc-q-rise tc-q-fall td-q

Q

Delays can be different for rising and falling data transitions

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EE141 Integrated Circuits 2nd Timing Issues
 Register Parameters

D Q

Clk

T
Clk

D thold

tsu
tc-q
Q

Delays can be different for rising and falling data transitions

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EE141 Integrated Circuits 2nd Timing Issues
 Clock Uncertainties
4 Power Supply
3 Interconnect
2 6 Capacitive Load
Devices

7 Coupling to Adjacent Lines

5 Temperature
1 Clock Generation

Sources of clock uncertainty

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EE141 Integrated Circuits 2nd Timing Issues
 Clock Nonidealities
 Clock skew
 Spatial variation in temporally equivalent clock
edges; deterministic + random, tSK
 Clock jitter
 Temporal variations in consecutive edges of the
clock signal; modulation + random noise
 Cycle-to-cycle (short-term) tJS
 Long term tJL
 Variation of the pulse width
 Important for level sensitive clocking

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EE141 Integrated Circuits 2nd Timing Issues
 Clock Skew and Jitter
tpw2
tpw1
Clk
tSK

Clk tJS

 Both skew and jitter affect the effective cycle time

 Only skew affects the race margin
4 Power Supply
3 Interconnect
2 6 Capacitive Load
Devices

7 Coupling to Adjacent Lines

5 Temperature
1 Clock Generation

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EE141 Integrated Circuits 2nd Timing Issues
 Positive and Negative Skew
R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

CLK tCLK1 tCLK2 tCLK3

delay delay
(a) Positive skew

R1 R2 R3
In Combinational Combinational
D Q D Q D Q •••
Logic Logic

tCLK1 tCLK2 tCLK3

delay
(b) Negative skew

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EE141 Integrated Circuits 2nd Timing Issues
 Positive Skew

TCLK  
TCLK
1
CLK1


CLK2 2 4
  th

Launching edge arrives before the receiving edge

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EE141 Integrated Circuits 2nd Timing Issues
 Negative Skew

TCLK + 
TCLK
1 3
CLK1

CLK2 2 4


Receiving edge arrives before the launching edge

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EE141 Integrated Circuits 2nd Timing Issues
 Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc  q tlogic
tc  q, cd t
tsu, thold

Minimum cycle time:

T -  = tc-q + tsu + tlogic
Worst case is when receiving edge arrives early (positive skew )

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EE141 Integrated Circuits 2nd Timing Issues
 Timing Constraints
R1 R2
In Combinational
D Q D Q
Logic

CLK tCLK1 tCLK2

tc  q tlogic
tc  q, cd t T
tsu, thold Clk

thold
Hold time constraint: D
t(c-q, cd) + t(logic, cd) > thold +  tsu

Worst case is when receiving edge arrives late

Race between data and clock

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EE141 Integrated Circuits 2nd Timing Issues
 Impact of Jitter
 TC LK 

CLK    t j itter

-tji tte r 

REGS Combinational
In Logic

CLK t log ic
tc-q , tc-q, cd t log ic, cd
ts u, thold
tjitter

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EE141 Integrated Circuits 2nd Timing Issues
 Longest Logic Path in
Edge-Triggered Systems TJI + 
TSU
Clk
TClk-Q
TLM
T

Latest point
of launching Earliest arrival
of next cycle

R1 R2
In Combinational
D Q D Q
Logic Shorten cycle time:
CLK tCLK1 tCLK2 Tj - 2 < tc-q + tsu + tlogic
tc  q tlogic
tc  q, cd t
tsu, thold
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EE141 Integrated Circuits 2nd Timing Issues
 Clock Constraints in
Edge-Triggered Systems
If launching edge is late and receiving edge is early, the data will not be too late if:

Tc-q + TLM + TSU < T – TJI,1 –

TJI,2 - 
Minimum cycle time is determined by the maximum delays through the logic

Tc-q + TLM + TSU +  + 2 TJI

< can
Skew T be either positive or negative
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EE141 Integrated Circuits 2nd Timing Issues
 Shortest Path
Earliest point
of launching

Clk
TClk-Q TLm

Clk
TH

Data must not arrive

Nominal
before this time
clock edge

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EE141 Integrated Circuits 2nd Timing Issues
 Clock Constraints
in Edge-Triggered Systems

If launching edge is early and receiving edge is late:

Tc-q + TLM – TJI,1 < TH + TJI,2 + 

Minimum logic delay

Tc-q + TLM < TH + 2TJI+



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EE141 Integrated Circuits 2nd Timing Issues
How to counter Clock Skew?
Negative Skew

REG

REG
REG
 . log Out

 
REG

In
Positive Skew


Clock Distribution

Data and Clock Routing

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EE141 Integrated Circuits 2nd Timing Issues
 Flip-Flop – Based Timing
Skew Flip-flop
Logic delay delay


TSU
Flip TClk-Q
-flop



Logic 

Representation after
M. Horowitz, VLSI Circuits 1996.

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EE141 Integrated Circuits 2nd Timing Issues
 Flip-Flops and Dynamic Logic
Logic delay

TSU
TSU TClk-Q
TClk-Q

 
 
 


Logic delay
Precharge Evaluate Precharge
Evaluate

Flip-flops are used only with static logic

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EE141 Integrated Circuits 2nd Timing Issues
 Latch timing
tD-Q When data arrives
to transparent latch
Latch is a ‘soft’ barrier
D Q

Clk

tClk-Q When data arrives

to closed latch

Data has to be ‘re-launched’

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EE141 Integrated Circuits 2nd Timing Issues
 Single-Phase Clock with Latches


Latch

Logic

Tskl Tskl Tskt Tskt

Clk
PW
P

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EE141 Integrated Circuits 2nd Timing Issues
 Latch-Based Design
L1 latch is L2 latch is transparent
transparent when  = 1

when  = 0

L1 L2
Logic
Latch Latch

Logic

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EE141 Integrated Circuits 2nd Timing Issues
 Slack-borrowing
L1 L2 L1
In CLB_A CLB_B
D Q D Q D Q
a t p d,A b c t p d,B d e

CLK1 CLK2 CLK1

TC LK

CLK1
   

CLK2

slack passed to next stage

t pd,A tD Q tpd,B t DQ
e valid
a valid b valid c valid d valid

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EE141 Integrated Circuits 2nd Timing Issues
 Latch-Based Timing
Skew
Static logic


 L2 latch
L1 L2
Logic
Latch Latch

L1 latch

Logic
Long 
path 

Can tolerate skew!

Short
path
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EE141 Integrated Circuits 2nd Timing Issues
Clock Distribution

H-tree

CLK

Clock is distributed in a tree-like fashion

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EE141 Integrated Circuits 2nd Timing Issues
 More realistic H-tree

[Restle98]
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EE141 Integrated Circuits 2nd Timing Issues
 The Grid System
G CL K

D r iv e r
Driver

Driver
G C LK G C LK

•No rc-matching
•Large power
D r iv e r

G CL K

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EE141 Integrated Circuits 2nd Timing Issues
Example: DEC Alpha 21164
Clock Frequency: 300 MHz - 9.3 Million Transistors

Total Clock Load: 3.75 nF

Power in Clock Distribution network : 20 W (out of 50)

Uses Two Level Clock Distribution:

• Single 6-stage driver at center of chip

• Secondary buffers drive left and right side
clock grid in Metal3 and Metal4
Total driver size: 58 cm!

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EE141 Integrated Circuits 2nd Timing Issues
 21164 Clocking
tcycle= 3.3ns  2 phase single wire clock,
trise = 0.35ns tskew = 150ps distributed globally
 2 distributed driver channels
Clock waveform  Reduced RC delay/skew
final drivers  Improved thermal distribution
 3.75nF clock load
 58 cm final driver width
 Local inverters for latching
 Conditional clocks in caches to
reduce power
pre-driver  More complex race checking
 Device variation
Location of clock
driver on die
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EE141 Integrated Circuits 2nd Timing Issues
 Clock Drivers

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EE141 Integrated Circuits 2nd Timing Issues
 Clock Skew in Alpha Processor

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EE141 Integrated Circuits 2nd Timing Issues
 EV6 (Alpha 21264) Clocking
600 MHz – 0.35 micron CMOS
tcycle= 1.67ns

trise = 0.35ns tskew = 50ps

Global clock waveform
 2 Phase, with multiple conditional
buffered clocks
 2.8 nF clock load
 40 cm final driver width
 Local clocks can be gated “off” to
save power
 Reduced load/skew
 Reduced thermal issues
 Multiple clocks complicate race
PLL
checking
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EE141 Integrated Circuits 2nd Timing Issues
 21264 Clocking

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EE141 Integrated Circuits 2nd Timing Issues
 EV6 Clock Results
ps ps
5 300
10 305
15 310
20 315
25 320
30 325
35 330
40 335
45 340
50 345

GCLK Skew GCLK Rise Times

(at Vdd/2 Crossings) (20% to 80% Extrapolated to 0% to 100%)
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EE141 Integrated Circuits 2nd Timing Issues
 EV7 Clock Hierarchy
Active Skew Management and Multiple Clock Domains

+ widely dispersed
NCLK
(Mem Ctrl) drivers

+ DLLs compensate
DLL
static and low-
DLL

DLL
frequency variation

+ divides design and

verification effort
PLL

L2R_CLK
L2L_CLK
(L2 Cache)

(L2 Cache)

- DLL design and

GCLK
(CPU Core)
verification is added
work
SYSCLK + tailored clocks
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EE141 Integrated Circuits 2nd Timing Issues
 Self-timed and Asynchronous
Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events

Truly asynchronous design

1) Completion is ensured by careful timing analysis

2) Ordering of events is implicit in logic

Self-timed design

1) Completion ensured by completion signal

2) Ordering imposed by handshaking protocol

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EE141 Integrated Circuits 2nd Timing Issues
 Synchronous Pipelined Datapath

R1 R2 R3 R4
In Logic Logic
D Q Block #1 D Q Block #2 D Q D Q

CLK tpd,reg tpd1 tpd2 tpd3

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EE141 Integrated Circuits 2nd Timing Issues
 Self-Timed Pipelined Datapath
Req Req Req Req

Ack HS Ack HS Ack HS ACK

Start Done Start Done Start Done

R1 F1 R2 F2 R3 F3 Out
In

tpF1 tpF2 tpF3

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EE141 Integrated Circuits 2nd Timing Issues
 Completion Signal Generation

LOGIC
In Out
NETWORK

Start DELAY MODULE Done

Using Delay Element (e.g. in memories)

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EE141 Integrated Circuits 2nd Timing Issues
 Completion Signal Generation

Using Redundant Signal Encoding

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EE141 Integrated Circuits 2nd Timing Issues
 Completion Signal in DCVSL
VDD VDD

Start B0
Done
B1

B0 B1

In1
In1
In2 PDN PDN
In2

Start

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EE141 Integrated Circuits 2nd Timing Issues
 Self-Timed Adder
VDD VDD
Start Start
P0 P1 P2 P3 Done
C0 C1 C2 C3 C4 C4
C4 C4
C0 G0 G1 G2 G3 C3 C3

Start C2 C2
C1 C1
VDD
Start
Start
P0 P1 P2 P3
C0 C1 C2 C3 C4 C4 (b) Completion signal
C0 K0 K1 K2 K3

Start

(a) Differential carry generation

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EE141 Integrated Circuits 2nd Timing Issues
 Completion Signal Using Current Sensing
Input Register

VDD
Start
Inputs Static CMOS Logic Output tdelay
A
GNDsense toverlap
Start
Current Sensor A B
tMDG
Done tpd-NOR
Done
Min Delay Generator B
Output valid

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EE141 Integrated Circuits 2nd Timing Issues
 Hand-Shaking Protocol
Req
Req
Ack
SENDER RECEIVER
Data 3
Ack

(a) Sender-receiver configuration Data 1 1

cycle 1 cycle 2
Sender’s action
Receiver’s action
(b) Timing diagram
Two Phase Handshake

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EE141 Integrated Circuits 2nd Timing Issues
 Event Logic – The Muller-C Element
A B Fn1
A
0 0 0
F 0 1 Fn
B 1 0 Fn
1 1 1

(a) Schematic (b) Truth table

VDD
VDD VDD

A B
A
S Q
F B
B F
R A F
B
(a) Logic
A B
B

(b) Majority Function

(c) Dynamic 47
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EE141 Integrated Circuits 2nd Timing Issues
 2-Phase Handshake Protocol
Data
Sender Receiver
logic logic

Data ready Data accepted

Req
C

Ack

Handshake logic

Advantage : FAST - minimal # of signaling events (important for global

interconnect)
Disadvantage : edge - sensitive, has state
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EE141 Integrated Circuits 2nd Timing Issues
 Example: Self-timed FIFO

In Out
R1 R2 R3

En Done
Reqi Req0
C C C

Acki Acko

All 1s or 0s -> pipeline empty

Alternating 1s and 0s -> pipeline full
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EE141 Integrated Circuits 2nd Timing Issues
 2-Phase Protocol

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EE141 Integrated Circuits 2nd Timing Issues
 Example

From [Horowitz]
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EE141 Integrated Circuits 2nd Timing Issues
 Example

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EE141 Integrated Circuits 2nd Timing Issues
 Example

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EE141 Integrated Circuits 2nd Timing Issues
 Example

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EE141 Integrated Circuits 2nd Timing Issues
 4-Phase Handshake Protocol

2 4 Sender’s action
Req
Receiver’s action

Ack
3 5

Data 1 1

Cycle 1 Cycle 2

Also known as RTZ

Slower, but unambiguous

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EE141 Integrated Circuits 2nd Timing Issues
 4-Phase Handshake Protocol
Implementation using Muller-C elements
Data
Sender Receiver
logic logic

Data ready Data accepted

Req
S
C C

Ack

Handshake logic

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EE141 Integrated Circuits 2nd Timing Issues
 Self-Resetting Logic

completion completion completion

detection detection detection
(L1) (L2) (L3)
Precharged Precharged Precharged
Logic Block Logic Block Logic Block
(L1) (L2) (L3)

VDD

Post-charge
int
out logic
A B C

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EE141 Integrated Circuits 2nd Timing Issues
 Clock-Delayed Domino
GND

CLK1 CLK2 (to next stage)

VDD
Q1 (also D2)

D1 Pulldown
Network

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EE141 Integrated Circuits 2nd Timing Issues
Asynchronous-Synchronous Interface

fin
Synchronous system
Asynchronous
system
fCLK

Synchronization

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EE141 Integrated Circuits 2nd Timing Issues
 Synchronizers and Arbiters
 Arbiter: Circuit to decide which of 2 events
occurred first
 Synchronizer: Arbiter with clock  as one of
the inputs
 Problem: Circuit HAS to make a decision in
limited time - which decision is not important
 Caveat: It is impossible to ensure correct
operation
 But, we can decrease the error probability at
the expense of delay
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EE141 Integrated Circuits 2nd Timing Issues
 A Simple Synchronizer
CLK

I1
int
D Q

I2
CLK

• Data sampled on rising edge of the clock

• Latch will eventually resolve the signal value,

but ... this might take infinite time!
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EE141 Integrated Circuits 2nd Timing Issues
 Synchronizer: Output Trajectories
2.0

Vout

1.0

0.0
0 100 200 300
time [ps]

Single-pole model for a flip-flop

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EE141 Integrated Circuits 2nd Timing Issues
 Mean Time to Failure

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EE141 Integrated Circuits 2nd Timing Issues
 Example
Tf = 10 nsec = T
Tsignal = 50 nsec
tr = 1 nsec
t = 310 psec
VIH - VIL = 1 V (VDD = 5 V)

N(T) = 3.9 10-9 errors/sec

MTF (T) = 2.6 10 8 sec = 8.3 years
MTF (0) = 2.5 sec

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EE141 Integrated Circuits 2nd Timing Issues
 Influence of Noise
Uniform distribution
around VM
p(v)

logarithmic
reduction
T

0 VIL VIH
Still Uniform
Initial Distribution

Low amplitude noise does not influence synchronization behavior

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EE141 Integrated Circuits 2nd Timing Issues
 Typical Synchronizers
2 phase clocking circuit 2

Q
1

Q 2

1

Using delay line

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EE141 Integrated Circuits 2nd Timing Issues
 Cascaded Synchronizers Reduce MTF

In O1 O2 Out
Sync Sync Sync

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EE141 Integrated Circuits 2nd Timing Issues
 Arbiters
Req1 Ack1
Req1 A
Arbiter
Req2 Ack2 Ack2
B
Ack1
Req2
(a) Schematic symbol

Req1 (b) Implementation

Req2
VT gap
A (c) Timing diagram
B
metastable
Ack1
t

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EE141 Integrated Circuits 2nd Timing Issues
 PLL-Based Synchronization
Chip 1 Chip 2

Data
Digital Digital
System System

reference
fsystem = N x fcrystal clock
Divider PLL
PLL Clock
Buffer

fcrystal  200<Mhz

Crystal
Oscillator

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EE141 Integrated Circuits 2nd Timing Issues
 PLL Block Diagram

Reference Up
clock v
Phase Charge Loop
VCO
detector pump filter

Local Down
clock

Divide by
N
System
Clock

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EE141 Integrated Circuits 2nd Timing Issues
 Phase Detector
Output before filtering
ref
ref
Output local
clock
local Output
clock
(a) (b)
Output (Low pass filtered)
VDD
Transfer
characteristic

-180 -90 90 180 phase error (deg)

(c)
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EE141 Integrated Circuits 2nd Timing Issues
 Phase-Frequency Detector
B A
Rst UP
D Q B

A UP = 0 UP = 0 UP = 1
A
DN = 1 DN = 0 DN = 0
Rst
D Q
DN
A B
B
(a) schematic (b) state transition diagram

A A

B B

UP UP

DN DN

(c) Timing waveforms

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EE141 Integrated Circuits 2nd Timing Issues
 PFD Response to Frequency

UP

DN

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EE141 Integrated Circuits 2nd Timing Issues
 PFD Phase Transfer Characteristic

Average (UP-DN)
VDD

2

2 phase error (deg)

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EE141 Integrated Circuits 2nd Timing Issues
 Charge Pump
VDD

UP To VCO Control Input

DN

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EE141 Integrated Circuits 2nd Timing Issues
 PLL Simulation
ref
1.0

div
0.8
Control Voltage (V)

0.6 vco

0.4
ref
0.2

0.0 div
0 1 2 3 4 5
Time (  s)
vco

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EE141 Integrated Circuits 2nd Timing Issues
 Clock Generation using DLLs
Delay-Locked Loop (Delay Line Based)

fREF U
Phase Charge
D DL
Det Pump
Filter
fO

Phase-Locked Loop (VCO-Based)

fREF U

PD D CP VCO
÷N Filter
fO
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EE141 Integrated Circuits 2nd Timing Issues
 Delay Locked Loop
U
FREF Phase Charge C
PH D VCTRL VCDL
detect pump

FO
(a)

REF
OUT
UP

DN
PH
VCTRL

Delay

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EE141 Integrated Circuits 2nd Timing Issues
 DLL-Based Clock Distribution
Digital
VCDL •••
Circuit

CP/LF

Phase
Detector

Digital
GLOBAL CLK VCDL •••
Circuit

CP/LF

Phase
Detector

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EE141 Integrated Circuits 2nd Timing Issues
 Problem Practices
2.a
3.a, b
5.

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EE141 Integrated Circuits 2nd Timing Issues