UNIT-III
UNIT- III: TIMERS AND MIXED SIGNAL SYSTEMS
Timers - Watchdog Timer, RTC, Timer_A, Measurement in capture mode, PWM generation; Mixed Signal
Systems- Comparator_A, ADC10 SAADC –Architecture, operation- Single Conversion, Temperature Sensor on
ADC10, DTC in ADC10; ADC12 – Comparison with ADC10.
Timers
Watchdog timer: Its main function is to protect the system against malfunctions but it
can instead be used as an interval timer if this protection is not needed.
Basic timer1: Present in the MSP430x4xx family only. It provides the clock for the LCD
and acts as an interval timer. Newer devices have the LCD_A controller, which contains its
own clock generator and frees the basic timer from this task.
Real-time clock: In which the basic timer has been extended to provide a real-time clock
in the most recent MSP430x4xx devices.
Timer_A: It typically has three channels and can handle external inputs and outputs
directly to measure frequency, time-stamp inputs, and drive outputs at precisely specified
times, either once or periodically. There are internal connections to other modules so that
it can measure the duration of a signal from the comparator, for instance. It can also
generate interrupts.
Timer_B: It is similar to Timer_A with some extensions that make it more suitable for
driving outputs such as pulse-width modulation.
Watchdog Timer (WDT)
Features of the watchdog timer+ module include:
• Four software-selectable time intervals
• Watchdog mode
• Interval mode
• Access to WDT+ control register is password protected
• Control of RST/NMI pin function
• Selectable clock source
• Can be stopped to conserve power
• Clock fail-safe feature
Watchdog Timer+ Operation
The WDT+ module can be configured as either a watchdog or interval timer with the
WDTCTL register.
The WDTCTL register also contains control bits to configure the RST/NMI pin.
WDTCTL is a 16-bit, password-protected, read/write register.
Any read or write access must use word instructions and write accesses must include
the write password 05Ah in the upper byte.
Any write to WDTCTL with any value other than 05Ah in the upper byte is a security key
violation and triggers a PUC system reset regardless of timer mode.
Any read of WDTCTL reads 069h in the upper byte. The WDT+ counter clock should be
slower or equal than the system (MCLK) frequency.
Watchdog Mode
After a PUC condition, the WDT+ module is configured in the watchdog mode with an initial 32768 cycle
reset interval using the DCOCLK.
The user must setup, halt, or clear the WDT+ prior to the expiration of the initial reset interval or another
PUC will be generated.
When the WDT+ is configured to operate in watchdog mode, either writing to WDTCTL with an incorrect
password, or expiration of the selected time interval triggers a PUC.
A PUC resets the WDT+ to its default condition and configures the RST/NMI pin to reset mode.
Interval Timer Mode
Watchdog Timer+ Registers
16-Bit Timer Counter
The 16-bit timer/counter register, TAR, increments or decrements (depending on mode of operation) with
each rising edge of the clock signal.
TAR can be read or written with software. Additionally, the timer can generate an interrupt when it overflows
TAR may be cleared by setting the TACLR bit. Setting TACLR also clears the clock divider and count
direction for up/down mode..
Clock Source Select and Divider
The timer clock TACLK can be sourced from ACLK, SMCLK, or externally via TACLK.
The clock source is selected with the TASSELx bits. The selected clock source may be passed directly to the timer
or divided by 2, 4, or 8, using the IDx bits.
The selected clock source can be further divided by 2, 3, 4, 5, 6, 7, or 8 using the IDEXx bits.
The TACLK dividers are reset when TACLR is set.
Timer Mode Control
The timer has four modes of operation
Timer_A 16-bit Counter
15 0
TACTL
Input Input Mode un- TAIE TAIFG
unused CLR
Select Divider Control used
160h
rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- (w)- rw- rw-
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
MC1 MC0
0 0 Stop Mode
TACLR – clears TAR and resets 0 1 Up Mode
1 0 Continuous Mode
the direction of counting (it 1 1 Up/Down Mode
ID1 ID0
clears automatically itself)
0 0 1/1, Pass
0 1 1/2
TAIFG – set when the timer 1 0 1/4
counts to 0; a maskable 1 1 1/8
SSEL1 SSEL0
interrupt is requested if TAIE bit
0 0 TACLK
is set 0 1 ACLK
1 0 MCLK
1 1 INCLK (often = #TACLK)
CPE 323 16
Timer_A Capture Compare
Blocks Logic
Overflow x
COVx Data Bus Timer Bus
Capture Path
CCISx1 CCISx0 CMPx
CCIxA 0
1 15 0
CCIxB Capture 1
2 Capture/Compare Register
GND Mode
3 CCRx
VCC Timer 0 Capture
Clock Synchronize
CMx1 CMx0
Capture SCSx
0 0 Disabled
0 1 Pos. Edge
1 0 Neg. Edge 15 0
1 1 Both Edges
Comparator
to Port0x
CAPx
EQUx 0
1 Set_CCIFGx
Compare Path
EN
Y SCCIx
CCIx A
CCRx 15 0
0172h
15 0
to 2 2
017Eh
rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw-
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
15 0
CCTLx un-
CAPTURE INPUT CAP
SCS SCCI OUTMODx CCIE CCI OUT COV CCIFG
162h MODE SELECT used
to
rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- rw- r rw- rw- rw-
16Eh
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
REAL TIME CLOCK
Calendar Mode
Real-Time Clock and Prescale Dividers
The prescale dividers, RT0PS and RT1PS,
are automatically configured to provide a 1-s
clock interval for the RTC_A.
RT0PS is sourced from ACLK. ACLK must
be set to 32768 Hz (nominal) for proper
RTC_A calendar operation.
RT1PS is cascaded with the output
ACLK/256 of RT0PS, which is ACLK/256 =
128 Hz.
The RTC_A is sourced with the /128 output
of RT1PS, thereby providing the required 1-s
interval.
Mixed-Signal Systems
ADC10 Architecture & operation
ADC10
• Single channel, single conversion: Single conversion for the channel selected by INCHx bits.
This mode is represented by the constant CONSEQ_0.
• Sequence of channels: One conversion in multiple channels, beginning with the channel selected by
INCHx bits and decrementing to channel A0. The operation stops after the conversion of channel A0. This
mode is represented by the constant CONSEQ_1.
• Repeat single channel: A single channel selected by INCHx bits is converted repeatedly until
stopped. This mode is represented by the constant CONSEQ_2.
• Repeat sequence of channels: Repeated conversions for multiple channels, beginning with the
channel selected by INCHx bits and decrementing to channel A0. The sequence ends after conversion of
channel A0. The next trigger signal restarts the sequence. This mode is represented by the constant
CONSEQ_3.
ADC10SR bit adjusts the sampling rate.
bit is reset, the sampling rate 200 ksps.
When it is set, the sampling rate 50 ksps
REFOUT bit enables the reference voltage output
(15-13) SREFx, are used for voltage reference values
REFBURST bit controls the internal reference buffer
MSC bit allows multiple sample and conversion operations
REFON bit enables the reference generator
REF2_5V bit selects the reference voltage as either 1.5 or 2.5
V when it is reset and set
ADC10IE bit enables the interrupts
ADC10IFG bit stands for the interrupt flag
ENC bit enables the conversion
bits 12 and 11 (ADC10SHTx) S&H times ADC10SC bit starts the analog-to-digital conversion
INCHx, are reserved for the input pins
SHSx bits select the sample and hold source
ADC10DF data format for the ADC10 will be in
binary or two’s complement form
ADC10MEM register
ISSH bit enables or disables the sample input signal inversion
ADC10DIVx bits set the clock divider values
ADC10SSELx bits are used to select the clock source
CONSEQx bits are used to select the conversion mode
Single channel, single
conversion
Sequence of channels
Repeat single channel
Repeat sequence of channels
ADC10BUSYconversion is in progress
Data Transfer
Controller
Multiple Conversions Using the Data
Transfer Controller
DTC automatically transfers the conversion results from the ADC10MEM to specified memory locations
two registers ADC10DTC0 and ADC10 DTC1
ADC10DTC1 register is used to define the number
of transfers per block
ADC10TB bit is used to select the transfer mode. ADC10SA register: data transfer start address
When this bit is reset, one-block transfer mode will be active
When it is set, two-block transfer mode will be active
ADC10CT bit is reset, data transfer stops when one block (in
one-block mode) or two blocks (in two-block mode) have
completed.
ADC10B1 indicates block is filled with the ADC10 conversion results (in the two-block mode).
When this block is reset, it indicates that block 2 is filled.
When it is set, it indicates that block 1 is filled.
ADC10FETCH bit should normally be reset