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Introduction to HDL BMT702

Dr. Manjunatha K N
Associate Professor, Dept. of MTE, AIT
Dept. of MTE
Click to Edit Introduction
Module 1
 Introduction to HDL
• Hardware Description Language (HDL) is an essential
computer aided design (CAD) tool for the modern
design and synthesis of digital systems.
• The designer uses HDL to describe the system in a
computer-language code that is similar to several
commonly used software languages such as C.
• The two widely used hardware description languages
Dept. of MTE are VHDL and Verilog.
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• After writing and testing the HDL code, the user can
synthesize the code into digital logic components such
as gates and flip-flops that can be downloaded into
FPGAs
 History of HDL
• HDL has gone through continuous improvement since its
inception.
• Verilog was introduced in 1980s and has gone through
several iterations and standardization by the Institute of
Electrical and Electronic Engineers(IEEE),
• such as in December 1995 when Verilog HDL became
IEEE
• Standard 1364-1995, in 2001 when IEEE Std.
Dept. of MTE • 1364-2001 was introduced, and in 2005 when IEEE
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1800-2005 was introduced.
• VHDL, which stands for very-high-speed integrated
circuit (VHSIC) hardware description language, was
developed in the early 1980s. In 1987, the IEEE
Standard 1076- 1987 version of VHDL was introduced,
and several upgrades followed.
• In 1993, VHDL was updated and more futures were
 Structure of HDL Module
• Structure of the VHDL Module
• The word entity is a
predefined word. The
name of the entity is
Half_adder.
• Is, port, in, out,
end are predefined
words

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 Structure of the Verilog module Module
Sensitivity
keyword list

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• Verilog is case sensitive
• Module, input, output, end module are
library/predefined.
• The double slash (//) is a comment command where a
comment can be entered.
• If the comment takes more than one line, a double slash or
 Styles (Types) Of Description
• Data Flow Description
syllabus
• Behavioral Description
• Structural Description
• Switch-Level Description
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Click to Edit • Mixed-Type Description
• Mixed-Language Description
 Ports
• A simple definition of ports can be stated as a communication means
between the system to be described and the environment.
VHDL Ports
In VHDL, ports can take one of the following modes:
• in: The port is only an input port. In any assignment statement, the port
should appear only on the right-hand side of the statement (i.e., the port is
read).
• out: The port is only an output port. In any assignment statement, the port
should appear only on the left-hand side of the statement (i.e., the port is
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• buffer: The port can be used as both an input and output but can have
only one source (i.e., limited fan out). The port can appear on either the
left- or right-hand side of an assignment statement. A buffer port can only
be connected to another buffer port or to a signal that also has only one
source.
• inout: The port can be used as both an input and output.
• linkage: Same as inout but the port can only correspond to a signal.
 Verilog Ports
Verilog ports can take one of the following three modes:
• input: The port is only an input port. In any assignment
statement, the port should appear only on the right-
hand side of the statement (i.e., the port is read).
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• output: The port is an output port. In contrast to
Click to Edit VHDL, the Verilog output port can appear in either side
of the assignment statement.
• inout: The port can be used as both an input and
output. The inout port represents a bidirectional bus.
 Operators
• Logical Operators
• Relational Operators
• Arithmetic Operators
• Shift Operators
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 Logical Operators

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 Boolean and Reduction Operator

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 Relational Operators

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 Arithmetic Operators

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Dept. of MTE
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 Arithmetic Operator Precedence
• The precedence of the arithmetic operators in VHDL or Verilog is
the same as in C.
• The precedence of the major operators is listed below from highest
to lowest:
**
* / mod (%)
+-
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 Shift/Rotate Operators

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Dept. of MTE
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 Data Types Scalar type
•
•
Bit
Boolean
Composite type
•
•
Bit _vector
Array
• Integer • Record
VHDL Data Types • Real
• Character
• scalar, • Physical
• User defined
• composite, • Severity
• access,
• file, and
• other.
Verilog Data Types
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• Nets
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• Register
• Vectors
• Integers
• Real
• Parameter
• Arrays
 Scalar Types
• The values that a scalar can assume are numeric.
Numeric values can be integer, real, physical (such as
time), Boolean (0 or 1), or characters when stored as
American Standard Code for Information Interchange
(ASCII) or compatible code.
• Bit Type
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• The only values allowed here are 0 or 1. It is used to
Click to Edit describe a signal that takes only 1 (high) or 0 (low).
• Example: port (I1, I2 : in bit; O1, O2 : out bit);
 Boolean Type
• This type can assume two values: false (0) or true (1). Both
true
• and false are predefined words. One of the most frequent
applications of the Boolean type is in the if statement

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• port (I1, I2 : in bit; O1 : out bit; O2 : Boolean);
• The output of the first line, If (y =B), is Boolean: it is either true
or false.
• If true, then S = 1; if false, S = 0. Boolean can also be
specified as the port type:
 Integer Type
• the values can be negative or positive. The default
range is from –2,147,483,648 to +2,147,483,647.
• The exponent has to be of type integer, such
• as X**2 or X**y, where y is declared as integer. The
port can also be declared as type integer:
• port (I1 : in natural; I2 : in bit; O1 : out integer; O2 :
Dept. of MTE Boolean);
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Real Type
• This type accepts fractions, such as .4502, 12.5,
and –5.2E–10 where E–10 = 10-10.
• port (I1 : in natural; I2 : in real; O1 : out integer; O2 :
Boolean);
 Character Type
• This type includes characters that can be used to print
a message using, for example, the predefined
command report, such as:
• report (“Variable x is greater than Y”);
• report (“Variable x is greater than Y.”) & CR &
(“Variable x is > 2.34.”);
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• where & is the concatenation operator, and CR is a
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predefined word for carriage return.
Physical Type
• This type has values that can be measured in units,
such as time and voltage.
• An example of type time is: constant Delay_inv :
time := 1 ns;
 User-Defined Types
• The user can define a type by using the predefined word type as shown
below:
• type op is (add, mul, divide, none);
• variable opcode : op := mul;
• Type op is user defined. The variable opcode is of type op and can
therefore be instantiated to: add, mul, divide, or none.
• Severity Type
• This type is used with the assert statement. An object with type severity can
Dept. of MTE take one of four values: note, warning, error, or failure. An example of this
Click to Edit type is as follows:
• assert (Flag_full = false);
• report “The stack is full”;
• severity failure;
 Composite Types
• The composite type is a collection of values. There are
three composite types: bit vector, arrays, and records.
• An array is a collection of values all belonging to a
single type; a record is a collection of values with the
same or different types.
• Bit_vector Type
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Click to Edit • The bit_vector type represents an array of bits; each
element of the array is a single bit.
• Port (I1 : in bit; I2 : in bit_vector (5 downto 0); Sum :
out bit);
• In the above statement, port I2 is declared as type
bit_vector; it has six bits. Possible values of I2 include
110110, 011010, and 000000
 Array Type:
• This type is declared by using the predefined word
array.
• For example, the following statements declare the
variable memory to be a single dimensional array of
eight elements, and each element is an integer:

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Click to Edit • Record Type
• An object of record type is composed of elements of
the same or different
• types. An example of record type is shown below:
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Variable temp is of type forecast; type forecast includes

record, and record has three different types: integer, real, and
bit.
 Access Types
• Values belonging to an access type are pointers to
objects of other types. For example:
• type ptr_weathr is access forecast;
File Types
• Objects of type file can be read from and written to
using built-in functions and procedures that are
provided in the standard library.
Dept. of MTE
Click to Edit • Some of these procedures and functions are
file_open to open files, readline to
• read a line from the file, writeline to write a line into
the file, and file_close to close the file.
 Other Types
• There are several other types provided by external
libraries. For example,
• the IEEE library contains a package by the name of
std_logic_1164.
Std_Logic Type

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 Std_logi c_vector Type
• The following example illustrates the implementation of
type std_logic_vector:
Port (I1 : in bit; I2 : in std_logic_vector (5 downto 0); Sum :
out bit);
Signed
Variable prod : signed (3 downto 0) := 1010;
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• The above statement declares the variable prod. It is of
Click to Edit type signed, has four bits, and its initial value is 1010, or
–6
Unsigned
• Variable Qout : unsigned (3 downto 0) := 1010;
• The above statement declares variable Qout as of type
unsigned, it has four bits, and its initial value is 1010, or
10
 Verilog Data Types
Verilog supports several data types including
• nets,
• registers,
• vectors,
Click to Edit • integer,
• real,
• parameters,
• arrays.
 Nets
• Nets are declared by the predefined word wire.
• Nets have values that change continuously by the circuits that are
driving them.
• Examples of net types are as follows:
• wire sum;
• wire S1 = 1’b0;

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Register
• Register, in contrast to nets, stores values until they are updated.
• Register, as its name suggests, represents data-storage elements.
• Registeris declared by the predefined word reg.
• An example of register is: reg Sum_total;
 Vectors
• Vectors are multiple bits. A register or a net can be
declared as a vector.
• Vectors are declared by brackets [ ]. Examples of vectors
are:
• wire [3:0] a = 4’b1010;
• reg [7:0] total = 8’d12;
Integers
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• Integers are declared by the predefined word integer. An
example of integer declaration is:
• integer no_bits;
Real
• Real (floating-point) numbers are declared with the
predefined word real. Examples of real values are 2.4,
56.3, and 5e12. real weight;
 Parameter
• Parameter represents a global constant. It is declared
by the predefined word parameter. The following is an
example of implementing parameters:

Dept. of MTE
Click to Edit • To change the size of the inputs x and y, the size of the
nets sum, and the size of net Yb to eight bits
 Arrays
• Verilog, in contrast to VHDL, does not have a
predefined word for array.
• Registers and integers can be written as arrays.
Consider the following statements:

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• The above statements declare an array by the
name carry. The array carry has five elements,
and each element is four bits.
 Simulation and Synthesis

• The ultimate goal for hardware description is to synthesize

the system onto an electronic chip.
• To synthesize an HDL description, it needs to be simulated
and tested.
• The steps of simulation and synthesis in general can be
summarized as follows:
1. Choose the preferred language to describe the system.
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2. Choose the style or type of description.
Click to Edit 3. Write the code.
4. Compile the code using the compiler supplied by the HDL
package.
5. After successful compilation, the code is tested to see that it
correctly describes the system.
6. After the simulation verifies that the signals behave as
expected, the compiled code can be synthesized.
 Comparison of VHDL and Verilog

Parameter VHDL Verilog

Data Types VHDL types are built Verilog data types are very simple and
in or users can create and define easy to use. All types are defined by the language
them.
Ease of VHDL may seem hard to learn Verilog users just write the module without
Learning because of its worrying about what library or package should be
rigid type requirements. attached
Libraries Libraries and packages can be Libraries are not as easily implemented as in
and easily attached to the standard VHDL, however the basic Verilog package
Packages VHDL package. includes several libraries as integer part of the
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verbose, strongly typed, good for concise, C-like, fast for prototyping, dominant in
large & safety-critical projects. chip design.