Digital Systems Design
Processor Logic Design
Introduction
• A computer CPU must manipulate not only data but also instruction codes and
addresses coming from memory.
• The register that holds and manipulates the operation code of instructions is
considered to be part of the control unit.
• Here, we will learn about the general-purpose register, commonly called an
accumulator.
Processor Organization
• In a well organized processor unit, the data paths are formed by means of buses
and other common lines.
• The control gates that formulate the given path are essentially multiplexers and
decoders whose selection lines specify the required path.
• All organizations employ a common ALU and shifter.
• The differences in organizations are mostly manifested in the organization of the
registers and their common path to the ALU.
Bus Organization
• When a large number of registers are included
in a processor unit, it is most efficient to
connect them through common buses or
arrange them as a small memory having very
fast access time.
• In the figure, there are 4 processor registers.
Each register is connected to 2 MUXs to form
input buses A and B.
• The result from the shifter goes through the
output bus S into the inputs of all registers.
Scratchpad Memory
• The registers in a processor unit can be
enclosed within a small memory unit. This
memory is called scratchpad memory.
• For example, a processor unit employs 8
registers of 16 bits each. The 8 memory
words can be designated R0 through R7.
• A single register can be selected by means
of an address to the memory unit.
2-Port Memory
• Some processors employ a 2-port memory
in order to overcome the delay caused
when reading 2 source registers.
• When enabled by the memory enable
(ME) input, new data can be written into
the word specified by the B address.
Accumulator Register Input data
• Some processor units separate one register from all Processor registers
Select B
others and call it an accumulator register (AC or A source or Memory Unit
register).
A B
• It is a multipurpose register capable of performing
not only the add microoperation, but many other
ALU
microoperations as well.
• To form the sum of 2 numbers stored in processor
unit, we need;
Accumulator
T1: A←0 Register
T2: A ← A + R1
T3: A ← A + R2
Output data
Arithmetic Logic Unit
• ALU can perform a set of basic arithmetic
operations and a set of logic operations. A B
• It has a number of selection lines to select a
particular operation in the unit.
s2
• The selection lines are decoded within the ALU so Arithmetic Logic Unit
s1
Cout s0
that k selection variables can specify up to 2k (ALU) Cin
distinct operations.
F
Design of Arithmetic Circuit
• The basic component of the arithmetic section
of an ALU is a parallel adder.
• A parallel adder is constructed with a number
of full-adder circuits connected in cascade.
• The circuit that controls input B to provide the
functions is called a true/complement, one/zero
element.
S1 S0 Yi
0 0 0
0 1 Bi
1 0 B i’
1 1 1
Design of Arithmetic Circuit
F=A+ Y+ Cin
Function select
Y equals Output equals
s1 s0 Cin
0 0 0 0 F=A
0 0 1 0 F=A+1
0 1 0 B F=A+B
0 1 1 B F=A+B+1
1 0 0 B’ F = A + B’
1 0 1 B’ F = A + B’ + 1
1 1 0 All 1’s F=A–1
1 1 1 All 1’s F=A
Design of Logic Circuit
s1 s0 Output Operation
0 0 F=A+B OR
0 1 F=A B XOR
1 0 F = AB AND
1 1 F’ = A’ NOT
Design of Arithmetic
Logic Unit
• To combine the two unit we need another
selection line s2.
Status Register
• It is sometimes convenient to supplement
the ALU with a status register where
these status-bit conditions are stored for
further analysis.
• Status-bit conditions are sometimes
called condition-code bits or flag bits.
Design of Shifter
• The shifter may transfer the
information directly without
a shift, or it may shift the
information to the right or to
the left.
• H2 may be employed to
specify IR or IL during shift.
H1 H0 Operation
0 0 No shift
0 1 Shift right
1 0 Shift left
1 1 Assign zero
1..3 4..6 7..9 10..12 13 14..16
Control word A B D F Ci H
Processor Unit n
• The selection variables in a processor unit
control the microoperations executed within
the processor during any given clock pulse.
• 16 selection variables in the unit and their
functions are specified by a control word.
• The control word is partitioned into 6 fields
with each field designated by a letter name.
Design of Accumulator
• An accumulator is a sequential circuit with A register and
the associated combinational circuit. It requires control
variables p1 through p9 generated by control logic circuits.
Register A
Control variable Microoperation Name
p1 A←A+B Add
p2 A←0 Clear
p3 A←A’ Complement Combinational
p4 A←A˄B AND Circuit Control
variables
p5 A←A˅B OR
p6 A←AB Exclusive-OR
p7 A← shr A Shift right B
p8 A← shl A Shift left Data inputs
One Stage of Accumulator
• The register we are using here is of JK-type
flip-flops.
• We must ensure that only one control
variable is enabled at any given time.
Complete Accumulator
• Finally an accumulator with n
bits requires n stages connected
in cascade, with each stage
having the circuit in the figure.