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Sequential Circuits in Autonomous Systems

The document is a module on Sequential Circuits from the Introduction to Autonomous Systems course, detailing concepts of asynchronous and synchronous circuits, latches, and flip-flops. It covers various types of latches like SR and D latches, their characteristics, and timing diagrams, as well as flip-flops including JK and T flip-flops. The document provides characteristic tables and equations for analyzing these components in digital systems.

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anfelnova0404
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4 views32 pages

Sequential Circuits in Autonomous Systems

The document is a module on Sequential Circuits from the Introduction to Autonomous Systems course, detailing concepts of asynchronous and synchronous circuits, latches, and flip-flops. It covers various types of latches like SR and D latches, their characteristics, and timing diagrams, as well as flip-flops including JK and T flip-flops. The document provides characteristic tables and equations for analyzing these components in digital systems.

Uploaded by

anfelnova0404
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Natnal School of Autonomous Systems Technologies

ioSecond Year Engineering

Module
Introduction to Autonomous Systems 1

Second Year Engineering

Dr Yasmine GUERBAI
E mail:[Link]@[Link]
Chapter 2

Sequential Circuits
Sequential Circuits
 Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

 Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

3 / 30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0

R
0 0
Q

S Q
0 1

Initial Value

4 / 30
Sequential Circuits
 Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

 Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

5 / 30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q

S Q
0 0

6 / 30
Sequential Circuits
 Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

 Synchronous

Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

7 / 30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 0
Q

S Q
0 1

8 /30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 1 0 1 Q=0
Q

S Q
0 0

9 / 30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1

S Q
1 1

10 / 30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

S Q
1 0

11 / 30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10

12 / 30
Latches
 SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0

13 / 60
Latches
 SR Latch
S R Q
R Q 0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S R Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
14 / 30
Latches
 SR Latch
S R Q
R Q 0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
S Q 1 1 Q=Q’=0 Invalid

S S’ R’ Q
Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
Q 1 0 0 Reset
R 1 1 Q0 No change
15 / 30
Controlled Latches
 SR Latch with Control Input
R R S S
Q Q
C C
S Q R Q
S R

C S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q=Q’ Invalid
16 / 30
Controlled Latches
 D Latch (D = Data) Timing Diagram

S
C
D
Q
C
D
R Q
Q

t
C D Q
Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

17 /30
Controlled Latches
 D Latch (D = Data) Timing Diagram

S
C
D
Q
C
D
R Q
Q

C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

18 / 30
Flip-Flops
 Controlled latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

19 / 30
Flip-Flops
 Master-Slave D Flip-Flop

D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C

Master Slave
CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
20 / 30
Flip-Flops
 Edge-Triggered D Flip-Flop
D Q

Q Positive
Edge
CLK
D Q
Q

D Negative Edge

21 /30
Flip-Flops
 JK Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
22 / 30
Flip-Flops
 T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T  Q Q

23 / 30
Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q 1 Q’(t) Toggle
24 / 30
Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0
Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t)
Q Q(t+1) = T  Q
1 Q’(t)
25 / 30
Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
J Q 0 0 1 1
0 1 0
Reset
0 1 1
K Q
1 0 0
Set
1 0 1
1 1 0 Toggle
1 1 1

26 / 30
Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
J Q 0 0 1 1
0 1 0 0
Reset
0 1 1 0
K Q
1 0 0
Set
1 0 1
1 1 0 Toggle
1 1 1

27 / 30
Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
J Q 0 0 1 1
0 1 0 0
Reset
0 1 1 0
K Q
1 0 0 1
Set
1 0 1 1
1 1 0 Toggle
1 1 1

28 / 30
Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
J Q 0 0 1 1
0 1 0 0
Reset
0 1 1 0
K Q
1 0 0 1
Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

29 / 30
Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q 0 0 1 1 K
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q
1 0 0 1 Q
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q


30 / 30
Flip-Flops with Direct Inputs
 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q
R
Reset

31 / 30
Flip-Flops with Direct Inputs
 Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 x x 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset

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