ECT 206
COMPUTER
ARCHITECTURE AND
MICROCONTROLLERS
ECT 206
• Preamble: This course aims to impart
knowledge of basic computer architecture and
modern microcontrollers.
• Prerequisite: ECT203 Logic Circuit Design
2
Course Outcomes:
• After the completion of the course the student
will be able to :
CO1 Explain the functional units, I/O and memory management w.r.t
a typical computer architecture.
CO2 Distinguish between microprocessor and microcontroller.
CO3 Develop simple programs using assembly language
programming.
CO4 Interface 8051 microcontroller with peripheral devices using
ALP/Embedded C
CO5 Familiarize system software and Advanced RISC Machine
Architecture.
3
Module 1: Computer Arithmetic and
Processor Basics
• Algorithms for binary multiplication and division.
• Fixed and floating-point number representation.
• Functional units of a computer, Von Neumann and Harvard
computer architectures, CISC and RISC architectures.
• Processor Architecture – General internal architecture,
Address bus, Data bus, control bus.
• Register set – status register, accumulator, program counter,
stack pointer, general purpose registers.
• Processor operation – instruction cycle, instruction fetch,
instruction decode, instruction execute, timing response,
instruction sequencing and execution (basic concepts,
datapath. Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 4
and beyond, Pearson, 2011.
2’s Complement
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Integer ranges
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Binary multiplication
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Binary multiplication
• Method of Repeated Additions
• Other Method – Booth’s Algorithm
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 8
Booth’s algorithm
• Arithmetic Right-Shift
• Fig : 4 bit arithmetic right-shift a) positive and
b) negative binary integer
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 9
Locations involved for Booth's
algorithm
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Details of Shift Operation
Condition check and actions to be taken before every shift
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Booth’s Algorithm and flow chart
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Booth’s Algorithm and flow chart
• Step 1: Load multiplicand in MD, multiplier in MR. For negative
numbers, two's complement format to be used.
• Step 2: Initialize the down counter CR by the number of bits
involved.
• Step 3: Clear locations PD (n-bits) and Mx (1-bit).
• Step 4: Check LS bit of MR and Mx jointly. If the pattern is 00 or
11 then go to Step 5. If 10, then PD = PD - MD. If 01, then PD =
PD +MD.
• Step 5: Perform arithmetic right-shift with PD, MR and Mx. LS of
PD goes to MS of MR and LS of MR goes to Mx. Old content of
Mx is discarded.
• Step 6: Decrement CR by one. If CR is not zero then go to Step 4.
• Step 7: Final result (or the product) is available in PD (higher
part) and MR (lower part).
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Illustration of Booth's algorithm for 2 x3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 14
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for 2 x3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 15
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for 2 x3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 16
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for 2 x3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 17
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for 2 x3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 18
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for 2 x3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 19
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for 2 x3
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 20
Illustration of Booth's algorithm for (-2) x 3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 21
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for (-2) x 3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 22
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for (-2) x 3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 23
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for (-2) x 3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 24
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for (-2) x 3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 25
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for (-2) x 3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 26
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for (-2) x 3
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 27
and beyond, Pearson, 2011.
Illustration of Booth's algorithm for 2 x (-3)
28
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011.
Multiplication With Signed
Integers
• Easily implemented using Booth’s algorithm
• If signed integers are represented using signed-representation
scheme, then sign of the result is separately evaluated.
• Product is found out using the absolute value of multiplier and
multiplicand.
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 29
Division Algorithms
•Paper And Pencil Method:
– Take an example where dividend is 5 and divisor is 2
– The numbers are represented as 0101 and 0010
respectively.
– The dividend is scanned one digit at a time, from left to
right, and if not divisible, a zero is placed in the quotient.
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 30
Division Algorithms
• Division algorithm uses several locations as Booth’s
algorithm for multiplication.
• Left-shift of two locations have to be performed.
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 31
Locations And Counters In
Division Algorithm
• Four locations, each n-bit wide is required, where n is the
number of bits in dividend and divisor.
• Locations designated as V, R, D and C
• V contains n-bit divisor (2’s complement form)
• C contains the n- bit counter initially loaded by n
• n-bit dividend is expanded to 2n-bit form and
loaded in R and Q.
• R is loaded with MSBs and Q LSBs.
• If the dividend is negative, change to 2’s
complement form, expand to 2n bits and load in R
and Q
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 32
Details of Shift Operation
• One-bit left shift operation is performed.
• One bit left shift of R and Q is performed.
• A zero ‘0’ is inserted in the LSB of Q.
• The MSB of Q becomes the LSB of R.
• The MSB of R is moved out and discarded.
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 33
Algorithm For Division OF Signed
Integers
• Step1: Load V by n-bit divisor using two’s complement form for negative
numbers.
• Step2: Load n-bit dividend in R and Q after expanding it to 2n bits after
maintaining its sign .
• Step3: Load C by the number of bits being considered i.e. n.
• Step4: Perform 1-bit left shift of R and Q, inserting a 0 in the LSB of Q.
• Step5: If the divisor in V and R have the same sign, then replace R by R – V
otherwise replace R by R + V.
• Step6: If the sign of R remains unchanged after Step5, or R becomes zero,
then set LSB of Q as 1. If the sign of R changes after Step5 and R
becomes non-zero, then restore the value of R as it was after Step4.
• Step7: Decrement C by 1, and if it is not zero goto Step4.
• Step8: Find the remainder in R. If the divisor and dividend have the same
sign, then Q indicates the quotient, otherwise its two’s complement
would be the correct quotient.
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 34
Illustration of Division algorithm for 5 / 2
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Illustration of Division algorithm for 5 / 2
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 36
Illustration of Division algorithm for 5 / 2
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011.- 37
Illustration of Division algorithm for 5 / 2
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 38
Illustration of Division algorithm for 5 / 2
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Fixed and floating point
number representation
• Fixed point representation
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Floating point representation
• Scientific notation scheme
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Floating point representation
• Biasing the exponent (ex 3 bit)
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Floating point representation
• Different way of expressing the same value in
scientific notation
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 43
Floating point representation
• Binary point and positional values
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Floating point representation
• Example of normalization for binary number in
scientific notation
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Floating point representation
• Conversion of a sample binary representation
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Floating point representation
• Examples
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Floating point representation
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IEEE 754 Format
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IEEE 754 Format – Example 1
Represent (85.125)10 as a 32 bit number in IEEE 754 format
(85)10 = (1010101)2
(0.125)10= (001)2
85.125 = 1010101.001 =1.010101001 x 26
sign value is 0
Single precision:
biased exponent 127+6=133
133 = 10000101
normalised mantisa = 010101001 we need to add 0's to
complete the 23 bits 🡪 01010100100000000000000
IEEE 754 Single precision 🡪
0 10000101 01010100100000000000000
Subrata Ghoshal, Computer Architecture and Organization: From 8085 to Core2Duo and beyond, Pearson, 2011. 50
IEEE 754 Format – Example1
Represent (85.125)10 as a 64 bit number in IEEE 754 format
Double precision: 64 bits
biased exponent 1023+6=1029
(1029) 10= (10000000101)2
Normalised mantisa = 010101001 we will add 0's to complete
the 52 bits
i.e.
0101010010000000000000000000000000000000000000000000
IEEE 754 Double precision 🡪
0 10000000101 0101010010000000000000000000000000000000000000000000
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ECT 206
• Reference : Subrata Ghoshal, Computer
Architecture and Organization: From 8085 to
Core2Duo and beyond, Pearson, 2011.
Subrata Ghoshal, Computer Architecture
and Organization: From 8085 to Core2Duo 52
and beyond, Pearson, 2011.