COMPUTER ORGANIZATION AND DESIGN

5
Edition
th

The Hardware/Software Interface

MIPS Instruction Set and

Assembly Language
 §2.1 Introduction
Instruction Set
 The repertoire of instructions of a
computer
 Different computers have different
instruction sets
 But with many aspects in common
 Early computers had very simple
instruction sets
 Simplified implementation
 Many modern computers also have simple
instruction sets

Chapter 2 — Instructions: Language of the Computer — 2

The MIPS Instruction Set
 Used as the example throughout the book
 Stanford MIPS commercialized by MIPS
Technologies ([Link])
 Large share of embedded core market
 Applications in consumer electronics, network/storage
equipment, cameras, printers, …
 Typical of many modern ISAs
 See MIPS Reference Data tear-out card, and
Appendixes B and E

Chapter 2 — Instructions: Language of the Computer — 3

 §2.2 Operations of the Computer Hardware
Arithmetic Operations
 Add and subtract, three operands
 Two sources and one destination
add a, b, c # a = b + c
 All arithmetic operations have this form
 Design Principle 1: Simplicity favours
regularity
 Regularity makes implementation simpler
 Simplicity enables higher performance at
lower cost

Chapter 2 — Instructions: Language of the Computer — 4

Arithmetic Example
 C code:
f = (g + h) - (i + j);
 Pseudo MIPS code:
add t0, g, h # temp t0 = g + h
add t1, i, j # temp t1 = i + j
sub f, t0, t1 # f = t0 - t1

Chapter 2 — Instructions: Language of the Computer — 5

 §2.3 Operands of the Computer Hardware
Register Operands
 Arithmetic instructions use register
operands
 MIPS has a 32 × 32-bit register file
 Use for frequently accessed data
 Numbered 0 to 31
 32-bit data called a “word”
 Assembler names
 $t0, $t1, …, $t9 for temporary values
 $s0, $s1, …, $s7 for saved variables
 Design Principle 2: Smaller is faster
 cf. main memory: millions of locations

Chapter 2 — Instructions: Language of the Computer — 6

Register Operand Example
 C code:
f = (g + h) - (i + j);
 f, …, j in $s0, …, $s4

 Compiled MIPS code:

add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1

Chapter 2 — Instructions: Language of the Computer — 7

Memory Operands
 Main memory used for composite data

Arrays, structures, dynamic data
 To apply arithmetic operations

Load values from memory into registers

Store result from register to memory
 Memory is byte addressed 0 32 bits of data

Each address identifies an 8-bit byte 4 32 bits of data
 Words are aligned in memory 8 32 bits of data


Address must be a multiple of 4 12 32 bits of data

 MIPS is Big Endian ...


Most-significant byte at least address of a word

cf. Little Endian: least-significant byte at least address

Chapter 2 — Instructions: Language of the Computer — 8

 Byte Addresses
 Since 8-bit bytes are so useful, most architectures
address individual bytes in memory
 Alignment restriction - the memory address of a word must be on
natural word boundaries (a multiple of 4 in MIPS-32)
 Big Endian: leftmost byte is word address
IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
 Little Endian: rightmost byte is word address
Intel 80x86, DEC Vax, DEC Alpha

Example : 0*2563 + 1*2562 + 2*256 + 3 = 66051

(0x 00 01 02 03) (03 02 01 00)
 little endian byte 0

00 01 02 03

big endian byte 0 

(00 01 02 03)
Load Instruction
 Load/Store Instruction Format (I format):
lw $t0, 24($s3)

Memory
2410 + $s3 = 0xf f f f f f f f

. . . 0001 1000 0x120040ac

$t0
+ . . . 1001 0100
. . . 1010 1100 = $s3 0x12004094

0x120040ac
0x0000000c
0x00000008
0x00000004
0x00000000
data word address (hex)
Memory Operand Example 1
 C code:
g = h + A[8];
 g in $s1, h in $s2, base address of A in $s3

 Compiled MIPS code:

 Index 8 requires offset of 32

4 bytes per word
lw $t0, 32($s3) # load word
add $s1, $s2, $t0

offset base register

Chapter 2 — Instructions: Language of the Computer — 11

Memory Operand Example 2
 C code:
A[12] = h + A[8];
 h in $s2, base address of A in $s3

 Compiled MIPS code:

 Index 8 requires offset of 32
lw $t0, 32($s3) # load word
add $t0, $s2, $t0
sw $t0, 48($s3) # store word

Chapter 2 — Instructions: Language of the Computer — 12

Memory Operand Example 3
C Code: g=h+A[i];

Assumption: g  $s1
h  $s2
A$s3
i$s4

MIPS Code: add $t1,$s4,$s4

add $t1,$t1,$t1
add $t1,$t1,$s3
lw $t0,0($t1)
add $s1,$s2,$t0
 Our First Example
 Can you figure out the code?
swap(int v[ ], int k);
{
int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}

swap:
add $2, $5, $5
add $2 ,$2, $2
v$4 add $2, $4, $2
lw $15, 0($2)
k$5 lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
jr $31
So far we’ve learned:
 MIPS
— loading words but addressing bytes
— arithmetic on registers only

 Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3

sub $s1, $s2, $s3 $s1 = $s2 – $s3
lw $s1, 100($s2) $s1 = Memory[$s2+100]
sw $s1, 100($s2) Memory[$s2+100] = $s1
Registers vs. Memory
 Registers are faster to access than
memory
 Operating on memory data requires loads
and stores
 More instructions to be executed
 Compiler must use registers for variables
as much as possible
 Only spill to memory for less frequently used
variables
 Register optimization is important!

Chapter 2 — Instructions: Language of the Computer — 16

Immediate Operands
 Constant data specified in an instruction
addi $s3, $s3, 4
 No subtract immediate instruction
 Just use a negative constant
addi $s2, $s1, -1
 Design Principle 3: Make the common
case fast
 Small constants are common
 Immediate operand avoids a load instruction

Chapter 2 — Instructions: Language of the Computer — 17

The Constant Zero
 MIPS register 0 ($zero) is the constant 0
 Cannot be overwritten
 Useful for common operations
 E.g., move between registers
add $t2, $s1, $zero

Chapter 2 — Instructions: Language of the Computer — 18

 §2.4 Signed and Unsigned Numbers
Unsigned Binary Integers
 Given an n-bit number
n 1 n 2 1 0
x x n  1 2  x n 2 2    x1 2  x 0 2
 Range: 0 to +2n – 1
 Example
 0000 0000 0000 0000 0000 0000 0000 10112
= 0 + … + 1×23 + 0×22 +1×21 +1×20
= 0 + … + 8 + 0 + 2 + 1 = 1110
 Using 32 bits
 0 to +4,294,967,295

Chapter 2 — Instructions: Language of the Computer — 19

2s-Complement Signed Integers
 Given an n-bit number
n 1 n 2 1 0
x  x n 1 2  x n 2 2    x1 2  x 0 2
 Range: –2n – 1 to +2n – 1 – 1
 Example
 1111 1111 1111 1111 1111 1111 1111 11002
= –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= –2,147,483,648 + 2,147,483,644 = –410
 Using 32 bits
 –2,147,483,648 to +2,147,483,647

Chapter 2 — Instructions: Language of the Computer — 20

2s-Complement Signed Integers
 Bit 31 is sign bit
 1 for negative numbers
 0 for non-negative numbers
 –(–2n – 1) can’t be represented
 Non-negative numbers have the same unsigned
and 2s-complement representation
 Some specific numbers
 0: 0000 0000 … 0000
 –1: 1111 1111 … 1111
 Most-negative: 1000 0000 … 0000
 Most-positive: 0111 1111 … 1111

Chapter 2 — Instructions: Language of the Computer — 21

Review: Unsigned Binary Representation
Hex Binary Decimal
0x00000000 0…0000 0
0x00000001 0…0001 1 231 230 229 ... 2 3 22 21 20 bit weight
0x00000002 0…0010 2
31 30 29 ... 3 2 1 0 bit position
0x00000003 0…0011 3
0x00000004 0…0100 4 1 1 1 ... 1 1 1 1 bit

0x00000005 0…0101 5
0x00000006 0…0110 6 1 0 0 0 ... 0 0 0 0 - 1
0x00000007 0…0111 7
0x00000008 0…1000 8
0x00000009 0…1001 9
232 - 1
…
0xFFFFFFFC 1…1100 232 - 4
0xFFFFFFFD 1…1101 232 - 3
0xFFFFFFFE 1…1110 232 - 2
0xFFFFFFFF 1…1111 232 - 1
 Review: Signed Binary Representation
2’sc binary decimal
-23 = 1000 -8
-(23 - 1) = 1001 -7
1010 -6
1011 -5
complement all the bits 1100 -4
1101 -3
0101 1011
1110 -2
and add a 1 1111 -1
and add a 1 0000 0
1010 0001 1
0110
0010 2
complement all the bits 0011 3
0100 4
0101 5
0110 6
0111 7
23 - 1 =
Signed Negation
 Complement and add 1
 Complement means 1 → 0, 0 → 1

x  x 1111...111 2  1

x  1  x
 Example: negate +2
 +2 = 0000 0000 … 00102
 –2 = 1111 1111 … 11012 + 1
= 1111 1111 … 11102

Chapter 2 — Instructions: Language of the Computer — 24

Sign Extension
 Representing a number using more bits
 Preserve the numeric value
 In MIPS instruction set
 addi: extend immediate value
 lb, lh: extend loaded byte/halfword
 beq, bne: extend the displacement
 Replicate the sign bit to the left
 c.f. unsigned values: extend with 0s
 Examples: 8-bit to 16-bit
 +2: 0000 0010 => 0000 0000 0000 0010
 –2: 1111 1110 => 1111 1111 1111 1110

Chapter 2 — Instructions: Language of the Computer — 25

 §2.5 Representing Instructions in the Computer
Representing Instructions
 Instructions are encoded in binary
 Called machine code
 MIPS instructions
 Encoded as 32-bit instruction words
 Small number of formats encoding operation code
(opcode), register numbers, …
 Regularity!
 Register numbers
 $t0 – $t7 are reg’s 8 – 15
 $t8 – $t9 are reg’s 24 – 25
 $s0 – $s7 are reg’s 16 – 23

Chapter 2 — Instructions: Language of the Computer — 26

 Register File
Name Register number Usage
$zero 0 the constant value 0
$v0-$v1 2-3 values for results and expression evaluation
$a0-$a3 4-7 arguments
$t0-$t7 8-15 temporaries
$s0-$s7 16-23 saved
$t8-$t9 24-25 more temporaries
$gp 28 global pointer
$sp 29 stack pointer
$fp 30 frame pointer
$ra 31 return address

Chapter 2 — Instructions: Language of the Computer — 27

MIPS R-format Instructions
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

 Instruction fields
 op: operation code (opcode)
 rs: first source register number
 rt: second source register number
 rd: destination register number
 shamt: shift amount (00000 for now)
 funct: function code (extends opcode)

Chapter 2 — Instructions: Language of the Computer — 28

R-format Example
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

Chapter 2 — Instructions: Language of the Computer — 29

Hexadecimal
 Base 16
 Compact representation of bit strings
 4 bits per hex digit

0 0000 4 0100 8 1000 c 1100

1 0001 5 0101 9 1001 d 1101
2 0010 6 0110 a 1010 e 1110
3 0011 7 0111 b 1011 f 1111

 Example: 0x eca8 6420

 1110 1100 1010 1000 0110 0100 0010 0000

Chapter 2 — Instructions: Language of the Computer — 30

MIPS I-format Instructions
op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

 Immediate arithmetic and load/store instructions

 rt: destination or source register number
 Constant: –215 to +215 – 1
 Address: offset added to base address in rs
 Design Principle 4: Good design demands good
compromises
 Different formats complicate decoding, but allow 32-bit
instructions uniformly
 Keep formats as similar as possible

Chapter 2 — Instructions: Language of the Computer — 31

 Machine Language
 Consider the load-word and store-word instructions,
 What would the regularity principle have us do?
 New principle: Good design demands a compromise
 Introduce a new type of instruction format
 I-type for data transfer instructions

 Example: lw $t0, 32($s2)

35 18 8 32
6 bit op 5 bit rs 5 bit rt 16 bit number
 Where's the compromise?
 Example
Assuming that $t1 has the base of the array A and that $s2 corresponds
to h, the C assignment statement

A[300]=h+A[300];

Is compiled into

lw $t0, 1200($t1)
add $t0, $s2, $t0
sw $t0, 1200($t1)

What is the MIPS machine language code for these three instructions?
 Decoding Machine Code
 What is the assembly language
corresponding to this machine instruction?
0000 0000 1010 1111 1000 0000 0010 0000

 000000 00101 01111 10000 00000 100000

 add $s0, $a1, $t7

Stored Program Computers
The BIG Picture
 Instructions represented in
binary, just like data
 Instructions and data stored
in memory
 Programs can operate on
programs
 e.g., compilers, linkers, …
 Binary compatibility allows
compiled programs to work
on different computers
 Standardized ISAs

Chapter 2 — Instructions: Language of the Computer — 35

 §2.6 Logical Operations
Logical Operations
 Instructions for bitwise manipulation
Operation C Java MIPS
Shift left << << sll
Shift right >> >>> srl
Bitwise AND & & and, andi
Bitwise OR | | or, ori
Bitwise NOT ~ ~ nor

 Useful for extracting and inserting

groups of bits in a word
Chapter 2 — Instructions: Language of the Computer — 36
Shift Operations
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
 sllv $t0, $t1, $t2
 sll $t0, $t1, shamt
 shamt: how many positions to shift
 Shift left logical
 Shift left and fill with 0 bits
 sll by i bits  multiplies by 2i
 Shift right logical
 Shift right and fill with 0 bits
 srl by i bits  divides by 2i (unsigned only)
Chapter 2 — Instructions: Language of the Computer — 37
AND Operations
 Useful to mask bits in a word
 Select some bits, clear others to 0
and $t0, $t1, $t2

$t2 0000 0000 0000 0000 0000 1101 1100 0000

$t1 0000 0000 0000 0000 0011 1100 0000 0000 mask

$t0 0000 0000 0000 0000 0000 1100 0000 0000

Chapter 2 — Instructions: Language of the Computer — 38

OR Operations
 Useful to include bits in a word
 Set some bits to 1, leave others unchanged
or $t0, $t1, $t2

$t2 0000 0000 0000 0000 0000 1101 1100 0000

$t1 0000 0000 0000 0000 0011 1100 0000 0000 mask

$t0 0000 0000 0000 0000 0011 1101 1100 0000

Chapter 2 — Instructions: Language of the Computer — 39

NOT Operations
 Useful to invert bits in a word
 Change 0 to 1, and 1 to 0
 MIPS has NOR 3-operand instruction
 a NOR b == NOT ( a OR b )
nor $t0, $t1, $zero Register 0: always
read as zero

$t10000 0000 0000 0000 0011 1100 0000 0000

1111 1111 1111 1111 1100 0011 1111 1111

$t0

Chapter 2 — Instructions: Language of the Computer — 40

 §2.7 Instructions for Making Decisions
Conditional Operations
 Branch to a labeled instruction if a
condition is true
 Otherwise, continue sequentially
 beq rs, rt, L1
 if (rs == rt) branch to instruction labeled L1;
 bne rs, rt, L1
 if (rs != rt) branch to instruction labeled L1;
 j L1
 unconditional jump to instruction labeled L1

Chapter 2 — Instructions: Language of the Computer — 41

 Compiling If Statements
 C code:
if (i==j) f = g+h;
else f = g-h;
 f, g, h,… in $s0, $s1 , $s2, …
 Compiled MIPS code:
bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit: …
Assembler calculates addresses

Chapter 2 — Instructions: Language of the Computer — 42

Compiling Loop Statements 1
C Code  Loop: g=g+A[i];
i=i+j;
if (i!=h) goto Loop;

Assumption  g$s1
h$s2
i$s3
j$s4
A$s5

MIPS Code 
Compiling Loop Statements 2
 C code:
while (save[i] == k) i += 1;

i in $s3, k in $s5, address of save in $s6
 Compiled MIPS code:
Loop: sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
addi $s3, $s3, 1
j Loop
Exit: …

Chapter 2 — Instructions: Language of the Computer — 44

Basic Blocks
 A basic block is a sequence of instructions
with
 No embedded branches (except at end)
 No branch targets (except at beginning)

 A compiler identifies basic

blocks for optimization
 An advanced processor
can accelerate execution
of basic blocks

Chapter 2 — Instructions: Language of the Computer — 45

More Conditional Operations
 Set result to 1 if a condition is true
 Otherwise, set to 0
 slt rd, rs, rt
 if (rs < rt) rd = 1; else rd = 0;
 slti rt, rs, constant
 if (rs < constant) rt = 1; else rt = 0;
 Use in combination with beq, bne
slt $t0, $s1, $s2 # if ($s1 < $s2)
bne $t0, $zero, L # branch to L

Chapter 2 — Instructions: Language of the Computer — 46

Branch Instruction Design
 Why not blt, bge, etc?
 Hardware for <, ≥, … slower than =, ≠
 Combining with branch involves more work
per instruction, requiring a slower clock
 All instructions penalized!
 beq and bne are the common case
 This is a good design compromise

Chapter 2 — Instructions: Language of the Computer — 47

 Aside: More Branch Instructions
 Can use slt, beq, bne, and the fixed value of 0 in
register $zero to create other conditions
 less than blt $s1, $s2, Label
slt $at, $s1, $s2 #$at set to 1 if
bne $at, $zero, Label #$s1 < $s2

 less than or equal to ble $s1, $s2, Label

 greater than bgt $s1, $s2, Label
 great than or equal to bge $s1, $s2, Label

 Such branches are included in the instruction set as

pseudo instructions - recognized (and expanded) by the
assembler
 Its why the assembler needs a reserved register ($at)
Conditional Statements
if (A<=B)
A=A+B
 So far:
 Instruction Meaning

add $s1,$s2,$s3 $s1 = $s2 + $s3

sub $s1,$s2,$s3 $s1 = $s2 – $s3
lw $s1,100($s2) $s1 = Memory[$s2+100]
sw $s1,100($s2) Memory[$s2+100] = $s1
bne $s4,$s5,L Next instr. is at Label if $s4!= $s5
beq $s4,$s5,L Next instr. is at Label if $s4 = $s5
j Label Next instr. is at Label
slt $s1,$s2,$s3
 Addresses are not 32 bits
— How do we handle this with load and store instructions?
 Formats:
R op rs rt rd shamt funct
I op rs rt 16 bit address
J op 26 bit address
Signed vs. Unsigned
 Signed comparison: slt, slti
 Unsigned comparison: sltu, sltui
 Example
 $s0 = 1111 1111 1111 1111 1111 1111 1111 1111
 $s1 = 0000 0000 0000 0000 0000 0000 0000 0001
 slt $t0, $s0, $s1 # signed

–1 < +1  $t0 = 1
 sltu $t0, $s0, $s1 # unsigned

+4,294,967,295 > +1  $t0 = 0

Chapter 2 — Instructions: Language of the Computer — 51

 §2.8 Supporting Procedures in Computer Hardware
Procedure Calling
 Steps required
1. Place parameters in registers
2. Transfer control to procedure
3. Acquire storage for procedure
4. Perform procedure’s operations
5. Place result in register for caller
6. Return to place of call

Chapter 2 — Instructions: Language of the Computer — 52

 Six Steps in Execution of a Procedure
1. Main routine (caller) places parameters in a place where the
procedure (callee) can access them
 $a0 - $a3: four argument registers
2. Caller transfers control to the callee
3. Callee acquires the storage resources needed
4. Callee performs the desired task
5. Callee places the result value in a place where the caller can
access it
 $v0 - $v1: two value registers for result values
6. Callee returns control to the caller
 $ra: one return address register to return to the point of origin

Calling procedures  jal Procedure Address

Procedure returns  jr $ra
Register Usage
 $a0 – $a3: arguments (reg’s 4 – 7)
 $v0, $v1: result values (reg’s 2 and 3)
 $t0 – $t9: temporaries
 Can be overwritten by callee
 $s0 – $s7: saved
 Must be saved/restored by callee
 $gp: global pointer for static data (reg 28)
 $sp: stack pointer (reg 29)
 $fp: frame pointer (reg 30)
 $ra: return address (reg 31)

Chapter 2 — Instructions: Language of the Computer — 54

Corresponding Registers
Name Register Usage Preserve
Number on call?
$zero 0 constant 0 (hardware) n.a.
$at 1 reserved for assembler n.a.
$v0 - $v1 2-3 returned values no
$a0 - $a3 4-7 arguments yes
$t0 - $t7 8-15 temporaries no
$s0 - $s7 16-23 saved values yes
$t8 - $t9 24-25 temporaries no
$gp 28 global pointer yes
$sp 29 stack pointer yes
$fp 30 frame pointer yes
$ra 31 return addr (hardware) yes
Chapter 2 — Instructions: Language of the Computer — 55
Procedure Call Instructions
 Procedure call: jump and link
jal ProcedureLabel
 Address of following instruction put in $ra

 Jumps to target address

 Procedure return: jump register

jr $ra
 Copies $ra to program counter

 Can also be used for computed jumps


e.g., for case/switch statements

Chapter 2 — Instructions: Language of the Computer — 56

Leaf Procedure Example
 C code:
int leaf (int g, h, i, j)
{
int f;
f = (g + h) - (i + j);
return f;
}
 Arguments g, …, j in $a0, …, $a3

 f in $s0 (hence, need to save $s0 on stack)

 Result in $v0

Chapter 2 — Instructions: Language of the Computer — 57

Leaf Procedure Example
int leaf (int g, h, i, j)
{
 MIPS code: int f;
leaf_example: f = (g + h) - (i + j);
return f;
addi $sp, $sp, -4 }
Save $s0 on stack
sw $s0, 0($sp)
add $t0, $a0, $a1
add $t1, $a2, $a3 Procedure body
sub $s0, $t0, $t1
add $v0, $s0, $zero Result
lw $s0, 0($sp)
Restore $s0
addi $sp, $sp, 4
jr $ra Return

Chapter 2 — Instructions: Language of the Computer — 58

Non-Leaf Procedures
 Procedures that call other procedures
 For nested call, caller needs to save on the
stack:
 Its return address
 Any arguments and temporaries needed after
the call
 Restore from the stack after the call

Chapter 2 — Instructions: Language of the Computer — 59

Non-Leaf Procedure Example
 C code:
int fact (int n)
{
if (n < 1) return 1;
else return n * fact(n - 1);
}
 Argument n in $a0

 Result in $v0

Chapter 2 — Instructions: Language of the Computer — 60

 int fact (int n)
{
if (n < 1) return 1;
else return n * fact(n -
1);
 MIPS code: }
fact:
addi $sp, $sp, -8 # adjust stack for 2 items
sw $ra, 4($sp) # save return address
sw $a0, 0($sp) # save argument
slti $t0, $a0, 1 # test for n < 1
beq $t0, $zero, L1
addi $v0, $zero, 1 # if so, result is 1
addi $sp, $sp, 8 # pop 2 items from stack
jr $ra # and return
L1: addi $a0, $a0, -1 # else decrement n
jal fact # recursive call
lw $a0, 0($sp) # restore original n
lw $ra, 4($sp) # and return address
addi $sp, $sp, 8 # pop 2 items from stack
mul $v0, $a0, $v0 # multiply to get result
jr $ra # and return

Chapter 2 — Instructions: Language of the Computer — 61

Stack Manipulation

PUSH POP
addi $sp, $sp, -12 lw $s0, 0($sp)
sw $t1, 8($sp) lw $t0, 4($sp)
sw $t0, 4($sp) lw $t1, 8($sp)
sw $s0, 0($sp) addi $sp, $sp, 12
Local Data on the Stack

 Local data allocated by callee


e.g., C automatic variables
 Procedure frame (activation record)

Used by some compilers to manage stack storage

Chapter 2 — Instructions: Language of the Computer — 63

Memory Layout
 Text: program code
 Static data: global
variables
 e.g., static variables in C,
constant arrays and strings
 $gp initialized to address
allowing ±offsets into this
segment
 Dynamic data: heap
 E.g., malloc in C, new in
Java
 Stack: automatic storage

Chapter 2 — Instructions: Language of the Computer — 64

 §2.9 Communicating with People
Character Data
 Byte-encoded character sets
 ASCII: 128 characters

95 graphic, 33 control
 Latin-1: 256 characters

ASCII, +96 more graphic characters
 Unicode: 32-bit character set
 Used in Java, C++ wide characters, …
 Most of the world’s alphabets, plus symbols
 UTF-8, UTF-16: variable-length encodings

Chapter 2 — Instructions: Language of the Computer — 65

Byte/Halfword Operations
 Could use bitwise operations
 MIPS byte/halfword load/store
 String processing is a common case
lb rt, offset(rs) lh rt, offset(rs)
 Sign extend to 32 bits in rt
lbu rt, offset(rs) lhu rt, offset(rs)
 Zero extend to 32 bits in rt
sb rt, offset(rs) sh rt, offset(rs)
 Store just rightmost byte/halfword

Chapter 2 — Instructions: Language of the Computer — 67

String Copy Example
 C code (naïve):
 Null-terminated string
void strcpy (char x[], char y[])
{ int i;
i = 0;
while ((x[i]=y[i])!='\0')
i += 1;
}
 Addresses of x, y in $a0, $a1

 i in $s0

Chapter 2 — Instructions: Language of the Computer — 68

String Copy Example
 MIPS code:
strcpy:
addi $sp, $sp, -4 # adjust stack for 1 item
sw $s0, 0($sp) # save $s0
add $s0, $zero, $zero # i = 0
L1: add $t1, $s0, $a1 # addr of y[i] in $t1
lbu $t2, 0($t1) # $t2 = y[i]
add $t3, $s0, $a0 # addr of x[i] in $t3
sb $t2, 0($t3) # x[i] = y[i]
beq $t2, $zero, L2 # exit loop if y[i] == 0
addi $s0, $s0, 1 # i = i + 1
j L1 # next iteration of loop
L2: lw $s0, 0($sp) # restore saved $s0
addi $sp, $sp, 4 # pop 1 item from stack
jr $ra # and return

Chapter 2 — Instructions: Language of the Computer — 69

 §2.10 MIPS Addressing for 32-Bit Immediates and Addresses
32-bit Constants
 Most constants are small
 16-bit immediate is sufficient
 For the occasional 32-bit constant
lui rt, constant
 Copies 16-bit constant to left 16 bits of rt
 Clears right 16 bits of rt to 0

lui $s0, 61 0000 0000 0111 1101 0000 0000 0000 0000

ori $s0, $s0, 2304 0000 0000 0111 1101 0000 1001 0000 0000

Chapter 2 — Instructions: Language of the Computer — 70

How about larger constants?
 We'd like to be able to load a 32 bit constant into a register
 Must use two instructions, new "load upper immediate" instruction

lui $t0, 1010101010101010

filled with zeros

1010101010101010 0000000000000000

 Then must get the lower order bits right, i.e.,

ori $t0, $t0, 1010101010101010

1010101010101010 0000000000000000

0000000000000000 1010101010101010
ori

1010101010101010 1010101010101010
Branch Addressing
 Branch instructions specify
 Opcode, two registers, target address
 Most branch targets are near branch
 Forward or backward

op rs rt constant or address
6 bits 5 bits 5 bits 16 bits

 PC-relative addressing
 Target address = PC + offset × 4
 PC already incremented by 4 by this time
Chapter 2 — Instructions: Language of the Computer — 72
Jump Addressing
 Jump (j and jal) targets could be
anywhere in text segment
 Encode full address in instruction

op address
6 bits 26 bits

 (Pseudo)Direct jump addressing

 Target address = PC31…28 : (address × 4)

Chapter 2 — Instructions: Language of the Computer — 73

Target Addressing Example
 Loop code from earlier example
 Assume Loop at location 80000

Loop: sll $t1, $s3, 2 80000 0 0 19 9 4 0

add $t1, $t1, $s6 80004 0 9 22 9 0 32
lw $t0, 0($t1) 80008 35 9 8 0
bne $t0, $s5, Exit 80012 5 8 21 2
addi $s3, $s3, 1 80016 8 19 19 1
j Loop 80020 2 20000
Exit: … 80024

Chapter 2 — Instructions: Language of the Computer — 74

Branching Far Away
 If branch target is too far to encode with
16-bit offset, assembler rewrites the code
 Example
beq $s0,$s1, L1
↓
bne $s0,$s1, L2
j L1
L2: …

Chapter 2 — Instructions: Language of the Computer — 75

Branching Far Away
 Branch instructions:
beq $t4,$t5,Label Next instruction is at Label if $t4=$t5
 most branches are local (principle of locality)
 address boundaries of 256KB (16+2 bits)
 PC-relative addressing (in fact, relative to PC+4)
 Jump instruction preserves 4 higher order bits of PC
bne $t4,$t5,L2
j Label
L2:
 address boundaries of 256MB (26+2 bits)
 Pseudodirect addressing (will replace the lower 26 bits of PC)
 Could specify a register (like lw and sw) and add it to address
bne $t4,$t5,L2
jr $ra
L2:
 Can use Instruction Address Register (PC = program counter)
 address boundaries of 4GB (32 bits)
System Calls
$v0 $a0-3,$f12 $v0, $f0
Example 1 (for SPIM)
#subsequent items are stored in the data segment
.data
#store the string in memory and null-terminate it
str: .asciiz "\nthe answer = "
#declare label main is global and can be referenced from other files
.globl main
#subsequent items are stored in the text segment
.text
main: li $v0, 4
la $a0, str
syscall # print the string
li $v0, 1
li $a0, 5
syscall # print the value
li $v0, 10
syscall
 Example 2
 Please write an MIPS assembly program to sum up a sequence of
numbers. The sequence of numbers should be provided by user through
keyboard. The end of the sequence is indicated by a zero.

main: li $a0, 0
loop: li $v0, 5
syscall
add $a0, $a0, $v0
bne $v0, $zero, loop
li $v0, 1
syscall
li $v0, 10
syscall
 MIPS assembly language
Category Instruction Example Meaning Comments
add add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants
load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register
store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory
Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register
store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory
load upper immediate lui $s1, 100 $s1 = 100 * 2
16 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to Equal test; PC-relative branch
PC + 4 + 100

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to Not equal test; PC-relative
PC + 4 + 100
Conditional
branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; Compare less than; for beq, bne
else $s1 = 0

set less than slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; Compare less than constant
immediate else $s1 = 0

jump j 2500 go to 10000 Jump to target address

Uncondi- jump register jr $ra go to $ra For switch, procedure return
tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call
Addressing Mode Summary

Chapter 2 — Instructions: Language of the Computer — 81

1. Immediate addressing
op rs rt Immediate

2. Register addressing
op rs rt rd ... funct Registers
Register

3. Base addressing
op rs rt Address Memor y

Register + Byte Halfword Word

4. PC-relative addressing 16 bits

op rs rt Address Memor y

PC + Word

5. Pseudodirect addressing 26 bits Memor y

op Address

PC Word
 §2.11 Parallelism and Instructions: Synchronization
Synchronization
 Two processors sharing an area of memory
 P1 writes, then P2 reads
 Data race if P1 and P2 don’t synchronize

Result depends of order of accesses
 Hardware support required
 Atomic read/write memory operation
 No other access to the location allowed between the
read and write
 Could be a single instruction
 E.g., atomic swap of register ↔ memory
 Or an atomic pair of instructions

Chapter 2 — Instructions: Language of the Computer — 83

Synchronization in MIPS
 Load linked: ll rt, offset(rs)
 Store conditional: sc rt, offset(rs)
 Succeeds if location not changed since the ll

Returns 1 in rt
 Fails if location is changed

Returns 0 in rt
 Example: atomic swap (to test/set lock variable)
try: add $t0,$zero,$s4 ;copy exchange value
ll $t1,0($s1) ;load linked
sc $t0,0($s1) ;store conditional
beq $t0,$zero,try ;branch store fails
add $s4,$zero,$t1 ;put load value in $s4

Chapter 2 — Instructions: Language of the Computer — 84

 §2.12 Translating and Starting a Program
Translation and Startup

Many compilers produce

object modules directly

Static linking

Chapter 2 — Instructions: Language of the Computer — 85

Assembler Pseudoinstructions
 Most assembler instructions represent
machine instructions one-to-one
 Pseudoinstructions: figments of the
assembler’s imagination
move $t0, $t1 → add $t0, $zero, $t1
blt $t0, $t1, L → slt $at, $t0, $t1
bne $at, $zero, L
 $at (register 1): assembler temporary

Chapter 2 — Instructions: Language of the Computer — 86

Producing an Object Module (*.OBJ)
 Assembler (or compiler) translates program into
machine instructions
 Provides information for building a complete
program from the pieces
 Header: described contents of object module
 Text segment: translated instructions
 Static data segment: data allocated for the life of the
program
 Relocation info: for contents that depend on absolute
location of loaded program
 Symbol table: global definitions and external refs
 Debug info: for associating with source code

Chapter 2 — Instructions: Language of the Computer — 87

Linking Object Modules
 Produces an executable image
1. Merges segments
2. Resolve labels (determine their
addresses)
3. Patch location-dependent and external
refs
 Could leave location dependencies for
fixing by a relocating loader
 But with virtual memory, no need to do this
 Program can be loaded into absolute location
in virtual memory space
Chapter 2 — Instructions: Language of the Computer — 88
Loading a Program (*.EXE)
 Load from image file on disk into memory
1. Read header to determine segment
sizes
2. Create virtual address space
3. Copy text and initialized data into
memory

Or set page table entries so they can be faulted in
4. Set up arguments on stack
5. Initialize registers (including $sp, $fp,
$gp)
6. Jump to startup routine

Copies arguments to2 —$a0,
Chapter … and
Instructions: callsofmain
Language the Computer — 89
 §2.13 A C Sort Example to Put It All Together
C Sort Example
 Illustrates use of assembly instructions
for a C bubble sort function
 Swap procedure (leaf)
void swap(int v[], int k)
{
int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
 v in $a0, k in $a1, temp in $t0

Chapter 2 — Instructions: Language of the Computer — 90

The Procedure Swap
swap: sll $t1, $a1, 2 # $t1 = k * 4
add $t1, $a0, $t1 # $t1 = v+(k*4)
# (address of v[k])
lw $t0, 0($t1) # $t0 (temp) = v[k]
lw $t2, 4($t1) # $t2 = v[k+1]
sw $t2, 0($t1) # v[k] = $t2 (v[k+1])
sw $t0, 4($t1) # v[k+1] = $t0 (temp)
jr $ra # return to calling routine

Chapter 2 — Instructions: Language of the Computer — 91

 The Sort Procedure in C
Non-leaf (calls swap)  Non-leaf (calls swap)
void sort (int v[], int n) void sort (int v[], int n)
{ {
int i, j; int i, j;
for (i = 0; i < n; i += 1){ for (i = 0; i < n-1; i += 1){
for (j = i–1; for (j = 0;
j >= 0 && v[j] > v[j+1]; j < n-i-1 && v[j] > v[j+1];
j -= 1){ j += 1){
swap(v,j); swap(v,j);
} }
} }
} }

v in $a0, k in $a1, i in $s0, j in $s1 
v in $a0, k in $a1, i in $s0, j in $s1

Chapter 2 — Instructions: Language of the Computer — 92

The Procedure Body
move $s2, $a0 # save $a0 into $s2 Move
move $s3, $a1 # save $a1 into $s3 params
move $s0, $zero # i = 0
Outer loop
for1tst: slt $t0, $s0, $s3 # $t0 = 0 if $s0 ≥ $s3 (i ≥ n)
beq $t0, $zero, exit1 # go to exit1 if $s0 ≥ $s3 (i ≥ n)
addi $s1, $s0, –1 # j = i – 1
for2tst: slti $t0, $s1, 0 # $t0 = 1 if $s1 < 0 (j < 0)
bne $t0, $zero, exit2 # go to exit2 if $s1 < 0 (j < 0)
sll $t1, $s1, 2 # $t1 = j * 4
Inner loop
add $t2, $s2, $t1 # $t2 = v + (j * 4)
lw $t3, 0($t2) # $t3 = v[j]
lw $t4, 4($t2) # $t4 = v[j + 1]
slt $t0, $t4, $t3 # $t0 = 0 if $t4 ≥ $t3
beq $t0, $zero, exit2 # go to exit2 if $t4 ≥ $t3
move $a0, $s2 # 1st param of swap is v (old $a0)
Pass
move $a1, $s1 # 2nd param of swap is j params
jal swap # call swap procedure & call
addi $s1, $s1, –1 # j –= 1
j for2tst # jump to test of inner loop Inner loop
exit2: addi $s0, $s0, 1 # i += 1
j for1tst # jump to test of outer loop Outer loop

Chapter 2 — Instructions: Language of the Computer — 93

The Full Procedure
sort: addi $sp,$sp, –20 # make room on stack for 5 registers
sw $ra, 16($sp) # save $ra on stack
sw $s3, 12($sp) # save $s3 on stack
sw $s2, 8($sp) # save $s2 on stack
sw $s1, 4($sp) # save $s1 on stack
sw $s0, 0($sp) # save $s0 on stack
… # procedure body
…
exit1: lw $s0, 0($sp) # restore $s0 from stack
lw $s1, 4($sp) # restore $s1 from stack
lw $s2, 8($sp) # restore $s2 from stack
lw $s3,12($sp) # restore $s3 from stack
lw $ra,16($sp) # restore $ra from stack
addi $sp,$sp, 20 # restore stack pointer
jr $ra # return to calling routine

Chapter 2 — Instructions: Language of the Computer — 94

 Effect of Compiler Optimization
Compiled with gcc for Pentium 4 under Linux

3 Relative Performance 140000 Instruction count

2.5 120000
100000
2
80000
1.5
60000
1
40000
0.5 20000
0 0
none O1 O2 O3 none O1 O2 O3

180000 Clock Cycles 2 CPI

160000
140000 1.5
120000
100000
1
80000
60000
40000 0.5
20000
0 0
none O1 O2 O3 none O1 O2 O3

Chapter 2 — Instructions: Language of the Computer — 95

Effect of Language and Algorithm
3 Bubblesort Relative Performance
2.5

1.5

0.5

0
C/ none C/ O1 C/ O2 C/ O3 J ava/ int J ava/ J IT

2.5 Quicksort Relative Performance

2

1.5

0.5

0
C/ none C/ O1 C/ O2 C/ O3 J ava/ int J ava/ J IT

3000 Quicksort vs. Bubblesort Speedup

2500

2000

1500

1000

500

0
C/ none C/ O1 C/ O2 C/ O3 J ava/ int J ava/ J IT

Chapter 2 — Instructions: Language of the Computer — 96

Lessons Learnt
 Instruction count and CPI are not good
performance indicators in isolation
 Compiler optimizations are sensitive to the
algorithm
 Java/JIT compiled code is significantly
faster than JVM interpreted
 Comparable to optimized C in some cases
 Nothing can fix a dumb algorithm!

Chapter 2 — Instructions: Language of the Computer — 97

 §2.14 Arrays versus Pointers
Arrays vs. Pointers
 Array indexing involves
 Multiplying index by element size
 Adding to array base address
 Pointers correspond directly to memory
addresses
 Can avoid indexing complexity

Chapter 2 — Instructions: Language of the Computer — 98

 Example: Clearing an Array
clear1(int array[], int size) { clear2(int *array, int size) {
int i; int *p;
for (i = 0; i < size; i += 1) for (p = &array[0]; p < &array[size];
array[i] = 0; p = p + 1)
} *p = 0;
}

move $t0,$zero # i = 0 move $t0,$a0 # p = & array[0]

loop1: sll $t1,$t0,2 # $t1 = i * 4 sll $t1,$a1,2 # $t1 = size * 4
add $t2,$a0,$t1 # $t2 = add $t2,$a0,$t1 # $t2 =
# &array[i] # &array[size]
sw $zero, 0($t2) # array[i] = 0 loop2: sw $zero,0($t0) # Memory[p] = 0
addi $t0,$t0,1 # i = i + 1 addi $t0,$t0,4 # p = p + 4
slt $t3,$t0,$a1 # $t3 = slt $t3,$t0,$t2 # $t3 =
# (i < size) #(p<&array[size])
bne $t3,$zero,loop1 # if (…) bne $t3,$zero,loop2 # if (…)
# goto loop1 # goto loop2

Chapter 2 — Instructions: Language of the Computer — 99

Comparison of Array vs. Ptr
 Multiply “strength reduced” to shift
 Array version requires shift to be inside
loop
 Part of index calculation for incremented i
 c.f. incrementing pointer
 Compiler can achieve same effect as
manual use of pointers
 Induction variable elimination
 Better to make program clearer and safer

Chapter 2 — Instructions: Language of the Computer — 100

 §2.16 Real Stuff: ARM Instructions
ARM & MIPS Similarities
 ARM: the most popular embedded core
 Similar basic set of instructions to MIPS
ARM MIPS
Date announced 1985 1985
Instruction size 32 bits 32 bits
Address space 32-bit flat 32-bit flat
Data alignment Aligned Aligned
Data addressing modes 9 3
Registers 15 × 32-bit 31 × 32-bit
Input/output Memory Memory
mapped mapped

Chapter 2 — Instructions: Language of the Computer — 101

Compare and Branch in ARM
 Uses condition codes for result of an
arithmetic/logical instruction
 Negative, zero, carry, overflow
 Compare instructions to set condition codes
without keeping the result
 Each instruction can be conditional
 Top 4 bits of instruction word: condition value
 Can avoid branches over single instructions

Chapter 2 — Instructions: Language of the Computer — 102

Instruction Encoding

Chapter 2 — Instructions: Language of the Computer — 103

 §2.17 Real Stuff: x86 Instructions
The Intel x86 ISA
 Evolution with backward compatibility
 8080 (1974): 8-bit microprocessor

Accumulator, plus 3 index-register pairs
 8086 (1978): 16-bit extension to 8080

Complex instruction set (CISC)
 8087 (1980): floating-point coprocessor

Adds FP instructions and register stack
 80286 (1982): 24-bit addresses, MMU

Segmented memory mapping and protection
 80386 (1985): 32-bit extension (now IA-32)

Additional addressing modes and operations

Paged memory mapping as well as segments

Chapter 2 — Instructions: Language of the Computer — 104

The Intel x86 ISA
 Further evolution…

i486 (1989): pipelined, on-chip caches and FPU

Compatible competitors: AMD, Cyrix, …

Pentium (1993): superscalar, 64-bit datapath

Later versions added MMX (Multi-Media eXtension)
instructions

The infamous FDIV bug

Pentium Pro (1995), Pentium II (1997)

New microarchitecture (see Colwell, The Pentium Chronicles)

Pentium III (1999)

Added SSE (Streaming SIMD Extensions) and associated
registers

Pentium 4 (2001)

New microarchitecture

Added SSE2 instructions

Chapter 2 — Instructions: Language of the Computer — 105

Basic x86 Registers

Chapter 2 — Instructions: Language of the Computer — 106

Basic x86 Addressing Modes
 Two operands per instruction
Source/dest operand Second source operand
Register Register
Register Immediate
Register Memory
Memory Register
Memory Immediate

 Memory addressing modes

 Address in register
 Address = Rbase + displacement
 Address = Rbase + 2scale × Rindex (scale = 0, 1, 2, or 3)
 Address = Rbase + 2scale × Rindex + displacement
Chapter 2 — Instructions: Language of the Computer — 107
x86 Instruction Encoding
 Variable length
encoding
 Postfix bytes specify
addressing mode
 Prefix bytes modify
operation

Operand length,
repetition, locking, …

Chapter 2 — Instructions: Language of the Computer — 108

Implementing IA-32 (Intel Architecture)
 Complex instruction set makes
implementation difficult
 Hardware translates instructions to simpler
microoperations

Simple instructions: 1–1

Complex instructions: 1–many
 Microengine similar to RISC
 Market share makes this economically viable
 Comparable performance to RISC
 Compilers avoid complex instructions

Chapter 2 — Instructions: Language of the Computer — 109

MIPS (RISC) Design Principles
 Simplicity favors regularity
 fixed size instructions
 small number of instruction formats
 opcode always the first 6 bits
 Smaller is faster
 limited instruction set
 limited number of registers in register file
 limited number of addressing modes
 Make the common case fast
 arithmetic operands from the register file (load-store machine)
 allow instructions to contain immediate operands
 Good design demands good compromises
 three instruction formats
 §2.19 Fallacies and Pitfalls
Fallacies
 Powerful instruction  higher performance
 Fewer instructions required
 But complex instructions are hard to implement

May slow down all instructions, including simple ones
 Compilers are good at making fast code from simple
instructions
 Assembly code  higher performance
 But modern compilers are better at dealing with
modern processors
 More lines of code  more errors and less productivity

Chapter 2 — Instructions: Language of the Computer — 111

Fallacies
 Backward compatibility  instruction set
doesn’t change
 But they do accrete more instructions

x86 instruction set

Chapter 2 — Instructions: Language of the Computer — 112

Pitfalls
 Sequential words are not at sequential
addresses
 Increment by 4, not by 1!

 Keeping a pointer to an automatic variable

after procedure returns
 e.g., passing pointer back via an argument
 Pointer becomes invalid when stack popped

Chapter 2 — Instructions: Language of the Computer — 113

 §2.20 Concluding Remarks
Concluding Remarks
 Design principles
1. Simplicity favors regularity
2. Smaller is faster
3. Make the common case fast
4. Good design demands good
compromises
 Layers of software/hardware
 Compiler, Assembler, hardware
 MIPS: typical of RISC ISAs
 x86: typical of CISC ISAs

Chapter 2 — Instructions: Language of the Computer — 114

 Concluding Remarks
 Measure MIPS instruction executions in
benchmark programs
 Consider making the common case fast
 Consider compromises
Instruction class MIPS examples SPEC2006 Int SPEC2006 FP
Arithmetic add, sub, addi 16% 48%
Data transfer lw, sw, lb, lbu, 35% 36%
lh, lhu, sb, lui
Logical and, or, nor, andi, 12% 4%
ori, sll, srl
Cond. Branch beq, bne, slt, 34% 8%
slti, sltiu
Jump j, jr, jal 2% 0%

Chapter 2 — Instructions: Language of the Computer — 115