ECE5307 – VLSI DESIGN
Introduction
2
Integrated circuits (IC): Many transistors on one chip
Very Large Scale Integration (VLSI)
Complementary Metal Oxide Semiconductor (CMOS)
The advantages of CMOS are Fast, cheap, low power transistors
In this course, you are going to learn
How to build your own simple CMOS chip
About CMOS transistors
How to build logic gates from transistors
Transistor layout and fabrication
VLSI DESIGN / Design
approaches
VLSI Design is about designing systems on a chip
The designs are complex
We need to use structured design techniques and
sophisticated design tools to manage the
complexity of the design
We also accept the fact that any technology we
learn the details of will be out of date soon
Y Chart
5
• The design process, at various levels, is usually
evolutionary in nature.
• It starts with a given set of requirements.
Initial design is developed and tested
against the requirements.
• When requirements are not met, the design
has to be improved. If such improvement is
either not possible or too costly, then a revision
of requirements and an impact analysis must
be considered.
• The Y-chart (first introduced by D. Gajski)
illustrates a design flow for most logic chips,
using design activities on three different axes
(domains) which resemble the letter "Y."
Y CHART
6
Y Chart
7
• The Y-chart consists of three domains of
representation, namely (i) behavioral
domain, (ii) structural domain, and (iii)
geometrical layout domain.
• The design flow starts from the algorithm that
describes the behavior of the target chip.
The corresponding architecture of the processor
is first defined.
• It is mapped onto the chip surface by floor
planning. The next design evolution in the
behavioral domain defines finite state
machines (FSMs) which are structurally
implemented with functional modules such as
registers and arithmetic logic units (ALUs).
Y Chart
8
• These modules are then geometrically placed
onto the chip surface using CAD tools for
automatic module placement followed by
routing, with a goal of minimizing the
interconnects area and signal delays.
• The third evolution starts with a behavioral
module description.
• Individual modules are then implemented with
leaf cells. At this stage the chip is described in
terms of logic gates (leaf cells), which can be
placed and interconnected by using a cell
placement and routing program.
Y Chart
9
• The last evolution involves a detailed Boolean
description of leaf cells followed by a transistor
level implementation of leaf cells and mask
generation.
• In the standard cell based design style, leaf cells
are pre-designed (at the transistor level) and
stored in a library for logic implementation,
effectively eliminating the need for the
transistor level design.
SEMI AND FULL CUSTOM
10
SEMI AND FULL CUSTOM
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• Two different VLSI design styles are
compared for their relative merits in the design
of the same product.
• Using the full-custom design style (where
the geometry and the placement of every
transistor can be optimized individually)
requires a longer time until design maturity
can be reached, yet the inherent flexibility of
adjusting almost every aspect of circuit design
allows far more opportunity for circuit
performance improvement during the design
cycle.
• The final product typically has a high level of
performance (e.g. high processing speed,
low power dissipation) and the silicon area is
SEMI AND FULL CUSTOM
12
• But this comes at a larger cost in terms of
design time.
• In contrast, using a semi-custom design style
(such as standard-cell based design or FPGA)
will allow a shorter design time until design
maturity can be achieved.
• In the early design phase, the circuit
performance can be even higher than that of a
full-custom design, since some of the
components used in semi-custom design are
already optimized.
• But the semi-custom design style offers
less opportunity for performance
improvement over the long run, and the overall
performance of the final product will inevitably
FABRICATION PROCESS
Oxidation:
The process of oxidation consists of growing a
thin film of silicon dioxide on the surface of the
silicon wafer.
Diffusion:
This process consists of the introduction of a few
tenths to several micrometers of impurities by the
solid-state diffusion of dopants into selected
regions of a wafer to form junctions.
Ion Implantation:
This is a process of introducing dopants into
selected areas of the surface of the wafer by
bombarding the surface with high-energy ions of
the particular dopant.
Photolithography:
In this process, the image on the reticle is transferred to the
surface of the wafer.
Epitaxy:
Epitaxy is the process of the controlled growth of a
crystalline doped layer of
silicon on a single crystal substrate.
Metallization and interconnections:
After all semiconductor fabrication steps of a device or of
an integrated circuit are
completed, it becomes necessary to provide metallic
interconnections for the
integrated circuit and for external connections to both the
device and to the IC
SILICON WAFERS
THE PURITY OF SILICON
The starting form of silicon, which
manufacturers of devices and integrated circuits
use, is a circular slice known as a wafer.
These wafer diameters vary from 10 - 20 cms
with maximum up to 30 cms.
Silicon is found in abundance in nature as an
oxide in sand and quartz.
Silicon must be in Crystalline form, Very pure,
Free of defects, and Uncontaminated.
CMOS Fabrication
23
CMOS transistors are fabricated on silicon
wafer
Lithography process similar to printing press
On each step, different materials are
deposited or etched
Easiest to understand by viewing both top
and cross-section of wafer in a simplified
manufacturing process
0: Introduction
Detailed Mask Views
24
n well
Six masks
n-well
Polysilicon
Polysilicon
n+ diffusion
n+ Diffusion
p+ diffusion
Contact p+ Diffusion
Metal Contact
Metal
0: Introduction
Fabrication
25
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields
Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.
0: Introduction
Fabrication Steps
26
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO 2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
0: Introduction
Oxidation
27
Grow SiO2 on top of Si wafer
900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
0: Introduction
28 Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
Photoresist
SiO2
p substrate
0: Introduction
Lithography
29
Expose photoresist through n-well mask
Strip off exposed photoresist
Photoresist
SiO2
p substrate
0: Introduction
30 Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been
exposed
Photoresist
SiO2
p substrate
0: Introduction
31 Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesn’t melt in next step
SiO2
p substrate
0: Introduction
32 n-well
n-well is formed with diffusion or ion
implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well
0: Introduction
33 Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps
n well
p substrate
0: Introduction
34 Polysilicon
Deposit very thin layer of gate oxide
< 20 Å (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon
layer
Place wafer in furnace with Silane gas (SiH 4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
0: Introduction
35 Polysilicon Patterning
Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
0: Introduction
36 N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks
diffusion
Polysilicon is better than metal for self-
aligned gates because it doesn’t melt during
later processing
n+ Diffusion
n well
p substrate
0: Introduction
37 N-diffusion cont.
Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
0: Introduction
38 P-Diffusion
Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
0: Introduction
39 Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
0: Introduction
40 Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
0: Introduction
Stick Diagrams
41 Stick Diagrams
Objectives:
To know what is meant by stick diagram.
To understand the capabilities and limitations of stick
diagram.
To learn how to draw stick diagrams for a given MOS
circuit.
Outcome:
At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.
Stick Diagrams
42 Stick Diagrams
N+ N+
Stick Diagrams
43 Stick Diagrams
VDD
VDD
X
X
x x x
x Stick
Diagra X
m
Gnd Gnd
Stick Diagrams
44 Stick Diagrams
VDD
VDD
X
X
x x x
x X
Gnd Gnd
Stick Diagrams
45 Stick Diagrams
VLSI design aims to translate circuit concepts
onto silicon.
stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
Acts as an interface between symbolic circuit
and the actual layout.
Stick Diagrams
46 Stick Diagrams – Notations
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub
etc..
Stick Diagrams
47 Stick Diagrams – Some
Rule 1. rules
When two or more ‘sticks’ of the same type cross or touch each
other that represents electrical contact.
Stick Diagrams
48 Stick Diagrams – Some
Rule 2.
rules
When two or more ‘sticks’ of different type cross or touch each
other there is no electrical contact.
(If electrical contact is needed we have to show the
connection explicitly).
STICK DIAGRAM
STICK DIAGRAM
STICK DIAGRAM
STICK DIAGRAM
Stick Diagrams
53 Stick Diagrams – Some
Rule 3.
rules
When a poly crosses diffusion it represents a transistor.
Note: If a contact is shown then it is not a transistor.
Stick Diagrams
54 Stick Diagrams – Some
Rule 4.
rules
In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff. All pMOS must lie on one side of the line and all
nMOS will have to be on the other side.
Stick Diagrams
How to draw Stick Diagrams
55
Stick Diagrams
56 Stick Diagram
[Link], Faculty, Dept. of E&C Engineering, M.I.T Manipal
Stick Diagrams
57 Stick Diagram
Power
A Out
Ground
[Link], Faculty, Dept. of E&C Engineering, M.I.T Manipal