3.

1 Computer
Architecture
3.2 Input/output
Devices
3.3 Data Storage
3.4 Network Hardware
Hardware
 1. Stored program Concept
2. Buses and its types
3.1 3. Von Neuman Architecture
Computer 4. Registers and its types
Architecture 5. Fetch Execute Cycle FDE
6. Factors that improve CPU performance
  Integrated circuit
 responsibility of execution of all the instructions and
The Central data in an application

Processing  Consists of
1. CU
Unit CPU 2. ALU
3. Registers and buses
  2 types of data storage
Temporary storage (primary Memory)
Data Permanent storage (Secondary Memory)
Storage  Store data permanently will eliminate the chance of
data loss
(Store Program Concept)
 Temporary Primary
CPU Program
Memory Memory
Move
RAM
Store to
Program Secondary
Concept Memory

Move to
Register
s to
fetch
one by
 PPQ
 Describe the Store Program Concept when Applied to
Von Neuman Architecture

1. Program is stored in secondary storage device

2. Data and instruction are moved and stored to RAM
3. Data and instructions are moved to register to be executed
4. Instructions are fetched one by one
1. Stored Program Concept
 Programs and data are stored in the same memory.
 Instructions are fetched and executed sequentially, simplifying computer design.
2. Single Memory
 A single memory (RAM) is used to store both instructions (code) and data.
 Memory is addressable by location, and each address can hold a data or instruction word.
3. Central Processing Unit (CPU)
 The CPU is divided into:
 Control Unit (CU): Manages the execution of instructions by directing data flow between components.
 Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.

4. Registers
 Small, high-speed storage locations in the CPU used for temporary data storage during processing.
 Includes specific registers like the Program Counter (PC), which holds the address of the next instruction.
5. Sequential Processing
 Instructions are executed one at a time in a linear sequence, unless a jump or branch instruction is
encountered.
6. Input/Output Mechanism
 Facilitates data transfer between the computer and external devices like keyboards, screens, or storage
devices.
  Von Neuman Architecture
3.1 1. Store Program Concept
Computer 2. CPU Architecture

Architecture
 In the Von Neumann architecture, the number of
registers is not fixed and depends on the specific
implementation of the architecture. However, typical Von
Neumann systems include the following core registers:
 Program Counter (PC): Tracks the address of the next
instruction to execute.
 Accumulator (ACC): Stores intermediate results of
arithmetic and logic operations.
Registers  Current Instruction Register (CIR): Holds the current
instruction being executed.
 Memory Address Register (MAR): Stores the
memory address being accessed.
 Memory Data Register (MDR): Holds the data being
read from or written to memory.
 General-Purpose Registers: Optional and used to
store temporary data.
The Von Neumann architecture is a computer architecture model that forms the basis of most
modern computers. Its key components are:
1. Central Processing Unit (CPU):
 Control Unit (CU): Directs the flow of data and instructions, managing how operations are
executed.
 Arithmetic Logic Unit (ALU): Performs arithmetic and logical operations.
 Registers: Small, fast storage locations in the CPU, used for temporary data storage during
operations.
2. Memory:
 Stores both data and instructions in the same memory space.
 Key Feature: A single memory for instructions and data (referred to as the "stored-program
concept").

Components of
 Memory is divided into addressable locations, where each location can be accessed using its
unique address.
3. Input/Output (I/O) Devices: Von Neuman
 Input devices allow data to enter the system (e.g., keyboard, mouse).
 Output devices display or output data from the system (e.g., monitor, printer). Architecture
4. System Bus:
 Data Bus: Transfers data between the CPU, memory, and I/O devices.
 Address Bus: Carries the addresses of data/instructions being accessed.
 Control Bus: Sends control signals to manage operations across components. Data is always moved
with instruction
5. Clock:
 Synchronizes operations within the CPU and other components.
  A bus in computer architecture is a communication
system that transfers data between different
components of a computer, such as the CPU,
BUSES memory, and input/output (I/O) devices. It consists of
a set of parallel wires or lines that carry data,
addresses, and control signals
Data Bus
 Purpose: Transfers actual data between the CPU,
memory, and I/O devices.
 Characteristics:
 Bi-directional: Can carry data to and from the CPU and
other components.
2. Address Bus
 Purpose: Carries the memory address of the data
that the CPU needs to read or write.( between
memory and CPU)
 Characteristics:
 Uni-directional: The CPU sends addresses to the
memory or I/O devices.
3. Control Bus
 Purpose: Transmits control signals to coordinate
operations between components.
 Characteristics:
 Includes signals like read/write, interrupt requests, and
clock signals.
 Directs the flow of data and ensures proper operation of
the computer.
 Typically bi-directional but can be uni directional as
well.
 Example Signals:
 Read (RD): Instructs a component to read data from a
memory location or I/O device.
 Write (WR): Instructs a component to write data to a
memory location or I/O device.
Memory
IAS
(Immediate  Data and instructions waits before execution (RAM :
Access temporary memory)

Store)
  Registers are used to temporary store data and
instructions
during processing
Registers They are used to temporarily store data, instructions,
or addresses that the CPU is currently processing.
Registers are faster than primary memory (RAM) and
are crucial for efficient CPU operation.
  Calculate out calculations
 Carries out logical operation
Role of ALU  Holds temporary values during calculations in a
register called the accumulator
  Fetch - Extract
Fetch –  Decode - Translate
Decode –  Execute - run

Execute  In the end the instruction is finally decoded and is

then executed
PPQ
fetch
  The central processing unit ____________ the data and
instructions needed and stores them in
____________________to wait
 The ___________ holds the address of the next
instruction
 The next address is sent to ________
Past paper  The data from this address is sent to ________ . The
Question instruction is then decoded and ________
 . Any calculations that are carried out on data are
done by ________
 During calculations , the data is held in a register
temporarily held in a register called ________
  The central processing unit fetches the data and
instructions needed and stores them in Immediate
access store to wait
 The PC holds the address of the next instruction
 The next address is sent to MAR
Past paper  The data from this address is sent to MDR . The
Question instruction is then decoded and Executed . Any
calculations that are carried out on data are done by
ALU
 During calculations , the data is held in a register
temporarily held in a register called Accumulator
ACC