Chapter Two
Intel 8086 microprocessor
8086 FEATURES
• 16-bit Arithmetic Logic Unit
• 16-bit data bus (8085 has 8-bit data bus)
• 20-bit address bus = 2^20 = 1,048,576 = 1 meg
• Multiply and division operation is included
• Provides 14 16 bit registers
• It has introduced pipelining technology.
• Instruction queue feature is included
Architecture of 8086
Instruction Machine Codes
Instruction machine codes are binary numbers
For Example:
1000100011000011 MOV AL, BL
Register
MOV
mode
Machine code structure
Opcode Mode Operand1 Operand2
Some instructions do not have operands, or have only one operand
Opcode tells what operation is to be performed.
(EU control logic generates ALU control signals according to Opcode)
Mode indicates the type of a instruction: Register type, or Memory type
Operands tell what data should be used in the operation. Operands can
be addresses telling where to get data (or where to store results)
Cont.
8086 internal registers 16 bits (2 bytes each)
AX, BX, CX and DX are two
bytes wide and each byte can
be accessed separately
These
Theseregisters
registersare
areused
usedas
as
memory
memorypointers.
[Link]
Addressreg
reg
Flags 9
Segment registers are used
as base address for a segment
in the 1 M byte of memory
The 8086 Microprocessors: Registers
Organization
– Data registers
• Hold data for an operation to be performed
• There are 4 data registers (AX, BX, CX, DX)
– Address registers
• Hold the address of an instruction or data element
• Segment registers (CS, DS, ES, SS)
• Pointer registers (SP, BP, IP)
• Index registers (SI, DI)
– Status register
• Keeps the current status of the processor
– In total there are fourteen 16-bit registers in an 8086
Data Registers: AX, BX, CX, DX
• Instructions execute faster if the data is in a register
• AX, BX, CX, DX are the data registers
• Low and High bytes of the data registers can be accessed
separately
– AH, BH, CH, DH are the high bytes
– AL, BL, CL, and DL are the low bytes
• Data Registers are general purpose registers but they also
perform special functions
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data transfer
instructions.
Data Registers: AX, BX, CX, DX
• BX
– Base Register
– Also serves as an address register for addressing 8086
memory
– Used in array operations
• CX
– Count register
– Used as a loop counter………uses the contents of cx as a
counter
– Used in shift and rotate operations
• DX
– Data register
– Used in I/O, multiplication and division
Segment Registers - CS, DS, SS and ES
Are Address registers
• Store the memory addresses of instructions and data
• Memory Organization(why segmentation ?)
– Each byte in memory has a 20 bit address starting with 0 to 2 20-1 or 1 meg
of addressable memory
– Addresses are expressed as 5 hex digits from 00000 - FFFFF
– Problem: But 20 bit addresses are TOO BIG to fit in 16 bit registers!
• Solution: Memory Segment
– Block of 64K (65,536) consecutive memory bytes
– A segment number is a 16 bit number
– Segment numbers range from 0000 to FFFF
– Within a segment, a particular memory location is specified with
an offset
– An offset also ranges from 0000 to FFFF
Flag Register
•Conditional flags:
– They are set according to some results of arithmetic operation. You do not
need to alter the value yourself.
Carry flag
Overflow
Direction Parity flag
Interrupt enable Auxiliary flag
6 are status flags
Trap Zero
3 are control flag
•Control flags: Sign
– Used to control some operations of the MPU. These flags are to be set by you
in order to achieve some specific purposes.
Flag
Register
CF (carry):In case of addition this flag is set if there is a carry out of the MSB.
The carry flag also serves as a borrow flag for subtraction. In case of subtraction
it is set when borrow is needed.
OF (overflow) :This flag is set if result is out of range. For addition this flag is
set when there is a carry into the MSB and no carry out of the MSB or vice-
versa. For subtraction, it is set when the MSB needs a borrow and there is no
borrow from the MSB, or vice-versa
DF (direction) :Indicates left or right for moving or comparing string data.
IF (interrupt) Indicates whether external interrupts are being processed or
ignored.
PF (parity): Indicates the number of 1 bits that result from an operation. It is set
to 1 if result of byte operation or lower byte of the word operation contain an
even number of ones; otherwise it is zero.
Cont.
TF (trap):One way to debug a program is to run the program one
instruction at a time and see the contents of used registers and memory variables
after execution of every instruction. This process is called 'single stepping'
through a program. If set, a trap is executed after execution of each instruction.
SF (sign) Contains the resulting sign of an arithmetic operation (1=negative)
ZF (zero) Indicates when the result of arithmetic or a comparison is zero. (1=yes) The
zero flag sets if the result of operation in ALU is zero and flag resets if the result
is nonzero. The zero flag is also set if a certain register content becomes zero
following an increment or decrement operation of that register..
AF (auxiliary carry) :This flag is set if there is an overflow out of bit 3 i.e., carry
from lower nibble to higher nibble (D3 bit to D4 bit). This flag is used for BCD
operations and it is not available for the programmer 3-16
Segmented Memory
• Segmented memory addressing: absolute (linear) address is a
combination of a 16-bit segment value added to a 16-bit offset
F0000
E0000 8000:FFFF
D0000
linear addresses
C0000
B0000
one segment
A0000
90000
80000
70000
60000
8000:0250
50000
0250
40000
30000 8000:0000
20000
10000
seg ofs
00000
Intel
Memory Address Generation
• The BIU has a dedicated adder for determining physical
memory addresses
Offset Value (16 bits)
Segment Register (16 bits) 0000
Adder
Physical Address (20 Bits)
Intel
Example Address Calculation
• If the data segment starts at location 1000h
and a data reference contains the address
29h where is the actual data?
2 9
Offset: 0000000000101001
Segment: 0001000000000000 0000
Address: 0001000000000010 1001
THE CODE SEGMENT
4000H 0H
CS: 0400
H CS:IP = 400:56
4056H Logical Address
IP 0056H
Segment Register Memory
0400 0
Offset
+ 0056
Physical or 0FFFFFH
Absolute Address 04056H
The offset is the distance in bytes from the start of the segment.
The offset is given by the IP for the Code Segment.
Instructions are always fetched with using the CS register.
Fetching Instructions
Where to fetch the next instruction?
8088 Memory
CS 1234
IP 0012 12352 MOV AL, 0
12352
Update IP
— After an instruction is fetched, Register IP is updated as follows:
IP = IP + Length of the fetched
instruction
— For Example: the length of MOV AL, 0 is 2 bytes. After fetching
this instruction, the IP is updated to 0014
THE DATA SEGMENT
0H
05C00H
DS: 05C0
05C50H
EA 0050 DS:EA
Memory
05C0 0
Segment Register
Offset + 0050
Physical Address 05C50H 0FFFFFH
Data is usually fetched with respect to the DS register. The effective
address (EA) is the offset. The EA depends on the addressing mode.
Accessing Data Memory
• There is a number of methods to generate the memory address when accessing
data memory. These methods are referred to as Addressing Modes
• Examples:
— Direct addressing: MOV AL, [0300H]
DS 1 2 3 4 0 (assume DS=1234H)
0 3 0 0
Memory address 1 2 6 4 0
— Register indirect addressing: MOV AL, [SI]
DS 1 2 3 4 0 (assume DS=1234H)
0 3 1 0 (assume SI=0310H)
Memory address 1 2 6 5 0
THE STACK SEGMENT
0H
0A00 0A000H
SS:
0A100H
SP 0100 SS:SP
Segment Register
Memory
0A00 0
Offset
+ 0100
Physical Address
0A100H 0FFFFFH
The offset is given by the SP register.
The stack is always referenced with respect to the stack segment register.
Reserved Memory Locations
• Some memory locations are reserved for special purposes.
• Programs should not be loaded in these areas
FFFFF
Locations from FFFF0H to FFFFFH
Reset FFFF0
are used for system reset code instruction
area
Locations from 00000H to 003FFH
are used for the interrupt pointer table Interrupt
pointer
¾ It has 256 table entries
table
¾ Each table entry is 4 bytes
003FF
256 4 = 1024 = memory addressing space
From 00000H to 003FFH 00000
Exercise
#1) The value of Code Segment (CS) Register is 4042H and the value of different
offsets is as follows:
BX: 2025H , IP: 0580H , DI: 4247H Calculate the effective address of the memory
location pointed by the CS register.
#2) Calculate the effective address for the following register:
SS: 3864H, SP: 1735H, BP: 4826H
#3) The value of the DS register is 3032H. And the BX register contains a 16 bit
value which is equal to 3032H. 0008H is added to BX.
ADD BX, 0008H
The register AX contains some value which needs to be stored at a location as
follows:
MOV [BX], AX
Calculate the address at which the value of the AX will be stored.
#4) You are provided the following values:
DS: 3056H, IP: 1023H, BP: 2322H and SP: 3029H
Can you calculate the effective address of the memory location as per the DS
register?
8086 pin description
8086 pin configuration