Projects
Project 1: Dual Port Ram
DPRam
module dualport_ram #(parameter WIDTH = 8, DEPTH = 16, ADDRESS=4) ( input [WIDTH-1:0] d_in,
input r_en, w_en, rst, clk,
input [ADDRESS-1:0] r_addr,w_addr,
reg [WIDTH-1:0] memory [DEPTH-1:0]; output reg [WIDTH-1:0] d_out);
integer i;
always@(posedge clk)
begin
if(rst)
begin
for(i=0;i<DEPTH;i=i+1)
memory[i] <= 1'b0;
end
else
begin
if(w_en)
memory[w_addr] <= d_in;
if(r_en)
d_out <= memory[r_addr];
end
end
Example – 4 bit SISO
module siso ( input clr, clk, sin,
output sout);
reg [3:0] s; begin
always @(posedge clk, negedge clr) if(~clr)
begin s <= 0;
if(~clr) else
s <= 0; s[0] <= sin;
else s[1] <= s[0];
s <= {sin,s[3:1]}; s[2] <= s[1];
end s[3] <= s[2];
end
assign sout = s[0];
endmodule
Project 2 : 16 X 8 Synchronous FIFO
clk rd
rst 8 data_out
16 X 8
data_in 8 full
FIFO
wr empty
Here Depth = 16, and Data = 8
FIFO
module fifo_16_8 #(parameter WIDTH = 8, DEPTH = 16) (input clk, rst, r_en, w_en,
input [WIDTH-1:0] d_in,
output full, empty,
output reg [WIDTH-1:0] d_out);
integer k;
reg [4:0] r_addr,w_addr;
reg [WIDTH-1:0] memory [DEPTH-1:0];
always@(posedge clk) // resetting the memory to 0
begin
if(rst)
begin
for(k=0;k<DEPTH;k=k+1)
memory[k] <= 0;
end
else begin
if(w_en&&~full) // writing into the memory
memory[w_addr] <= d_in;
if(r_en&&~empty)
d_out <= memory[r_addr]; // reading from the memory
end
end
FIFO
always@(posedge clk) //generating read_Address when FIFO is not empty
begin
if(rst)
begin
r_addr <= 0;
end
else if(r_en && ~empty)
r_addr <= r_addr + 1'b1;
end
always@(posedge clk) // generating write_Address when FIFO is not full
begin
if(rst)
begin
w_addr <= 0;
end
else if(w_en && ~full)
w_addr <= w_addr + 1'b1;
end
assign empty = (r_addr==w_addr)?1'b1:1'b0;
assign full = (w_addr[3:0] == r_addr[3:0])&&( w_addr[4] !== r_addr[4])?1'b1:1'b0;
Example – Mux 2: 1
module mux2_1 (input a,b,sel, output y);
assign y = (~sel&a)|(sel&b);
endmodule
module mux4_1(input [3:0] a,
input [1:0] sel, output y);
wire [1:0] w;
mux2_1 M1 ( a[0], a[1], sel[1], w[1]);
mux2_1 M2 ( a[2], a[3], sel[1], w[0]);
mux2_1 M3 ( w[1], w[0], sel[0], y);
endmodule
Example 4:1 mux using Decoder & Tristate
module Decoder2_4 ( input s1, s0,
output a, b, c, d);
assign a = (~s1) & (~s0);
assign b = (~s1) & (s0);
assign c = (s1) & (~s0);
assign d = (s1) & (s0);
endmodule
module Tri_State (input a, w1,
output y);
bufif1 T1 ( y, a, w1);
endmodule
Example 4:1 mux using Decoder & Tristate
module Mux4_DecoderTri ( input s1, s0, a1, b1, c1, d1,
output wor y1);
wire w1, w2, w3, w4;
Decoder2_4 D1 (.s1(s1), .s0(s0), .a(w1), .b(w2), .c(w3), .d(w4));
Tri_State T1 ( .w1(w1), .a(a1), .y(y1));
Tri_State T2 ( .w1(w2), .a(b1), .y(y1));
Tri_State T3 ( .w1(w3), .a(c1), .y(y1));
Tri_State T4 ( .w1(w4), .a(d1), .y(y1));
endmodule
Example 4:1 mux using Decoder & Tristate
module Mux4_DecoderTri_tb ();
reg s1,s0; reg a,b,c,d;
wire y; integer i,j;
Mux4_DecoderTri DUT ( .s1(s1), .s0(s0), .a1(a), .b1(b), .c1(c), .d1(d), .y1(y));
initial
begin
{a,b,c,d,s1,s0} = 0;
end
end
#20 $finish;
end
initial
initial
begin
begin
for(i=0;i<4;i=i+1)
$monitor($time, " Values of input a=%b, b=%b,
begin
c=%b, d=%b, select s1=%b,
{s1,s0} = i;
s0=%b, output y=%b",
for(j=0;j<16;j=j+1)
a,b,c,d,s1,s0,y);
begin
end
{a,b,c,d} = j;
endmodule
#10;
end
Example – 4:1 mux using Task
module task_mux ( input [3:0] a,
input [1:0] sel,
output reg y);
task mux ( input [3:0] d, input [1:0] s, output reg out);
begin
case(s)
0 : out = d[0];
1 : out = d[1];
2 : out = d[2];
3 : out = d[3];
endcase
end
always@(*)
mux( a , sel, y);
endmodule
Example – 4:1 mux using Function
module func_mux ( input [3:0] a,
input [1:0] sel,
output reg y);
function mux ( input [3:0] d, input [1:0] s);
begin
case(s)
0 : mux = d[0];
1 : mux = d[1];
2 : mux = d[2];
3 : mux = d[3];
endcase
end
always@(*)
y = mux( a , sel);
endmodule
Example 2X4 Decoder
module decoder2_4 ( input [1:0] sel,
output reg [3:0] d);
always@(sel)
begin
case (sel)
2'b00 : d = { 1’b1, 3’b000 };
2'b01 : d = 4’b0100;
2'b10 : d = 2;
2'b11 : d = 4’h1;
endcase
end
endmodule
Example 4X2 priority encoder
module prencoder_casex ( input [3:0] sel,
output reg [1:0] y);
always@(*) begin
begin case(1’b1)
casex(sel) sel[3] : y = 3;
4'b1xxx : y = 2'b11; sel[2] : y = 2;
4'b01xx : y = 2'b10; sel[1] : y = 1;
4'b001x : y = 2'b01; sel[0] : y = 0;
4'b0001 : y = 2'b00; default : y = z;
default : y = 2'bzz; endcase
endcase end
end
endmodule
Example Counter - up - load(RTL)
module counter_up_load ( input [3:0] data,
input load, clk, rst,
output reg [3:0] count);
always@(posedge clk)
begin
if(rst)
count <= 0;
else if(load)
count <= data;
else
count <= count + 1'b1;
end
endmodule
Example Counter - up – load(TB)
module counter_up_load_tb (); task rst_dut (); begin
reg rst, clk, load; reg [3:0] data; @(negedge clk); rst = 1'b1;
wire [3:0] count; @(negedge clk); rst = 1'b0;
parameter CYCLE = 10; end endtask
counter_up_load DUT ( data, load, clk, rst, count); task inputs( input [3:0] data1); begin
initial data = data1;
begin delay;
clk = 1'b0; end endtask
forever #CYCLE clk = ~clk; task loading ( input load1); begin
end load = load1;
task initialize (); end endtask
begin initial begin
{load,rst,data} = 0; initialize;
end rst_dut;
endtask #(5*CYCLE) delay;
task delay(); inputs(10);
begin loading(0);
@(negedge clk); delay;
end $finish;
endtask end
Example counter 0 to 15(Non-Blocking)
module counter_4_blocking #(parameter N =4) ( input clk, rst,
output reg flag, output reg [N-1:0] count);
always @(posedge clk)
begin
if(rst)
begin
count <= 0; flag <= 0;
end
else
begin
count <= count + 1;
flag <= 0;
if(count == 15)
begin
count <= 0;
flag <= 1;
end
end
end
endmodule
Example counter 0 to 15(Blocking)
module counter_4_blocking #(parameter N =4) ( input clk, rst,
output reg flag, output reg [N-1:0] count);
always @(posedge clk)
begin
if(rst)
begin
count = 0; flag = 0;
end
else
begin
count = count + 1;
flag = 0;
if(count == 15)
begin
count = 0;
flag = 1;
end
end
end
endmodule