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Verilog Interview Questions and Examples

The document provides various examples of Verilog code, including a 5 to 32 decoder, simulation timescales for different tools, and examples of race conditions and pipelining of registers. It highlights the importance of non-blocking assignments to avoid race conditions and demonstrates the use of flip-flops in pipelining. Additionally, it includes examples of clock signal manipulation and task execution timing.

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Mr.K Sanath Kumar
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8 views10 pages

Verilog Interview Questions and Examples

The document provides various examples of Verilog code, including a 5 to 32 decoder, simulation timescales for different tools, and examples of race conditions and pipelining of registers. It highlights the importance of non-blocking assignments to avoid race conditions and demonstrates the use of flip-flops in pipelining. Additionally, it includes examples of clock signal manipulation and task execution timing.

Uploaded by

Mr.K Sanath Kumar
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd

Interview Questions

1
5 to 32 Decoder

module decoder5_32 ( input [4:0] sel, module decoder5_32 ( input [4:0] sel,
output reg [31:0] d); output reg [31:0] d);
always@(sel) always@(sel)
begin begin
case (sel) d = 32’hffff_ffff;
5'b00000 : d = 32’hffff_fffe; d[sel] = 1’b0;
5’b00001 : d = 32’hffff_fffd; end
5’b00010 : d = 32’hffff_fffc;
………………. module decoder5_32 ( input [4:0] sel,
……………… output [31:0] d);
endcase
end assign d = ~(1’b1 << (sel));
endmodule

2
Defaults Simulation Timescale

• Isim - 1ns/1ps

• Questa Sim - 1ns/1ns

• VCS – 1ns/1ns

3
RTL Code – loops back

0000_0001
0000_0010
0000_0001
0000_0100
0000_0001
0000_1000
0000_0001
0001_0000
0000_0001
0010_0000
0000_0001
0100_0000
0000_0001
1000_0000

4
Example

At what time a and b will executes.

module example;
reg a = 1;
reg b = 0;

task t1;
begin initial
forever begin
begin fork
#10 b <= a; t1;
#10 a <= b; join
end
end #5 a <= ~a;
endtask #10 b <= a;
end
endmodule
5
Example

module example;
reg clk;

initial
begin
#10 clk = 0;
end

always @(clk)
begin
#10 clk = ~clk;
end

endmodule

6
Example

module example;
reg a , clk;
always
#10 clk = ~ clk;

always @(clk)
begin
$display($time);
a = #15 clk;
end

initial begin
clk = 1’b1;
a = 0;
#200 $finish;
end
endmodule
7
Race Condition

• Read-Write Race: It occurs when same register is read in one block


and writes in another
• Example
always@(posedge clk)
a = 1;

always@(posedge clk)
b = a;

• Here you are seeing that in one always block, 1 is assigned to “a”
while simultaneously its value is assign to “b”. This type of race
condition can easily be solved by using non-blocking assignment

Note: Above example is only for blocking, if non-blocking then there is no racing
8
Race Condition

• Read-Write Race: It occurs when same register is read in one


block and writes in another
• Example
module rw_race (input clk);
integer count = 10;

always@(posedge clk)
begin
count = count + 1;
end

always@(posedge clk)
begin
$write(“count = %0d \n”, count);
end
endmodule
9
Pipelining of Registers

• Pipelining of registers is done by connecting flip-flops in series


• Each FF adds a delay on the path that connects input to
output

a_in a_in1 a_in2 a_out

dff dff dff always@(posedge clk)


begin
a_in1 <= a_in;
clk a_in2 <= a_in1;
a_out <= a_in2;
end

10

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