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CMOS Testing Techniques Overview

The document discusses testing methods for combinational and sequential circuits, emphasizing truth table testing and fault detection for combinational circuits, and state initialization and sequence testing for sequential circuits. It highlights techniques such as Automatic Test Pattern Generation (ATPG), scan-based testing, simulation-based testing, and Built-in Self-Test (BIST). Additionally, it details the D-algorithm for generating test patterns to detect stuck-at faults in digital circuits.

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30 views16 pages

CMOS Testing Techniques Overview

The document discusses testing methods for combinational and sequential circuits, emphasizing truth table testing and fault detection for combinational circuits, and state initialization and sequence testing for sequential circuits. It highlights techniques such as Automatic Test Pattern Generation (ATPG), scan-based testing, simulation-based testing, and Built-in Self-Test (BIST). Additionally, it details the D-algorithm for generating test patterns to detect stuck-at faults in digital circuits.

Uploaded by

gurjumunirathnam
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd

Testing of Combinational circuits

• Testing combinational circuits involves applying all possible input


combinations and verifying the outputs against a truth table, while
sequential circuits require testing for state transitions and memory element
functionality, often using scan-based or simulation-based methods.
• Truth Table Testing:
• Apply all possible input combinations to the circuit.
• Compare the observed outputs with the expected outputs as defined in the
truth table.
• This method ensures that the circuit functions correctly for every input
combination.
• Fault Detection Test Sets (FDTS):
• Identify a minimal set of test patterns that can detect all possible faults in
the circuit.
• This method focuses on efficiently detecting faults rather than
exhaustively testing all combinations.
• Automatic Test Pattern Generation (ATPG):
• Algorithms like D-algorithm, PODEM, and Boolean difference can be used
to automatically generate test patterns for combinational circuits.
• These algorithms aim to find test patterns that sensitize paths in the
circuit, allowing faults to propagate to the outputs.
Testing of sequential circuits
• State Initialization:
• Before applying test patterns, ensure that the memory elements (flip-
flops) are initialized to a known state.
• This is crucial for repeatable and predictable testing.
• Sequence of Test Patterns:
• Sequential circuits require applying a sequence of test patterns to test
state transitions and memory element functionality.
• These patterns should cover all possible states and transitions.
• Scan-Based Testing:
• Introduce scan chains to access and control the internal memory elements.
• This allows for easier testing of the combinational logic and memory elements
separately.
• Simulation-Based Testing:
• Simulate the circuit's behavior under various input sequences and fault
conditions.
• This method can be used to identify potential problems and generate test
patterns.
• Built-in Self-Test (BIST):
• Integrate test circuitry directly into the sequential circuit to enable self-testing.
• This reduces the need for external test equipment and simplifies the testing
process.
D-algorithm
• The D-algorithm, developed by Roth in 1966, is a method for
generating test patterns to detect stuck-at faults in digital circuits,
focusing on propagating a fault signal (represented by "D") to a
primary output.
• Here's a breakdown of the D-algorithm:
• 1. Stuck-at Faults:
• The D-algorithm addresses the common type of fault model, where a
signal line is "stuck" at either a logic 0 (stuck-at-0) or a logic 1 (stuck-
at-1).
• The goal is to find input patterns that can differentiate between the
fault-free and faulty behaviour of the circuit.

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