Module Title: Computer Systems

Topic: 7
Topic Title: Computer programs

© NCC Education Limited

 Computer Programs Topic 7 - 7.2

Scope and Coverage

This topic will cover:
• Programmer’s point of view
• Instruction-sets (RISC vs CISC ISA)
• Hardware registers
• Addressing modes
• Input and output
• Context switching
• Interrupts
 Computer Programs Topic 7 - 7.3

Learning Outcomes
By the end of this topic students will be able
to:
• Explain instruction sets and addressing modes.
• Explain hardware features designed to support
execution of computer programs.
• Explain instruction processing (fetch, decode,
execute cycle)
• Explain the interrupt mechanism.
 Computer Programs Topic 7 - 7.4

Computer systems - roadmap

So far, various configurations of computer
systems and computer systems hardware
Advanced topics components and operating systems are
Computer networks covered as a hierarchy of technology.
Embedded systems
Digital logic
We now build upon this knowledge and
Computer systems software drill into the specifics of what computer
Computer programs programs are made of.
Numbers and logic
So now, it’s time to look at the formats of
Operating systems 2
Computer systems hardware
instructions that make up computer
Computer systems
software such as instruction sets, CPU
registers, addressing modes, stacks and
subroutine calls and returns.
 Computer Programs Topic 7 - 7.5

What is an executable program

Text file Executable file

Program
source in HLL Executable
HLL, e.g. VB Compiler program code

Dim I, N As Integer
201A0130
For N = 0 To 100
001DE678
I=N+1 090012FF
Next N 00BC0130
 Computer Programs Topic 7 - 7.6

Loading program code in RAM

Executable file

Operating
Executable System
program code

201A0130
001DE678
090012FF
00BC0130 RAM
 Computer Programs Topic 7 - 7.7

Instruction set architecture (ISA)

A set of low-level binary codes interpreted by the CPU as
valid processing instructions. By definition, these are CPU
specific, i.e. each CPU has a unique set of instructions.

Typical instruction set categories are:

• Data movement instructions
• Arithmetic instructions
• Control transfer instructions
• Comparison instructions
 Computer Programs Topic 7 - 7.8

Generalised instruction formats

Arithmetic instructions
Op Code Operand 1 Operand 2

Data transfer instructions

Op Code Source Destination

Control transfer instructions

Op Code Destination
 Computer Programs Topic 7 - 7.9

Register set

A set of CPU resident very fast hardware memories used as

locations for temporary data (scratch-pads) and for supporting
specialised and specific CPU functions.

Register A (AX) 16/32/64-bit Hardware Register

Register B (BX) 16/32/64-bit Hardware Register

Status Register (SR) 8/16/32-bit HW Register

PC Register (PC) 16/32/64-bit Hardware Register

 Computer Programs Topic 7 - 7.10

Special registers

Status Register 8/16/32-bit HW register

OV: Arithmetic overflow flag

Holds 1-bit status N : Negative result flag
flags Z : Zero result flag

Random Access
Memory (RAM)
PC Register
Instruction
Instruction Address
 Computer Programs Topic 7 - 7.11

Instruction set revisited

Low-level CPU instructions are created as a series of
instruction "op codes" with associated "operand(s)" by the
programmer (using an assembler software) or by a compiler
after translating a program written in a high-level language
such as Java and VB.
MOV #10, AX CMP #0, AX CAL 86
CAL Test_Routine
MOV AX, BX CMP AX, BX
RET
ADD #3, AX JEQ 1056
Can you identify the
SUB AX, BX JLE End_Loop categories of these
instructions?
 Computer Programs Topic 7 - 7.12

Instruction set revisited- examples

Consider high-level statement: A = 3 + 6 where A is declared
as a variable of type integer. What code will this generate?
MOV #3, R01 ;R01 is temporary reg MOV #3, R01
MOV #6, R02 ;R02 is temporary reg ADD #6, R01
ADD R01, R02 ;Result is in R02 MOV R01, R03
MOV R02, R03 ;R03 represents var A

Now consider the high-level simple loop statement below

“while N < 10 N = N + 1 end”
L1: CMP #10, R01 ;R01 represents variable N
JGE L2 ;jump if greater than or equal to
ADD #1, R01 ;increment N by 1
JMP L1 ;jump unconditionally back to L1
L2: ;label L2 lies outside the loop
 Computer Programs Topic 7 - 7.13

Status register (SR) flags

A CPU’s status register is used to indicate the result of an
arithmetic instruction such as ADD, SUB, DIV and MUL.
Consider the following cases where the results will affect
the status register differently (assume register R01 = 5).
What will be the values of the N and the Z status bits of
the status register (SR) in each case?

ADD #3, R01 Status flags N = 0 and Z = 0

SUB #8, R01 Status flags N = 1 and Z = 0
SUB #5, R01 Status flags N = 0 and Z = 1
 Computer Programs Topic 7 - 7.14

Status register (SR) flags

The status register flags are used by the jump instructions in
order to decide whether they should jump or not. They do this
by examining the N and the Z flags.
The compare (CMP) instruction is actually a subtraction
instruction where 1st operand is subtracted from the 2nd.
CMP #3, R01 Jump to label L1 will take place because 5 – 3 =
JGT L1 2 (N=0, Z=0), i.e. a positive result.
CMP #8, R01 Jump to label L3 will take place because 5 – 8 =
JLT L3 -3 (N=1, Z=0), i.e. a negative result.
CMP #5, R01 Jump to label L2 will take place because 5 – 5 =
JEQ L2 0 (N=0, Z=1), i.e. a zero result.
 Computer Programs Topic 7 - 7.15

Addressing modes
The CPU instructions may include one or more operands. The
operand values may be part of the instruction, or they may be
in some memory location such as in register, in memory, etc.

For example, a jump instruction may have the address of the

location to jump to as part of the instruction either as a number
or as a register with the address of the location to jump to.

Two main modes of addressing are used:

• Direct addressing (literal, register direct, memory direct)
• Indirect addressing (register indirect, memory indirect)
 Computer Programs Topic 7 - 7.16

Addressing modes - example

Direct addressing: LDW –
load word RAM
JMP 0100
0100
Indirect addressing:

LDW #2 @AX
2 0400
0404
AX register
0400
0796
LDW loads 4-byte value to an
address location given in AX register
 Computer Programs Topic 7 - 7.17

Indirect addressing example

LDW #2, 400 LDW instruction stores 2 as a 4-byte
LDW #2, 404 value 100 times starting from address
400 and ending at address 796. This will
require 100 instructions. In this code, the
LDW #2, 796 address values are directly provided.

MOV #400, AX This code does the same thing as the

L1: LDW #2, @AX one above, but it requires only 6
ADD #4, AX instructions! This is because it uses
CMP #800, AX indirect addressing. This example shows
JEQ L2 the advantage of indirect addressing.
JMP L1
L2: So, how it works is left as an exercise!
 Computer Programs Topic 7 - 7.18

Input output instructions

Direct
RAM
OUT ‘H’ 10
port addr 10
port addr 11
IN 11 port addr 12

Memory mapped 0100 ‘H’

MOV ‘H' 0100 0101
0102
 Computer Programs Topic 7 - 7.19

Types of instruction architecture

There are two types of instruction set computers
Complex Instruction Set Computers (CISC)
• The instructions do complex operations created to suit high-level
language statements
• Complex instructions require many CPU clock cycles
• Take up less memory space
• Less instructions required in programs
Reduced Instruction Set Computers (RISC)
• Use simpler instructions
• Simpler instructions require fewer CPU clock cycles
• Take up larger memory space
• More instructions required in programs
 Computer Programs Topic 7 - 7.20

RISC features
Main RISC features:
• Large set of registers (32, 64, 128 or more)
• Uses registers for passing parameters to functions
• Uses registers to return values from functions
• Global variables stored in registers
• Low number of instructions (less than 100)
• Reduced number of addressing modes
• Fixed size instructions (64 / 128 bytes)
 Computer Programs Topic 7 - 7.21

CISC vs. RISC

Case against the CISC (opposite true for RISC):
• CISC require compilers to do more complex work, hence
compilers tend to be more complicated and slower
• CISC hardware decoders tend to be complex due to variable
length instructions, hence they occupy more chip space
• CISC instructions are slower due to many instructions with
memory accesses requiring many CPU clock cycles
• CISC instructions are microcoded as opposed to hardwired,
hence take up more chip space and are slower.
• CISC require more power, hence they are less suitable for low
voltage applications.
 Computer Programs Topic 7 - 7.22

Do You Know?
John Cocke devised the concept of the
reduced instruction set computer
(RISC). In 1970s he recognized that
compilers could better optimize the
simpler instructions of RISC hardware,
resulting in high-performance
computers. While the instruction sets of
Re:
most computers were becoming ever
[Link]
rofile/john-cocke/
more complex, Cocke's philosophy went
against the prevailing wisdom, but has
proven to be very successful with faster
CPUs. The RISC design philosophy is
now used in nearly every computational
device made, especially mobile devices.
 Computer Programs Topic 7 - 7.23

Context switching
Context switching is required when program control is re-
directed to a different address location temporarily, e.g.,
on external interrupt. The current context must be saved,
the new context is activated. On return, the old context
will replace the current context which may have to be
saved in return. Also used in multi-tasking.
Program context is defined by:
• PC register content (i.e. next instruction address)
• Status register content
• Additional register value(s)
 Computer Programs Topic 7 - 7.24

The stack
Hardware stack registers are used to save and restore
program context when program control is changed and
restored as the CPU instructions are executed.

HW Stack

PUSH POP
AX Register
SR Register
Last in, first
PC Register
out (LIFO)
 Computer Programs Topic 7 - 7.25

Interrupts
Interrupts are external (to CPU) events which forces the
value of the PC register to change, i.e. address re-
direction. Before the next address value is changed, the
current program context is saved as shown before.

Interrupt vectors
External
Timer int. handler addr. Handler
Interrupt
Serial IO int. handler addr. address to
User int. handler addr. PC reg.
Instruction set and assembly
Computer Programs Topic 7 - 7.26

language
CPU instructions are represented as assembly-level instructions
in an assembly language. An assembler is used to convert the
assembly language into CPU instructions in binary form.
Assembly language programming is used to produce a more
efficient and compact code than can be produced by high-level (e.g.
Java, C, VB) language compilers.
Assembly language programming is required when some very
specific CPU instructions are required that cannot be produced by
the compilers.
However, assembly language programming is more time-
consuming and requires intimate knowledge of the CPU
architecture and instructions.
Instruction set and assembly
Computer Programs Topic 7 - 7.27

language – some examples

A = 20 MOV #20, R02

B = A + 6 MOV R02, R03

ADD #6, R03
MOV R03, R01

if A == 10 then CMP #10, R02

B = 3 JNE $L1
end if MOV #3, R01
A = B L1: MOV R01, R02

while A < 5 L0: CMP #5, R02

A = A + 1 JGE $L1
wend ADD #1, R02
B = A JMP $L0
L1: MOV R02, R01
Instruction set and assembly
Computer Programs Topic 7 - 7.28

language – some examples

MOV #20, R02 0000: 000000140102
MOV R02, R03 0000: 0001020103
ADD #6, R03 0005: 100000060103
MOV R03, R02 0011: 0001030101
CMP #10, R02 0000: 2F00000A0102
JNE $L1 0006: 1E020010
MOV #3, R01 0010: 000000030101
L1: MOV R01, R02 0016: 0001010102
L0: CMP #5, R02 0000: 2F0000050102
JGE $L1 0006: 20020014
ADD #1, R02 0010: 100000010102
JMP $L0 0016: 1C020000
L1: MOV R02, R01 0020: 0001020101
Instruction set and assembly
Computer Programs Topic 7 - 7.29

language - Subroutines
Subroutines are used to write structured and more compact
program code. For example, consider a set of code that needs
executing many times in different parts of a program. How would you
do this?
Repeat the same set of code many times, i.e., a cut & paste job?

Consider the effect of the above quick job on the size of the
resultant program!
The resultant program size will grow each time you paste the same
set of code. Consider the code below:

a = a + 1
b = a * 2
writeln(a, “:”, b)
Instruction set and assembly
Computer Programs Topic 7 - 7.30

language - Subroutines
program UglyOne program NiceOne
var a integer var a integer
var b integer var b integer
a = a + 1 sub disp-data
b = a * 2 a = a + 1
writeln(a, “:”, b) b = a * 2
a = a + 1 writeln(a, “:”, b)
b = a * 2 end sub
writeln(a, “:”, b)
disp-data
a = a + 1 disp-data
b = a * 2 disp-data
writeln(a, “:”, b) end
end
Instruction set and assembly
Computer Programs Topic 7 - 7.31

language - Subroutines
Program UglyOne repeats the same 3 lines of code three times in a
sequential manner.
Program NiceOne puts the 3 lines of code in a subroutine and “calls”
this subroutine 3 times. Each such call will require a single statement
which is 2 less than the repeated lines!

We can improve further on this – can you guess how?

Consider repeating the same 3 lines 10

for n = 1 to 3 times. This will add 30 lines to the program.
disp-data Using the loop will add only 3 lines! If we
next need to repeat 1000 times, the loop will still
only add 3 lines!
Instruction set and assembly
Computer Programs Topic 7 - 7.32

language - Subroutines
However, there is one problem with calling the subroutine which
would not exist if all the code is only sequentially executed.

The subroutine code is in a different location than the calling code.

The CPU will have to locate the subroutine and then find its way
back to the statement after the calling statement if the program is
to run as expected.

This requires that the address of the statement after the calling
statement has to be saved somewhere so that the CPU can come
back to it once it finishes executing the subroutine code!

Enter the program stack! What sort of data structure is a stack?

Instruction set and assembly
Computer Programs Topic 7 - 7.33

language - Subroutines
So, how is subroutine call done in assembly language level?
add_numbers: The label “add_numbers” marks the start of
ADD R01, R02 the subroutine and the instruction RET marks
RET
the end of the subroutine.
Start_of_prog:
MOV #2, R01 The instruction MSF makes room on the
MOV #5, R02 stack for the return address from the
MSF subroutine.
CAL $add_numbers
MOV R02, R03 The CAL instruction puts the return address
end_of_prog: on the stack and jumps to the subroutine.
HLT
The RET instruction takes the return address
The two numbers to add from top of the stack and jumps to that
need to be in registers R01
address.
and R02 in this case.
Instruction set and assembly
Computer Programs Topic 7 - 7.34

language - Subroutines
01: program NiceOne
Program starts at line 10. What happens at
02: var a integer line 11? What happens at line 8? Consider
03: var b integer what would happen if the CPU did not
04: sub disp-data remember where to come back to after it
finished executing the subroutine!
05: a = a + 1
06: b = a * 2 At line 11, CPU saves line 12 as
07: writeln(a, “:”, b) the line it has to come back to. It
then goes to line 5. At line 8 it
08: end sub recalls that line 12 is where it
09: should go to next.
10: writeln(“Start of program”)
Where is line 12
11: disp-data saved and how is it
12: writeln(“End of program”) recalled?
13: end
Instruction set and assembly
Computer Programs Topic 7 - 7.35

language - Subroutines
PC: 10 PC: 11 TOS: PC: 04 PC: 05 PC: 06
Start of Start of
program
BOS: 12 sub
PC: 07 PC: 08 TOS: PC: 12 PC: 13
End of End of
sub program
This is a simple case but consider the case where the subroutine
itself calls another subroutine and so forth! As the CPU returns from
each subroutine it recalls the return addresses from the stack in the
right order, i.e., last in first out!
Top of stack - TOS
TOS: Bottom of stack - BOS
: 18 TOS:
: 36 : 36 TOS:
BOS: 45 BOS: 45 BOS: 45 TOS:
Instruction set and assembly
Computer Programs Topic 7 - 7.36

language - Subroutines
We wish to change the code so that we can increment a variable
other than by a fixed value making our code more flexible. Can you
suggest what architectural change is needed?

We use parameters for this. We pass parameters to subroutines.

Parameters are a kind of ‘placeholders’ for the actual values that are
passed.

The good thing about assembly-level programming is that the

programmer is close to the hardware and has much more control of
it than the high-level programmer has.
Instruction set and assembly
Computer Programs Topic 7 - 7.37

language - Subroutines
01: program NiceOne
At line 4, the subroutine
02: var a integer receives a parameter which
03: var b integer is used to increment the
04: sub disp-data(incval) value of a. At line 11, the
05: a = a + incval call to this subroutine
specifies the value of 2 as
06: b = a * 2
the parameter, i.e. “incval”
07: writeln(a, “:”, b) is set to 2 at entering the
08: end sub subroutine.
09:
10: writeln(“Start of program”)
11: disp-data(2)
12: writeln(“End of program”)
13: end
Instruction set and assembly
Computer Programs Topic 7 - 7.38

language - Subroutines
PC: 10 PC: 11 TOS: PC: 04 TOS: PC: 05
Start of 2 Start of BOS: 12
program sub
BOS: 12

PC: 06 PC: 07 PC: 08 TOS: PC: 12 PC: 13

End of End of
sub program

The parameters are passed on the stack. The calling program puts
the parameter values on the stack and the subroutine takes the
values off the stack. Stack is a very versatile data structure!
Instruction set and assembly
Computer Programs Topic 7 - 7.39

language - Subroutines
So, how is parameter passing done at assembly language level?
add_numbers: The two values are passed by putting the
POP R01 numbers on the stack using the PSH
POP R02
ADD R01, R02
instructions before the CAL instruction.
MOV R02, R00 The subroutine takes the two values on
RET
the stack by the POP instructions and
Start_of_prog: moved into registers R01 and R02.
MSF The ADD instruction adds the two
PSH #2
PSH #5
numbers and the MOV instruction puts
CAL $add_numbers the result in the R00 register.
MOV R00, R03 Is there another way of returning the
end_of_prog:
result?
HLT
Instruction set and assembly
Computer Programs Topic 7 - 7.40

language – Indirect addressing

Suppose we need to count the number of characters in a string
stored in memory. This string ends with a single byte of zero.
Let’s assume that the string starts at address location 1000 and
ends at address location 1002. LDB – load byte
LDB 1000, R02 MOV #1000, R01 The first attempt uses direct
CMP #0, R02 Loop: addressing. This is not efficient
JEQ $L0 LDB @R01, R02 or economical as it repeats the
ADD #1, R03 CMP #0, R02 same sequence of code 3 times.
LDB 1001, R02 JEQ $L0
CMP #0, R02 ADD #1, R03
JEQ $L0 JMP $Loop The second method uses
ADD #1, R03 L0: indirect addressing, i.e. the
LDB 1002, R02 The symbol ‘@’
address is in a register. It is
CMP #0, R02 indicates indirect flexible and much easier to do
JEQ $L0 addressing. with less code.
 Computer Programs Topic 7 - 7.41

Quiz time 
1. Give 3 examples of typical CPU operations
2. Explain what an instruction's operand is
3. Where do the instructions' operands reside?
4. CPU registers are fast memories. What are they used for?
5. A number's address in memory is in a register. What
addressing mode is used to locate it?
6. What are the two ways of passing parameters values to
subroutines?
7. Explain why RISC ISA prefers to use simple instructions
8. Explain the role of the stack in subroutine calls
9. Explain the role of context switching when two programs
compete for the CPU time.
 Computer Programs Topic 7 - 7.42

Topic Summary
• Computer programs are made of a series of instructions that
the CPU can fetch from memory, decode and execute.
Instructions contain the operations and the data or the
locations of data they operate on. CPU instructions are coded
in assembly language that is human readable.
• Instruction set architecture (ISA) defines the format of
instructions, how data is located and the results of operations
on data. CICS and RISC utilise two types of instructions with
different ISAs, where RISC ISA is becoming more popular
amongst CPU designers.
• CPU event interrupts and calls to subroutines use special
instructions where the CPU is re-direct to branch from its
current path, saving the return address on the stack.
 Computer Programs Topic 7 - 7.43

References
 Null, L. and Lobur, J. (2014) The Essentials of
Computer Organization and Architecture. Fourth
edition. Jones and Bartlett Publishers, Inc.
 Englander, I. (2014) The Architecture of Computer
Hardware and Systems Software. 5th Edition. John
Wiley.
 Harris, S.L. and Harris, D.M. (2016) Digital Design
and Computer Architecture – ARM edition. Morgan
Kaufmann.
Topic 7 – Computer Programs

Any Questions?