Module-3
Arithmetic Unit
Text Books
Computer Organization: C Hamacher, Z Vranesic, S Zaky:, Tata McGraw Hill, 5th Edition,
2011 .
Dr. Bhat Geetalaxmi Jairam
Professor,
ISE, NIE, Mysuru
Multiplication of Positive numbers
Multiplication of Positive numbers
Full Adder TT
Multiplication of Positive numbers
• The product of two n-digit numbers can be accommodated in 2n digits, so the product of the
two 4-bit numbers in this example fits into 8 bits.
• If the multiplier bit is 1, the multiplicand is entered in the appropriate position to be added to
the partial product If the multiplier bit is 0, then Os are entered, as in the third row of the
example.
• The main component in each cell is a full adder FA. The AND gate in each cell determines
whether a multiplicand bit, mj is added to the incoming partial-product bit, based on the value
of the multiplier bit, q;. Each row i, where 0 <= i >= 3, adds the multiplicand (appropriately
shifted) to the incoming partial product, PPi, to generate the outgoing partial product, PP(i +
1),if qj = 1.
• If qj = 0, PPi is passed vertically downward unchanged. PP0 is all 0s, and PP4 is the desired
product. The multiplicand is shifted left one position per row by the diagonal signal path.
• The worst case signal propagation delay path is from the upper right comer of the array
to the high-order product bit output at the bottom left comer of the array.
Multiplication of Positive numbers
• The simplest way to perform multiplication is to use the adder circuitry in the
ALU for a number of sequential steps .
• The block diagram in Figure 6.1a shows the hardware arrangement for sequential
multiplication. This circuit performs multiplication by using a single n-bit adder n
times to implement the spatial addition performed by the n rows of ripple-carry
adders of Figure 6.6b. Registers A and Q combined hold PPi while multiplier bit q;
generates the signal Add/No add.
• This signal controls the addition of the multiplicand, M, to PPi to generate PP(i +
l). The product is computed in n cycles. The partial product grows in length by one
bit per cycle from the initial vector, PPO, of n Os in register A.
• The carry-out from the adder is stored in flip-flop C, shown at the left end of
register A. At the start, the multiplier is loaded into register Q, the multiplicand into
register M, and C and A are cleared to 0. At the end of each cycle, C, A, and Q are
shifted right one bit position to allow for growth of the partial product as the
multiplier is shifted out of register Q
Multiplication of Positive numbers
Multiplication of Positive numbers
Multiplication of Positive numbers
• Because of this shifting, multiplier bit q; appears at the LSB
position of Q to generate the Add/No add signal at the correct
time, starting with q0 during the first cycle; q1 during the
second cycle, and so on. After they are used, the multiplier bits
are discarded by the right-shift operation. Note that the
• carry-out from the adder is the leftmost bit of PP(i + 1), and it
must be held in the C
• flip-flop to be shifted right with the contents of A and Q. After
n cycles, the high-order half of the product is held in register A
and the low-order half is in register Q. The multiplication
example of Figure 6.6a is shown in Figure 6.7b as it would be
performed by this hardware arrangement.
Multiplication of Positive numbers
• Using this sequential hardware structure, it is clear that a Multiply
instruction takes much more time to execute than an Add instruction.