BASIC OPERATIONAL CONCEPT
7.2 Execution of Complete Instruction
Actions required for execution of instruction ADD (R3), R1 and the control
sequence of it.
Action required
BASIC OPERATIONAL CONCEPT
7.2 Execution of Complete Instruction
Control Sequence
BASIC OPERATIONAL CONCEPT
7.2.1 BRANCH INSTRTUCTIONS
• A branch instruction replaces the contents of the PC with the branch target
address. This address is usually obtained by adding an offset X, which is given
in the branch instruction, to the updated value of the PC.
• Figure 7.7 gives a control sequence that implements an unconditional branch
instruction.
• Processing starts, as usual, with the fetch phase. This phase ends when the
instruction is loaded into the IR in step 3
• . The offset value is extracted from the IR by the instruction decoding circuit,
which will also perform sign extension if required. Since the value of the updated
PC is already available in register Y, the offset X is gated onto the bus in step 4, and
an addition operation is performed. The result, which is the branch target address, is
loaded into the PC in step 5.
• The offset X used in a branch instruction is usually the difference between the
branch target address and the address immediately following the branch instruction.
BASIC OPERATIONAL CONCEPT
7.2.1 BRANCH INSTRTUCTIONS
• For example, if the branch instruction is at location 2000 and if the branch target
address is 2050, the value of X must be 46. The reason for this can be readily
appreciated from the control sequence in Figure 7.7. The PC is incremented during
the fetch phase, before knowing the type of instruction being executed. Thus, when
the branch address is computed in step 4, the PC value used is the updated value,
which points to the instruction following the branch instruction in the memory.
• Consider now a conditional branch. In this case, we need to check the status of
the condition codes before loading a new value into the PC. For example, for a
Branch-onnegative (Branch<0 instruction), step 4 in Figure 7.7 is replaced with
BASIC OPERATIONAL CONCEPT
7.2.1 BRANCH INSTRTUCTIONS
Multiple Bus Organization
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Multiple Bus Organization
• We used the simple single-bus structure of Figure 7.l to illustrate the basic ideas.
The resulting control sequences in Figures 7.6 and 7.7 are quite long because only
one data item can be transferred over the bus in a clock cycle. To reduce the
number of steps needed, most commercial processors provide multiple internal
paths that enable several transfers to take place in parallel.
• Figure 7.8 depicts a three-bus structure used to connect the registers and the ALU
of a processor. All general-purpose registers are combined into a single block
called the register file. The register file in Figure 7.8 is said to have three ports.
There are two outputs, allowing the contents of two different registers to be
accessed simultaneously and have their contents placed on buses A and B. The
third port allows the data on bus C to be loaded into a third register during the
same clock cycle.
• Buses A and B are used to transfer the source operands to the A and B inputs of
the ALU, where an arithmetic or logic operation may be performed. The result is
transferred to the destination over bus C. If needed, the ALU may simply pass one
of its two input operands unmodified to bus C. We will call the ALU control signals
for such an operation R=A or R=B. The three-bus arrangement obviates the need
for registers Y and Z in Figure 7.l.
Multiple Bus Organization
• It has Incrementer unit, which is used to increment the PC by 4. Using the
Incrementer eliminates the need to add 4 to the PC using the main ALU, as was
done in Figures 1.6 and 7.7. The source for the constant 4 at the ALU input
multiplexer is still useful. It can be used to increment other addresses, such as the
memory addresses in LoadMultiple and StoreMultiple instructions.
Multiple Bus Organization
Control sequence for the instruction Add R4,R5,R6 for the three-bus organization
• In step 1, the contents of the PC are passed through the ALU, using the R=B control
signal, and loaded into the MAR to start a memory read operation. At the same
time the PC is incremented by 4. Note that the value loaded into MAR is the
original contents of the PC. The incremented value is loaded into the PC at the end
of the clock cycle and will not affect the contents of MAR. Instep 2, the processor
waits for MFC and loads the data received into MDR, then transfers them to IR in
step 3. Finally, the execution phase of the instruction requires only one control
step to complete, step 4.
• By providing more paths for data transfer a significant reduction in the number of
clock cycles needed to execute an instruction is achieved.